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1. 发明授权

US08994114B1 Performance enhancement of active device through reducing parasitic conduction 有权
标题翻译：通过减少寄生导通来提高有源器件的性能
公开(公告)号：US08994114B1
公开(公告)日：2015-03-31
申请号：US14078848
申请日：2013-11-13
申请人： M/A-COM Technology Solutions Holdings, Inc.
发明人： Jonathan Leckey , Lyndon Pattison , Andrew Patterson , Timothy E. Boles
IPC分类号： H01L21/70 , H01L21/339 , H01L29/78 , H01L29/20 , H01L29/66
CPC分类号： H01L29/2003
摘要： An apparatus having an active device, a plurality of traces and one or more areas is disclosed. The active device may have a channel layer. A buffer layer is generally disposed between the channel layer and a substrate. A parasitic layer may be formed at an interface between the buffer layer and the substrate. The traces may be connected to the active device. The areas are generally proximate at least one of (i) the active device and (ii) at least two of the traces from which the parasitic layer is removed.
摘要翻译：公开了一种具有有源器件，多个迹线和一个或多个区域的器件。有源设备可以具有信道层。缓冲层通常设置在沟道层和衬底之间。可以在缓冲层和衬底之间的界面处形成寄生层。迹线可能连接到有源器件。这些区域通常接近（i）有源器件和（ii）去除寄生层的迹线中的至少两个中的至少一个。

2. 发明授权

US08927355B2 Method of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08927355B2
公开(公告)日：2015-01-06
申请号：US13304936
申请日：2011-11-28
申请人： Doo-Young Lee , Ki Il Kim , Myeong-Cheol Kim , Do-Hyoung Kim , Do-Hsing Lee
发明人： Doo-Young Lee , Ki Il Kim , Myeong-Cheol Kim , Do-Hyoung Kim , Do-Hsing Lee
IPC分类号： H01L21/339 , H01L21/768 , H01L29/78 , H01L29/66
CPC分类号： H01L29/78 , H01L21/76829 , H01L21/76832 , H01L21/76895 , H01L21/76897 , H01L29/66545
摘要： A method of manufacturing a semiconductor device, including the second sacrificial layer receiving a gate structure include a metal and a spacer on a sidewall of the gate structure therethrough being formed on a substrate. The second sacrificial layer is removed. A second etch stop layer and an insulating interlayer are sequentially formed on the gate structure, the spacer and the substrate. An opening passing through the insulating interlayer is formed to expose a portion of the gate structure, a portion of the spacer and a portion of the second etch stop layer on a portion of the substrate. The second etch stop layer being exposed through the opening is removed. The contact being electrically connected to the gate structure and the substrate and filling the opening is formed. The semiconductor device having the metal gate electrode and the shared contact has a desired leakage current characteristic and resistivity characteristics.
摘要翻译：包括接收栅极结构的第二牺牲层的半导体器件的制造方法包括在基板上形成的栅极结构的侧壁上的金属和间隔物。去除第二牺牲层。在栅极结构，间隔物和衬底上依次形成第二蚀刻停止层和绝缘中间层。形成通过绝缘中间层的开口以暴露栅极结构的一部分，间隔物的一部分和第二蚀刻停止层的一部分在衬底的一部分上。去除通过开口露出的第二蚀刻停止层。形成与栅极结构和基板电连接并填充开口的触点。具有金属栅电极和共用触点的半导体器件具有期望的漏电流特性和电阻率特性。

3. 发明授权

US08803247B2 Fin-type field effect transistor 有权
标题翻译：鳍型场效应晶体管
公开(公告)号：US08803247B2
公开(公告)日：2014-08-12
申请号：US13326429
申请日：2011-12-15
申请人： Chih-Jung Wang , Tong-Yu Chen
发明人： Chih-Jung Wang , Tong-Yu Chen
IPC分类号： H01L27/148 , H01L29/66 , H01L29/00 , H01L27/088 , H01L21/339 , H01L21/00 , H01L21/84 , H01L21/338 , H01L21/337 , H01L21/336 , H01L21/8234
CPC分类号： H01L27/1211 , H01L21/845
摘要： A fin-type field effect transistor including at least one fin-type semiconductor structure, a gate strip and a gate insulating layer is provided. The fin-type semiconductor structure is doped with a first type dopant and has a block region with a first doping concentration and a channel region with a second doping concentration. The first doping concentration is larger than the second doping concentration. The blocking region has a height. The channel region is configured above the blocking region. The gate strip is substantially perpendicular to the fin-type semiconductor structure and covers above the channel region. The gate insulating layer is disposed between the gate strip and the fin-type semiconductor structure.
摘要翻译：提供了包括至少一个鳍式半导体结构，栅极条和栅极绝缘层的鳍式场效应晶体管。翅片型半导体结构掺杂有第一种掺杂剂并具有具有第一掺杂浓度的阻挡区和具有第二掺杂浓度的沟道区。第一掺杂浓度大于第二掺杂浓度。阻挡区域具有高度。通道区域被配置在阻塞区域之上。栅极条基本上垂直于鳍状半导体结构并且覆盖在沟道区域上方。栅极绝缘层设置在栅极条和鳍状半导体结构之间。

4. 发明授权

US08703548B2 Method of forming top electrode for capacitor and interconnection in integrated passive device (IPD) 有权
标题翻译：在集成无源器件（IPD）中形成电容器和互连顶电极的方法
公开(公告)号：US08703548B2
公开(公告)日：2014-04-22
申请号：US13765478
申请日：2013-02-12
申请人： STATS ChipPAC, Ltd.
发明人： Yaojian Lin , Robert C. Frye
IPC分类号： H01L21/339
CPC分类号： H01L28/40 , H01L23/5223 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2924/01079 , H01L2924/14 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105
摘要： A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.
摘要翻译：一种制造半导体器件的方法包括提供具有设置在基板的顶表面上的第一导电层的基板。在基板和第一导电层上形成高电阻率层。介电层沉积在衬底，第一导电层和高电阻率层上。介电层，高电阻率层和第一导电层的一部分形成电容器叠层。在电介质层上形成第一钝化层。在电容器堆叠和第一钝化层的一部分上形成第二导电层。在电介质层中蚀刻第一开口以暴露高电阻率层的表面。在电介质层中的第一开口和第一钝化层的一部分上沉积第三和第四导电层。

5. 发明授权

US08697500B2 Method for manufacturing solid-state image sensor 有权
标题翻译：固态图像传感器的制造方法
公开(公告)号：US08697500B2
公开(公告)日：2014-04-15
申请号：US13276753
申请日：2011-10-19
申请人： Junji Iwata
发明人： Junji Iwata
IPC分类号： H01L21/339 , H01L21/00
CPC分类号： H01L27/14612 , H01L27/1461 , H01L27/14641 , H01L27/14689
摘要： A method for manufacturing a solid-state image sensor includes forming a gate electrode structure including a gate electrode on a gate insulating film formed on a semiconductor substrate, and implanting ions into a first region and simultaneously implanting the ions into a second region of the semiconductor substrate via the gate electrode structure and the gate insulating film, wherein the first region is a region where a charge accumulation region is to be formed, and the second region is a region where an extended region that extends from the charge accumulation region to a portion below the gate electrode is to be formed, and a mean projected range of the ions in the step of simultaneous implanting of the ions into the first region and the second region is larger than a sum total of thicknesses of the gate electrode and the gate insulating film.
摘要翻译：固态图像传感器的制造方法包括：在形成于半导体基板上的栅极绝缘膜上形成包括栅电极的栅电极结构，将离子注入第一区域，同时将离子注入半导体的第二区域通过栅极电极结构和栅极绝缘膜的衬底，其中第一区域是要形成电荷聚集区域的区域，并且第二区域是从电荷累积区域延伸到部分的区域在栅极电极下方形成，同时将离子注入第一区域和第二区域的步骤中的离子的平均投射范围大于栅极电极和栅极绝缘体的厚度的总和电影。

6. 发明授权

US08551821B2 Enhancement normally off nitride semiconductor device manufacturing the same 有权
标题翻译：增强通常关闭氮化物半导体器件制造相同
公开(公告)号：US08551821B2
公开(公告)日：2013-10-08
申请号：US12960499
申请日：2010-12-04
申请人： Jung Hee Lee , Ki Sik Im , Jong Bong Ha
发明人： Jung Hee Lee , Ki Sik Im , Jong Bong Ha
IPC分类号： H01L21/335 , H01L21/8232 , H01L21/339 , H01L21/00 , H01L21/84
CPC分类号： H01L29/7787 , H01L29/1033 , H01L29/2003 , H01L29/517 , H01L29/66462
摘要： The present invention relates to an enhancement normally off nitride semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a buffer layer on a substrate; forming a first nitride semiconductor layer on the buffer layer; forming a second nitride semiconductor layer on the first nitride semiconductor layer; etching a gate region above the second nitride semiconductor layer up to a predetermined depth of the first nitride semiconductor layer; forming an insulating film on the etched region and the second nitride semiconductor layer; patterning a source/drain region, etching the insulating film in the source/drain region, and forming electrodes in the source/drain region; and forming a gate electrode on the insulating film in the gate region. In this manner, the present invention provides a method of easily implementing a normally off enhancement semiconductor device by originally blocking 2DEG which is generated under a gate region. In addition, the present invention provides an enhancement normally off power semiconductor device with a simple and efficient driving circuit in a HEMT device.
摘要翻译：本发明涉及一种增强常关氮化物半导体器件及其制造方法。该方法包括以下步骤：在衬底上形成缓冲层; 在所述缓冲层上形成第一氮化物半导体层; 在所述第一氮化物半导体层上形成第二氮化物半导体层; 将第二氮化物半导体层上方的栅极区域蚀刻到第一氮化物半导体层的预定深度; 在蚀刻区域和第二氮化物半导体层上形成绝缘膜; 图案化源极/漏极区域，蚀刻源极/漏极区域中的绝缘膜，以及在源极/漏极区域中形成电极; 以及在栅极区域的绝缘膜上形成栅电极。以这种方式，本发明提供了一种通过最初阻挡在栅极区域下产生的2DEG来容易地实现常关的增强型半导体器件的方法。此外，本发明提供了一种在HEMT装置中具有简单有效的驱动电路的增强型常关功率半导体器件。

7. 发明授权

US08377758B2 Thin film transistor, array substrate and method for manufacturing the same 有权
标题翻译：薄膜晶体管，阵列基板及其制造方法
公开(公告)号：US08377758B2
公开(公告)日：2013-02-19
申请号：US13242468
申请日：2011-09-23
申请人： Xinxin Li , Wei Wang , Chunping Long
发明人： Xinxin Li , Wei Wang , Chunping Long
IPC分类号： H01L21/339 , H01L21/44
CPC分类号： H01L29/66765 , H01L29/41733
摘要： A thin film transistor for a thin film transistor liquid crystal display (TFT-LCD), an array substrate and manufacturing method thereof are provided. The thin film transistor comprises a source electrode, a drain electrode, and a channel region between the source electrode and drain electrode. A source extension region is connected with the source electrode, a drain extension region is connected with the drain electrode, and the source extension region is disposed opposite to the drain extension region to form a channel extension region therebetween.
摘要翻译：提供了一种用于薄膜晶体管液晶显示器（TFT-LCD）的薄膜晶体管，阵列基板及其制造方法。薄膜晶体管包括源电极，漏电极和源极和漏电极之间的沟道区。源极延伸区域与源极连接，漏极延伸区域与漏极电极连接，源极延伸区域与漏极延伸区域相对设置，以在它们之间形成沟道延伸区域。

8. 发明授权

US08319878B2 Solid-state imaging device and its production method 失效
标题翻译：固态成像装置及其制作方法
公开(公告)号：US08319878B2
公开(公告)日：2012-11-27
申请号：US12723086
申请日：2010-03-12
申请人： Takashi Terada , Keisuke Hatano
发明人： Takashi Terada , Keisuke Hatano
IPC分类号： H04N5/335 , H01L21/339 , H01L27/148
CPC分类号： H04N5/3728 , H01L27/14683 , H01L27/14806
摘要： A solid-state imaging device of the type having photoelectric conversion elements formed in a matrix pattern on a semiconductor substrate, vertical transfer elements each of which reads signal charges from the photoelectric conversion elements arranged in the column direction and transfers the signal charges in the vertical direction, and a horizontal transfer element which transfers in the horizontal direction the signal charges sent from each of the vertical transfer elements, the horizontal transfer element includes: a charge transfer channel; a first transfer electrode; a second transfer electrode; and an interelectrode insulating film; with the first transfer electrode and the second transfer electrode being at the same potential.
摘要翻译：一种具有在半导体基板上以矩阵图案形成的光电转换元件的类型的固态成像装置，每个从沿列方向布置的光电转换元件读取信号电荷的垂直传送元件，并将信号电荷传输到垂直方向水平传送元件，其在水平方向上传送从每个垂直传送元件发送的信号电荷，水平传送元件包括：电荷传输通道; 第一转移电极; 第二转移电极; 和电极间绝缘膜; 第一转印电极和第二转印电极处于相同的电位。

9. 发明授权

US08053287B2 Method for making multi-step photodiode junction structure for backside illuminated sensor 有权
标题翻译：背面照明传感器制作多步光电二极管结构的方法
公开(公告)号：US08053287B2
公开(公告)日：2011-11-08
申请号：US11537265
申请日：2006-09-29
申请人： Tzu-Hsuan Hsu , Dun-Nian Yaung
发明人： Tzu-Hsuan Hsu , Dun-Nian Yaung
IPC分类号： H01L21/339
CPC分类号： H01L27/14645 , H01L27/1464
摘要： A method of making a backside illuminated sensor is provided. A substrate is provided and a high energy ion implantation is performed over the substrate to implant a first doped region. A layer is formed over the substrate and a self-align high energy ion implantation is performed over the substrate to implant a second doped region over the first doped region. The combined thickness of the first and second doped region is greater than 50 percent of thickness of the substrate and the distance between back surface of the substrate and the first and second doped regions is less than 50 percent of thickness of the substrate. In this way, an enlarged light sensing region is formed through which electrons generated from back surface of the surface may easily reach the pixel.
摘要翻译：提供制造背面照明传感器的方法。提供衬底并且在衬底上执行高能离子注入以注入第一掺杂区域。在衬底上形成层，并在衬底上执行自对准高能离子注入，以在第一掺杂区域上注入第二掺杂区域。第一和第二掺杂区域的组合厚度大于衬底的厚度的50％，并且衬底的背表面与第一和第二掺杂区域之间的距离小于衬底厚度的50％。以这种方式，形成放大的光感测区域，通过该放大的光感测区域从表面的后表面产生的电子可以容易地到达像素。

10. 发明申请

US20110031376A1 SOLID-STATE IMAGE PICKUP ELEMENT, METHOD OF MANUFACTURING THE SAME, AND IMAGE PICKUP APPARATUS INCLUDING THE SAME 有权
标题翻译：固态图像拾取元件，其制造方法和包括其的图像拾取装置
公开(公告)号：US20110031376A1
公开(公告)日：2011-02-10
申请号：US12736569
申请日：2010-03-02
申请人： Itaru Oshiyama , Susumu Hiyama
发明人： Itaru Oshiyama , Susumu Hiyama
IPC分类号： H01L27/148 , H01L21/339
CPC分类号： H01L27/148 , H01L27/14621 , H01L27/14623 , H01L27/14627 , H01L27/14632 , H01L27/1464 , H01L27/14645 , H01L27/14685 , H01L27/14687
摘要： A solid-state image pickup element 1 is structured so as to include: a semiconductor layer 2 having a photodiode formed therein, photoelectric conversion being carried out in the photodiode; a first film 21 having negative fixed charges and formed on the semiconductor layer 2 in a region in which at least the photodiode is formed; and a second film 22 having the negative fixed charges, made of a material different from that of the first film 21 having the negative fixed charges, and formed on the first film 21 having the negative fixed charges.
摘要翻译：固态图像拾取元件1被构造成包括：其中形成有光电二极管的半导体层2，在光电二极管中执行光电转换; 在至少形成有光电二极管的区域中，在半导体层2上形成负固定电荷的第一膜21; 以及具有负固定电荷的第二膜22，其由具有负固定电荷的第一膜21的材料制成，并形成在具有负固定电荷的第一膜21上。

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