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1. 发明授权

US11239872B2 Signal receiver and method of measuring offset of signal receiver 有权
公开(公告)号：US11239872B2
公开(公告)日：2022-02-01
申请号：US17083602
申请日：2020-10-29
申请人： SK hynix Inc.
发明人： Joo-Hyung Chae , Dae Han Kwon
IPC分类号： H04L25/34 , H04L25/49 , H04B1/12 , H03K5/24 , H04B1/16 , H03K3/037 , H04L7/00 , H03K5/02
摘要： A signal receiver includes a first preliminary receiver circuit suitable for receiving an input signal and generating a first preliminary reception signal based on a first reference voltage, a second preliminary receiver circuit suitable for receiving the input signal and generating a second preliminary reception signal based on a second reference voltage, a reception circuit suitable for selecting one of the first preliminary reception signal and the second preliminary reception signal in response to a voltage level of a reception signal and generating the reception signal using the selected signal, and a reference voltage generation circuit suitable for adjusting a voltage level of the first reference voltage based on a first offset and adjusting a voltage level of the second reference voltage based on a second offset.

2. 发明授权

US10601573B2 Asynchronous digital communication module 有权
公开(公告)号：US10601573B2
公开(公告)日：2020-03-24
申请号：US16521257
申请日：2019-07-24
申请人： GMK CO. LTD.
发明人： Jin Soon Hwang , Jeong Woo Lee
IPC分类号： H04L25/34 , H04L7/00 , H04L5/16
摘要： Provided is a digital transmitting module included in a host device connectable to a client device. A digital transmitting module included in a host device connectable to a client device, the digital transmitting module may include: a clock generator which provides the host device with a clock whose one cycle is comprised of T1, T2, T3 and T4 connected sequentially, and a voltage encoder which receives the clock from the clock generator, receives a digital bit from the host device, generates a voltage pulse by encoding the digital bit based on the clock, and then transmits the voltage pulse to the client device.

3. 发明授权

US09967194B2 Network control system, control device, network information management method, and storage 有权
公开(公告)号：US09967194B2
公开(公告)日：2018-05-08
申请号：US15521735
申请日：2015-10-29
申请人： NEC CORPORATION
发明人： Masaharu Morimoto , Kazuya Suzuki , Yohei Iizawa
IPC分类号： H04L25/34 , H04L25/49 , H04L12/801 , H04L12/931 , H04L12/709 , G06F17/00 , H04L12/26
CPC分类号： H04L47/196 , G06F17/00 , H04L43/00 , H04L45/02 , H04L45/245 , H04L45/507 , H04L45/586 , H04L45/64 , H04L47/825 , H04L49/602 , H04L69/321
摘要： The objective of the invention is to enable sharing, between layers in a network in which the layers are used to perform communications, resource information and information required for using paths. A network control system includes: a lower layer information storage unit, a lower layer control information conversion unit, an upper layer information storage unit, an upper layer control information conversion unit, an integrated layer information storage unit and a layer integration unit. The layer integration unit integrates, as virtual links, the information of flows, which are representative of communications among terminals in the lower layer, with the network information of the upper layer, thereby constituting the network information of the integrated layer. Further, the layer integration unit performs reciprocal exchanges of network information among the integrated layer information storage unit, the lower layer information storage unit and the upper layer information storage unit, said reciprocal exchanges including a process of giving, as the attribute information of the ports of the upper layer, label information required for using the virtual link provided by the lower layer.

4. 发明授权

US09900078B2 Data processing method, apparatus, and device 有权
公开(公告)号：US09900078B2
公开(公告)日：2018-02-20
申请号：US15620041
申请日：2017-06-12
申请人： Huawei Technologies Co., Ltd.
发明人： Yiqun Wu , Shunqing Zhang , Yan Chen
IPC分类号： H04L25/34 , H04B7/06 , H04L1/02 , H04B7/0456
CPC分类号： H04B7/0689 , H04B7/0456 , H04L1/02
摘要： A data processing method, including performing, by a transmit end device, mapping processing on L layers of information bits to generate L layers of modulation symbol sequences, where each layer of modulation symbol sequence includes U modulation symbols, the L layers of modulation symbol sequences correspond to a same time-frequency resource, and the U modulation symbols include at least one non-zero modulation symbol and at least one zero modulation symbol, performing precoding processing on each layer of modulation symbol sequence according to a precoding matrix to generate L layers of modulation symbol sequence matrixes, and performing superposition processing on the L layers of modulation symbol sequence matrixes to generate a to-be-sent symbol sequence matrix, where the to-be-sent symbol sequence matrix includes T element sequences in a first dimension, and the to-be-sent symbol sequence matrix includes U element sequences in a second dimension.

5. 发明授权

US09553635B1 Time based equalization for a C-PHY 3-phase transmitter 有权
标题翻译：用于C-PHY三相发射机的基于时间的均衡
公开(公告)号：US09553635B1
公开(公告)日：2017-01-24
申请号：US14808272
申请日：2015-07-24
申请人： QUALCOMM Incorporated
发明人： Dhaval Sejpal , Chulkyu Lee , George Alan Wiley
IPC分类号： H04L25/34 , H04B3/54 , H04B3/462
CPC分类号： H04B3/54 , H04B3/462 , H04L7/0087 , H04L7/033 , H04L25/0286 , H04L25/14 , H04L25/4917
摘要： A method, an apparatus, and a computer program product for data communication over a multi-wire, multi-phase interface are provided. The method may include providing a sequence of symbols to be transmitted on a 3-wire interface, each symbol in the sequence of symbols defining one of three voltage states for each wire of the 3-wire interface, driving all wires of the 3-wire interface to a common voltage state during a transition from a first transmitted symbol to a second transmitted symbol, driving each wire of the 3-wire interface in accordance with the second transmitted symbol after a predetermined delay. Each wire may be in a different voltage state from the other wires of the 3-wire interface during transmission of the each symbol. The common voltage state may lie between two of the three voltage states.
摘要翻译：提供了一种用于通过多线，多相接口进行数据通信的方法，装置和计算机程序产品。该方法可以包括提供要在3线接口上发送的符号序列，符号序列中的每个符号定义3线接口的每根线的三种电压状态之一，驱动3线的所有线在从第一传输符号到第二传输符号的转变期间接合到公共电压状态，在预定延迟之后根据第二传输符号驱动3线接口的每条线。在每个符号的传输期间，每根导线可能处于与3线接口的其它线不同的电压状态。公共电压状态可以位于三个电压状态中的两个之间。

6. 发明授权

US09509344B1 Communication method based on bi-level binary digital baseband symbols 有权
标题翻译：基于双电平二进制数字基带符号的通信方法
公开(公告)号：US09509344B1
公开(公告)日：2016-11-29
申请号：US14840937
申请日：2015-08-31
申请人： HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
发明人： Peng Guo
IPC分类号： H04L25/34 , H04B1/04
CPC分类号： H04L25/493
摘要： The invention discloses a communication method using dual-level and binary digital baseband symbols which represents information by durations of a high level and a low level instead of by a high level and a low level in conventional digital baseband symbol design. In the invention, waveforms of a symbol 0 and a symbol 1 are determined according to durations of a high level and a low level, a transmitter generates a corresponding digital baseband signal in terms of a binary data to be transmitted according to the defined waveforms, and a receiver determines a symbol 0 or a symbol 1 according to waveform of a received digital baseband signal. The invention realizes bit synchronization of a receiver and a transmitter without extracting a bit synchronization clock from a received signal by the receiver, and a bit rate thereof is higher than that of Manchester under a same signal bandwidth.
摘要翻译：本发明公开了一种使用双电平和二进制数字基带符号的通信方法，其代表了传统数字基带符号设计中高电平和低电平的持续时间而不是高电平和低电平的信息。在本发明中，根据高电平和低电平的持续时间来确定符号0和符号1的波形，发送器根据定义的波形根据要发送的二进制数据产生对应的数字基带信号，并且接收机根据接收的数字基带信号的波形确定符号0或符号1。本发明实现接收机和发射机的比特同步，而不用接收机从接收到的信号中提取比特同步时钟，并且其比特率高于曼彻斯特在相同信号带宽下的比特率。

7. 发明授权

US09270507B2 Stacked comparator topology for multi-level signaling 有权
标题翻译：用于多级信令的堆叠比较器拓扑
公开(公告)号：US09270507B2
公开(公告)日：2016-02-23
申请号：US14162648
申请日：2014-01-23
申请人： Samsung Display Co., Ltd.
发明人： Mohammad Hekmat
IPC分类号： H04L25/34 , H04L27/06 , H03M5/20 , H04L25/49 , H04L25/06 , H04L25/03 , H03M1/00 , H03M1/36
CPC分类号： H04L27/06 , H03M1/002 , H03M1/361 , H03M5/20 , H04L25/03878 , H04L25/066 , H04L25/4917
摘要： A system and method for detecting signal levels in a multi-level signaling receiver. In one embodiment, a plurality of comparators, each including a differential pair, such as a differential pair of field-effect transistors (FETs) are assembled in a stacked configuration so that in some states current flows through FETs of the plurality of differential pairs in series, resulting in a reduction in power consumption.
摘要翻译：一种用于检测多级信令接收机中的信号电平的系统和方法。在一个实施例中，每个包括差分对（例如差分对的场效应晶体管（FET））的多个比较器以堆叠配置组装，使得在一些状态下，电流流过多个差分对的FET 系列，导致功耗降低。

8. 发明授权

US09184841B2 Multi-level decoder with skew correction 有权
标题翻译：具有偏斜校正的多级解码器
公开(公告)号：US09184841B2
公开(公告)日：2015-11-10
申请号：US14020399
申请日：2013-09-06
申请人： Avago Technologies General IP (Singapore) Pte. Ltd.
发明人： Mike Allen Robinson , David W. Dolfi
IPC分类号： H04L25/34 , H04L25/49 , H04B10/2507 , H04B10/60
CPC分类号： H04B10/2507 , H04B10/541 , H04B10/60 , H04B10/69
摘要： An optical communication system, a transmitter, a receiver, and methods of operating the same are provided. In particular, a transmitter is disclosed as being configured to encode optical signals in accordance with a multi-level coding scheme. The receiver is configured to provide skew correction to the optical signals received from the transmitter by dividing a received signal into separate level-specific components and sampling each of the components with distinct sampling blocks.
摘要翻译：提供光通信系统，发射机，接收机及其操作方法。特别地，发射机被公开为被配置为根据多电平编码方案对光信号进行编码。接收机被配置为通过将接收到的信号分成单独的电平特定分量并且对具有不同采样块的每个分量进行采样来向从发射机接收的光信号提供偏斜校正。

9. 发明授权

US08958498B1 Method of generating driving signal for driving dual mode supply modulator for power amplifier and device thereof 有权
标题翻译：产生用于驱动功率放大器的双模式电源调制器的驱动信号的方法及其装置
公开(公告)号：US08958498B1
公开(公告)日：2015-02-17
申请号：US14267262
申请日：2014-05-01
申请人： Sung Jun Lee , Jae Ho Jung , Kwangchun Lee
发明人： Sung Jun Lee , Jae Ho Jung , Kwangchun Lee
IPC分类号： H04L25/34 , H04L25/49
CPC分类号： H03F3/245 , H03F1/025 , H03F3/195 , H03F2200/102 , H03F2200/331 , H03F2200/336 , H03F2200/511 , H03F2200/78 , H03M7/3004
摘要： Provided is a method of generating a driving signal for driving a dual mode supply modulator for a power amplifier. The method includes obtaining an envelope of a complex baseband signal to be transmitted, comparing the envelope of the complex signal with a preset threshold value, when a current envelope of the complex signal is the preset threshold value or greater or when there is a result having the preset threshold value or greater in previous N comparisons, outputting a digital board output signal configured with a first logic level through a digital-to-analog converter; and when the current envelope of the complex signal is smaller than the preset threshold value and when there is no result having the preset threshold value or greater in the previous N comparisons, outputting a digital board output signal configured with a second logic level through the digital-to-analog converter.
摘要翻译：提供了一种产生用于驱动功率放大器的双模式电源调制器的驱动信号的方法。该方法包括当复数信号的当前包络是预设阈值或更大时获得要发送的复基带信号的包络，将复数信号的包络与预设阈值进行比较，或者当具有在先前的N比较中预设的阈值或更大，通过数模转换器输出配置有第一逻辑电平的数字板输出信号; 并且当复信号的当前包络小于预设阈值时，并且当在先前N次比较中没有具有预设阈值或更大值的结果时，通过数字信号输出配置有第二逻辑电平的数字板输出信号模拟转换器。

10. 发明授权

US08873668B2 Communications arrangement for a system in package 有权
标题翻译：一个系统的通讯安排
公开(公告)号：US08873668B2
公开(公告)日：2014-10-28
申请号：US13651883
申请日：2012-10-15
申请人： STMicroelectronics SA , STMicroelectronics (R&D) Ltd , STMicroelectronics (Grenoble 2) SAS
发明人： Andrew Ferris , Ignazio Antonino Urzi , Pascal Teissier
IPC分类号： H04L25/34
CPC分类号： G06F13/423
摘要： A circuit includes a first n-bit communications block and a second m-bit communications block. A controller is configured to control mode of operation for the first and second communications blocks. In a first mode, the first and second communications blocks function as a single communications block for n+m bit communications. In a second mode, the first and second communications blocks operate as substantially independent communications block for n bit communications and m bit communications.
摘要翻译：电路包括第一n比特通信块和第二m比特通信块。控制器被配置为控制第一和第二通信块的操作模式。在第一模式中，第一和第二通信块用作n + m位通信的单个通信块。在第二模式中，第一和第二通信块作为用于n位通信和m位通信的基本上独立的通信块来操作。

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