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71. 发明授权

US08797786B2 Static RAM 有权
标题翻译：静态RAM
公开(公告)号：US08797786B2
公开(公告)日：2014-08-05
申请号：US13226726
申请日：2011-09-07
申请人： Shinichi Moriwaki
发明人： Shinichi Moriwaki
IPC分类号： G11C11/00 , G11C11/413 , G11C11/412 , G11C11/41 , G11C11/418 , G11C8/08 , G11C11/419 , G11C7/18 , G11C8/14
CPC分类号： G11C11/413 , G11C7/18 , G11C8/08 , G11C8/14 , G11C11/41 , G11C11/412 , G11C11/418 , G11C11/419
摘要： A static RAM includes a plurality of word lines, a plurality of global bit line pairs, a plurality of static-type memory cells, a plurality of sense amplifiers, a plurality of local bit line pairs provided in correspondence with each global bit line pair, and a plurality of global switches, wherein the plurality of static-type memory cells is connected to the corresponding local bit line pair in response to a row selection signal, and at the time of read, the row selection signal is applied to the word line and after the corresponding local bit line pair is brought into a state corresponding to contents stored in the memory cell, application of the row selection signal is stopped and then the corresponding global switch is brought into a connection state and after changing the state of the global bit line pair, the corresponding sense amplifier is operated.
摘要翻译：静态RAM包括多个字线，多个全局位线对，多个静态型存储单元，多个读出放大器，与每个全局位线对对应地提供的多个局部位线对，以及多个全局开关，其中响应于行选择信号将多个静态型存储单元连接到对应的本地位线对，并且在读取时，行选择信号被施加到字线并且在对应的本地位线对进入与存储单元中存储的内容相对应的状态之后，停止施加行选择信号，然后将相应的全局开关变为连接状态，并且在改变全局的状态之后位线对，相应的读出放大器工作。

72. 发明申请

US20140085965A1 COLUMN SELECT MULTIPLEXER AND METHOD FOR STATIC RANDOM-ACCESS MEMORY AND COMPUTER MEMORY SUBSYSTEM EMPLOYING THE SAME 有权
标题翻译：用于静态随机存取存储器的列选择多路复用器和方法以及使用其的计算机存储器子系统
公开(公告)号：US20140085965A1
公开(公告)日：2014-03-27
申请号：US13626090
申请日：2012-09-25
申请人： NVIDIA CORPORATION
发明人： Andreas Gotterba , Joel DeWitt , Marek Smoszna
IPC分类号： G11C11/413 , G11C7/10
CPC分类号： G11C7/12 , G11C11/419
摘要： A column select multiplexer, a method of reading data from a random-access memory and a memory subsystem incorporating the multiplexer or the method. In one embodiment, the column select multiplexer includes: (1) a first field-effect transistor having a gate coupled via an inverter to a bitline of a static random-access memory array, (2) a second field-effect transistor coupled in series with the first field-effect transistor and having a gate coupled to a column select bus of the static random-access memory array and (3) a latch having an input coupled to the first and second field-effect transistors.
摘要翻译：列选择多路复用器，从随机存取存储器读取数据的方法和结合多路复用器或方法的存储器子系统。在一个实施例中，列选择多路复用器包括：（1）具有经由反相器耦合到静态随机存取存储器阵列的位线的栅极的第一场效应晶体管，（2）串联耦合的第二场效应晶体管与第一场效应晶体管并且具有耦合到静态随机存取存储器阵列的列选择总线的栅极和（3）具有耦合到第一和第二场效应晶体管的输入的锁存器。

73. 发明授权

US08370557B2 Pseudo dual-port SRAM and a shared memory switch using multiple memory banks and a sideband memory 有权
标题翻译：伪双端口SRAM和使用多个存储体和边带存储器的共享存储器开关
公开(公告)号：US08370557B2
公开(公告)日：2013-02-05
申请号：US12340022
申请日：2008-12-19
申请人： Jonathan Dama , Andrew Lines
发明人： Jonathan Dama , Andrew Lines
IPC分类号： G06F13/00 , G06F12/00 , G11C11/413
CPC分类号： G11C8/16 , G11C7/1075 , G11C8/18
摘要： A memory is described which includes a main memory array made up of multiple single-ported memory banks connected by parallel read and write buses, and a sideband memory equivalent to a single dual-ported memory bank. Control logic and tags state facilitates a pattern of access to the main memory and the sideband memory such that the memory performs like a fully provisioned dual-ported memory capable of reading and writing any two arbitrary addresses on the same cycle.
摘要翻译：描述了一种存储器，其包括由通过并行读和写总线连接的多个单端口存储器组成的主存储器阵列，以及等同于单个双端口存储器组的边带存储器。控制逻辑和标签状态有助于访问主存储器和边带存储器的模式，使得存储器像完全配置的双端口存储器那样执行，其能够在相同周期上读取和写入任意两个任意地址。

74. 发明申请

US20120182792A1 BIASING CIRCUIT AND TECHNIQUE FOR SRAM DATA RETENTION 有权
标题翻译：用于SRAM数据保持的偏置电路和技术
公开(公告)号：US20120182792A1
公开(公告)日：2012-07-19
申请号：US13008992
申请日：2011-01-19
申请人： Hong-Chen CHENG , Chih-Chieh CHIU , Hsu-Shun CHEN , Chung-Ji LU , Cheng-Hung LEE , Hung-Jen LIAO
发明人： Hong-Chen CHENG , Chih-Chieh CHIU , Hsu-Shun CHEN , Chung-Ji LU , Cheng-Hung LEE , Hung-Jen LIAO
IPC分类号： G11C11/413 , G11C5/14
CPC分类号： G11C11/413
摘要： A SRAM system includes: a SRAM cell array coupled between high and low supply nodes, a difference therebetween defining a data retention voltage (VDR) for a low power data retention mode; a main power switch coupling one of high and low supply nodes to a main power supply and disconnecting the one high and low supply nodes from the main power supply during the low power data retention mode; a monitor cell including a SRAM cell preloaded with a data bit and configured for data destruction responsive to a reduction in VDR before data destruction occurs in the SRAM cell array; and a clamping power switch responsive to data destruction in the monitor cell to couple the one of the high and low supply nodes to the main power supply.
摘要翻译： SRAM系统包括：耦合在高电源节点和低电源节点之间的SRAM单元阵列，其间限定用于低功率数据保持模式的数据保持电压（VDR）; 主电源开关将高电源和低电源节点之一耦合到主电源，并且在低功率数据保持模式期间将一个高电源和低电源节点与主电源断开; 监控单元，其包括预先装载有数据位的SRAM单元，并且被配置为在SRAM单元阵列中发生数据破坏之前响应于VDR的减小而进行的数据破坏; 以及钳位电源开关，其响应于监视器单元中的数据破坏，将高电源节点和低电源节点中的一个耦合到主电源。

75. 发明授权

US07920438B2 Semiconductor memory device having the operating voltage of the memory cell controlled 有权
标题翻译：具有控制存储单元的工作电压的半导体存储器件
公开(公告)号：US07920438B2
公开(公告)日：2011-04-05
申请号：US12003970
申请日：2008-01-04
申请人： Masanao Yamaoka , Kenichi Osada
发明人： Masanao Yamaoka , Kenichi Osada
IPC分类号： G11C11/413 , G11C11/4193 , G11C5/14 , G11C7/24
CPC分类号： G11C29/02 , G11C5/146 , G11C5/147 , G11C11/41 , G11C11/412 , G11C11/413 , G11C11/417 , G11C11/419 , G11C29/021 , G11C29/028 , G11C2029/0409
摘要： An SRAM circuit operates at a reduced operation margin, especially at a low operating voltage by increasing or optimizing the operation margin of the SRAM circuit. The threshold voltage of the produced transistor in the SRAM circuit is detected to compare the operating voltage of a memory cell with the operating voltage of a peripheral circuit in order to adjust it to the optimum value, and the substrate bias voltage is further controlled.
摘要翻译： SRAM电路通过增加或优化SRAM电路的工作裕度，以较低的工作电压工作，特别是在低工作电压下工作。检测SRAM电路中产生的晶体管的阈值电压，以将存储单元的工作电压与外围电路的工作电压进行比较，以将其调整到最佳值，并进一步控制衬底偏置电压。

76. 发明申请

US20110032750A1 SEMICONDUCTOR MEMORY DEVICE COMPRISING A PLURALITY OF STATIC MEMORY CELLS 有权
标题翻译：包含多个静态记忆细胞的半导体存储器件
公开(公告)号：US20110032750A1
公开(公告)日：2011-02-10
申请号：US12909465
申请日：2010-10-21
申请人： Makoto Yabuuchi , Koji Nii
发明人： Makoto Yabuuchi , Koji Nii
IPC分类号： G11C7/00 , G11C11/413
CPC分类号： G11C8/08 , G11C5/147 , G11C11/412 , G11C11/413
摘要： A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.
摘要翻译：降低电源电压的驱动器电源电路被布置在字线驱动器的电源节点处。驱动器电源电路包括N +掺杂多晶硅的非硅化物电阻元件和降低驱动器电源节点的电压电平的下拉电路。下拉电路包括具有与下拉驱动器电源节点的电压电平的存储单元晶体管相同的阈值电压特性的下拉晶体管，以及至少调节下拉电路的栅极电压的栅极控制电路晶体管。栅极控制电路以与存储单元晶体管的阈值电压的变化相关联的方式校正下拉晶体管的栅极电位。

77. 发明授权

US07558145B2 Word line control for improving read and write margins 有权
标题翻译：字线控制，用于提高读写余量
公开(公告)号：US07558145B2
公开(公告)日：2009-07-07
申请号：US11468877
申请日：2006-08-31
申请人： Setti Shanmukheswara Rao , Biswa Bhusan Sahoo
发明人： Setti Shanmukheswara Rao , Biswa Bhusan Sahoo
IPC分类号： G11C8/16 , G11C11/41 , G11C11/413
CPC分类号： G11C5/08 , G11C11/413
摘要： Apparatus to apply a voltage to the word line during a first time interval portion of the access cycle and to apply a further voltage to the word line during a further time interval portion of the access cycle and to apply the further voltage to a further word line during the first time interval portion of the access cycle and to apply the voltage to the further word line during the further time interval of the access cycle.
摘要翻译：用于在访问周期的第一时间间隔部分期间向字线施加电压并且在访问周期的另外的时间间隔部分期间向字线施加另外的电压并将另外的电压施加到另外的字线在访问周期的第一时间间隔部分期间，并且在访问周期的另外的时间间隔期间将电压施加到另外的字线。

78. 发明授权

US07382674B2 Static random access memory (SRAM) with clamped source potential in standby mode 失效
标题翻译：静态随机存取存储器（SRAM），钳位源电位处于待机模式
公开(公告)号：US07382674B2
公开(公告)日：2008-06-03
申请号：US11401933
申请日：2006-04-12
申请人： Osamu Hirabayashi
发明人： Osamu Hirabayashi
IPC分类号： G11C5/14 , G11C11/413 , G11C29/00
CPC分类号： G11C7/1051 , G11C11/41 , G11C29/50 , G11C2207/108 , G11C2207/2227
摘要： A semiconductor memory device includes a memory cell array including a plurality of memory cells, a source terminal which supplies a source potential to the memory cells, a first switching element which electrically connects the source terminal and a first power supply potential in an operation mode of the memory cells, and electrically disconnects the source terminal and the first power supply potential in a standby mode of the memory cells, a clamp MIS transistor which is series-connected between the source terminal and the first power supply potential, and clamps the source potential in the standby mode, a bias generation circuit which supplies a first bias potential to a gate terminal of the clamp MIS transistor, and a switching circuit which switches a potential of a back gate terminal of the clamp MIS transistor between a test mode and a non-test mode.
摘要翻译：一种半导体存储器件包括：存储单元阵列，包括多个存储单元，向存储单元提供源极电位的源极端子;第一开关元件，用于将源极端子和第一电源电位以第存储器单元，并且在存储单元的待机模式下电源断开源极端子和第一电源电位;串联连接在源极端子和第一电源电位之间的钳位MIS晶体管，并钳位源极电位在待机模式中，向钳位MIS晶体管的栅极端提供第一偏置电位的偏置产生电路，以及将钳位MIS晶体管的背栅极的电位切换到测试模式和非测试模式之间的开关电路， -测试模式。

79. 发明授权

US07292492B2 SRAM, semiconductor memory device, method for maintaining data in SRAM, and electronic device 有权
标题翻译： SRAM，半导体存储器件，用于在SRAM中保持数据的方法，以及电子器件
公开(公告)号：US07292492B2
公开(公告)日：2007-11-06
申请号：US11523586
申请日：2006-09-20
申请人： Noriyuki Matsui
发明人： Noriyuki Matsui
IPC分类号： G11C11/41 , G11C11/413 , G11C11/406 , G11C29/52 , G11C7/02 , G11C7/24 , G11C7/04
CPC分类号： G11C11/406 , G11C11/4125 , G11C2211/4068
摘要： An SRAM (Static Ransom Access Memory) has a refreshing unit for performing a refreshing operation to maintain a state of an electric charge in a memory cell in order to prevent stored data from being destructed by a latch-up phenomenon to maintain the stored data certainly even when a soft error occurs due to a neutron.
摘要翻译： SRAM（静态随机存取存储器）具有刷新单元，用于执行刷新操作以保持存储单元中的电荷状态，以防止存储的数据被闩锁现象破坏，以保持存储的数据肯定即使由于中子而发生软错误。

80. 发明申请

US20050286323A1 Semiconductor memory device and circuit layout of dummy cell 有权
标题翻译：半导体存储器件和虚拟电池的电路布局
公开(公告)号：US20050286323A1
公开(公告)日：2005-12-29
申请号：US11156706
申请日：2005-06-21
申请人： Hirohisa Ohtsuki , Kazuo Itoh , Katsuji Satomi , Hironori Akamatsu
发明人： Hirohisa Ohtsuki , Kazuo Itoh , Katsuji Satomi , Hironori Akamatsu
IPC分类号： G11C7/08 , G11C7/12 , G11C11/413 , G11C29/00
CPC分类号： G11C7/08 , G11C7/12 , G11C7/227 , G11C11/413
摘要： A dummy cell includes two series-connected OFF-state transistors, one end of the series circuit which is formed by these two transistors is connected with a constant voltage source, and the other end of the series circuit is connected with a replica bit line. This suppresses a leak current flowing from the replica bit line to the dummy cell and therefore gives optimal start-up timing to a sense amplifier circuit.
摘要翻译：虚拟单元包括两个串联的截止状态晶体管，由这两个晶体管形成的串联电路的一端与恒定电压源连接，串联电路的另一端与复制位线连接。这抑制了从复制位线流向虚拟单元的泄漏电流，从而给读出放大器电路提供了最佳的启动时序。

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