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1. 发明申请

US20180337151A1 SEMICONDUCTOR MEMORY CHIP, SEMICONDUCTOR MEMORY PACKAGE, AND ELECTRONIC SYSTEM USING THE SAME 审中-公开
公开(公告)号：US20180337151A1
公开(公告)日：2018-11-22
申请号：US15847086
申请日：2017-12-19
申请人： SAMSUNG ELECTRONICS CO., LTD
发明人： KYOUNG SOO KIM , Won Young Kim , Sun Won Kang
IPC分类号： H01L23/00 , H01L25/10 , G11C5/04 , G11C5/06 , G11C7/10 , G11C8/18
CPC分类号： H01L24/06 , G11C5/04 , G11C5/06 , G11C7/1012 , G11C7/106 , G11C7/1063 , G11C7/1087 , G11C7/109 , G11C8/18 , G11C2207/105 , G11C2207/107 , G11C2207/108 , H01L23/3128 , H01L23/49816 , H01L24/16 , H01L24/32 , H01L24/73 , H01L25/105 , H01L2224/0401 , H01L2224/05014 , H01L2224/06151 , H01L2224/16113 , H01L2224/16227 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2924/1434
摘要： A semiconductor memory chip includes an upper data pad region, a lower data pad region, and an additional pad region. Upper data pads, upper data strobe signal pair pads, and an upper data mask signal pad are arranged in the upper data pad region. Lower data pads, lower data strobe signal pair pads, and a lower data mask signal pad are arranged in the lower data pad region adjacent to and below the upper data pad region. An inverted termination data strobe signal pad used for a second semiconductor memory package and internally connected to the upper data mask signal pad, which is used for a first semiconductor memory package, is arranged in the additional pad region adjacent to and above the upper data pad region.

2. 发明申请

US20180294038A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20180294038A1
公开(公告)日：2018-10-11
申请号：US16009769
申请日：2018-06-15
申请人： TOSHIBA MEMORY CORPORATION
发明人： Shinya OKUNO , Shigeki NAGASAKA , Toshiyuki KOUCHI
IPC分类号： G11C16/32 , G11C7/10 , G06F5/06 , G06F13/16 , G11C7/02 , G11C16/26 , G11C16/16 , G11C16/12 , G11C16/10 , G11C16/04
CPC分类号： G11C16/32 , G06F5/06 , G06F13/1673 , G06F2205/067 , G11C7/02 , G11C7/1012 , G11C7/1039 , G11C7/106 , G11C7/1066 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/26 , G11C2207/108 , G11C2207/2281 , Y02D10/14
摘要： A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

3. 发明申请

US20180102344A1 NON-VOLATILE MEMORY SYSTEM WITH WIDE I/O MEMORY DIE 审中-公开
公开(公告)号：US20180102344A1
公开(公告)日：2018-04-12
申请号：US15287344
申请日：2016-10-06
申请人： SANDISK TECHNOLOGIES LLC
发明人： Venkatesh P. Ramachandra , Michael Mostovoy , Hem Takiar , Gokul Kumar , Vinayak Ghatawade
IPC分类号： H01L25/065 , H01L25/18 , G11C7/10 , G11C7/22 , G11C29/00 , G11C7/06
CPC分类号： H01L25/0657 , G06F13/4018 , G06F13/4234 , G11C5/04 , G11C5/063 , G11C5/066 , G11C7/065 , G11C7/10 , G11C7/22 , G11C29/781 , G11C2207/105 , G11C2207/108 , H01L25/18 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2225/06582 , H01L2924/1431 , H01L2924/1434
摘要： A non-volatile storage system includes a plurality of memory dies and an interface circuit. Each memory die includes a wide I/O interface electrically coupled to another wide I/O interface of another memory die of the plurality of memory dies. The interface circuit is physically separate from the memory dies. The interface circuit includes a first interface and a second interface. The first interface comprises a wide I/O interface electrically coupled to a wide I/O interface of at least one of the memory dies of the plurality of memory dies. The second interface is a narrow I/O interface configured to communicate with an external circuit.

4. 发明授权

US09870810B2 Method and system for power signature suppression in memory devices 有权
公开(公告)号：US09870810B2
公开(公告)日：2018-01-16
申请号：US15247050
申请日：2016-08-25
申请人： Sidense Corp.
发明人： Wlodek Kurjanowicz , Betina Hold
IPC分类号： G11C7/10 , G11C7/22 , G11C7/06
CPC分类号： G11C7/222 , G11C7/065 , G11C7/1006 , G11C7/1048 , G11C7/1057 , G11C7/106 , G11C7/1066 , G11C7/1075 , G11C7/24 , G11C29/76 , G11C2207/108
摘要： A method and system for suppressing power signature in a memory device during read operations. A memory array stores data in an even number of cells per bit, such as 2 cells per bit, where complementary data states are stored in each pair of cells. Differential read out of the memory array via the bitlines suppresses power signature because the same power consumption occurs regardless of the data being accessed from the memory array. Data output buffers that provide complementary data to a downstream circuit system are reset to the same logic state prior to every read operation such that only one output buffer (in the complementary output buffer pair) is ever driven to the opposite logic state in each read cycle. Hence the power consumption remains the same regardless of the data states being read out from the memory array and provided by the output buffers.

5. 发明申请

US20170337957A1 METHOD AND SYSTEM FOR POWER SIGNATURE SUPPRESSION IN MEMORY DEVICES 有权
公开(公告)号：US20170337957A1
公开(公告)日：2017-11-23
申请号：US15247050
申请日：2016-08-25
申请人： Sidense Corp.
发明人： Wlodek KURJANOWICZ , Betina HOLD
IPC分类号： G11C7/22 , G11C7/06 , G11C7/10
CPC分类号： G11C7/222 , G11C7/065 , G11C7/1006 , G11C7/1048 , G11C7/1057 , G11C7/106 , G11C7/1066 , G11C7/1075 , G11C7/24 , G11C29/76 , G11C2207/108
摘要： A method and system for suppressing power signature in a memory device during read operations. A memory array stores data in an even number of cells per bit, such as 2 cells per bit, where complementary data states are stored in each pair of cells. Differential read out of the memory array via the bitlines suppresses power signature because the same power consumption occurs regardless of the data being accessed from the memory array. Data output buffers that provide complementary data to a downstream circuit system are reset to the same logic state prior to every read operation such that only one output buffer (in the complementary output buffer pair) is ever driven to the opposite logic state in each read cycle. Hence the power consumption remains the same regardless of the data states being read out from the memory array and provided by the output buffers.

6. 发明授权

US09690510B2 Two-stage read/write 3D architecture for memory devices 有权
公开(公告)号：US09690510B2
公开(公告)日：2017-06-27
申请号：US14259607
申请日：2014-04-23
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Kuang Ting Chen , Ching-Wei Wu
IPC分类号： G06F13/00 , G06F3/06 , G11C5/02 , G11C5/06 , G11C7/10 , G11C7/18 , H01L27/06 , H01L27/11
CPC分类号： G06F3/0625 , G06F3/0665 , G06F3/0689 , G11C5/025 , G11C5/063 , G11C5/066 , G11C7/1075 , G11C7/18 , G11C2207/108 , G11C2207/2209 , G11C2211/4016 , H01L27/0688 , H01L27/1104
摘要： Some embodiments of the present disclosure relate to a memory device wherein a single memory cell array is partitioned between two or more tiers which are vertically integrated on a single substrate. The memory device also includes support circuitry including a control circuit configured to read and write data to the memory cells on each tier, and a shared input/output (I/O) architecture which is connected the memory cells within each tier and configured to receive input data word prior to a write operation, and further configured to provide output data word after a read operation. Other devices and methods are also disclosed.

7. 发明授权

US09349418B2 Semiconductor device and method for driving the same 有权
标题翻译：半导体装置及其驱动方法
公开(公告)号：US09349418B2
公开(公告)日：2016-05-24
申请号：US14582319
申请日：2014-12-24
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yoshitaka Yamamoto , Kiyoshi Kato
IPC分类号： G11C11/00 , G11C11/14 , G11C5/14 , H01L27/108 , H01L27/06 , H01L29/786 , G11C8/16 , G11C11/405 , G11C11/408 , G11C11/56 , H01L27/115
CPC分类号： G11C5/14 , G11C7/12 , G11C8/08 , G11C8/10 , G11C8/16 , G11C11/24 , G11C11/405 , G11C11/4087 , G11C11/409 , G11C11/565 , G11C2207/108 , H01L23/528 , H01L27/0688 , H01L27/1052 , H01L27/10814 , H01L27/1082 , H01L27/10826 , H01L27/10855 , H01L27/10858 , H01L27/10873 , H01L27/10879 , H01L27/10897 , H01L27/1156 , H01L27/1207 , H01L27/1225 , H01L27/1255 , H01L27/1259 , H01L29/24 , H01L29/786 , H01L29/7869
摘要： A novel semiconductor device where multilevel data can be written and read. The semiconductor device includes first to fifth transistors, a capacitor, a bit line, and a power supply line. Write operation is performed in such a manner that first data is supplied to a gate of the fifth transistor through the first transistor; the first transistor is turned off; second data is supplied to a second electrode of the capacitor through the second transistor to convert the first data into third data; and the second electrode of the capacitor are made electrically floating. The second electrode of the capacitor is initialized to GND through the third transistor. Read operation is performed by charging or discharging the bit line through the fourth transistor and the fifth transistor. The first to third transistors are preferably oxide semiconductor transistors.
摘要翻译：可以写入和读取多级数据的新型半导体器件。半导体器件包括第一至第五晶体管，电容器，位线和电源线。以通过第一晶体管将第一数据提供给第五晶体管的栅极的方式执行写入操作; 第一个晶体管关闭; 第二数据通过第二晶体管提供给电容器的第二电极，以将第一数据转换为第三数据; 并且使电容器的第二电极电浮动。电容器的第二个电极通过第三个晶体管初始化为GND。通过对第四晶体管和第五晶体管的位线进行充电或放电来进行读操作。第一至第三晶体管优选为氧化物半导体晶体管。

8. 发明申请

US20150309750A1 TWO-STAGE READ/WRITE 3D ARCHITECTURE FOR MEMORY DEVICES 有权
标题翻译：用于存储器件的两级阅读/写入3D架构
公开(公告)号：US20150309750A1
公开(公告)日：2015-10-29
申请号：US14259607
申请日：2014-04-23
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Kuang Ting Chen , Ching-Wei Wu
IPC分类号： G06F3/06 , G11C11/406
CPC分类号： G06F3/0625 , G06F3/0665 , G06F3/0689 , G11C5/025 , G11C5/063 , G11C5/066 , G11C7/1075 , G11C7/18 , G11C2207/108 , G11C2207/2209 , G11C2211/4016 , H01L27/0688 , H01L27/1104
摘要： Some embodiments of the present disclosure relate to a memory device wherein a single memory cell array is partitioned between two or more tiers which are vertically integrated on a single substrate. The memory device also includes support circuitry including a control circuit configured to read and write data to the memory cells on each tier, and a shared input/output (I/O) architecture which is connected the memory cells within each tier and configured to receive input data word prior to a write operation, and further configured to provide output data word after a read operation. Other devices and methods are also disclosed.
摘要翻译：本公开的一些实施例涉及一种存储器件，其中单个存储器单元阵列在垂直集成在单个衬底上的两个或更多个层之间分隔。该存储设备还包括支持电路，其包括配置成将数据读取和写入每层上的存储器单元的控制电路，以及共享输入/输出（I / O）架构，其连接每层内的存储器单元并被配置为接收在写入操作之前的输入数据字，并且还被配置为在读取操作之后提供输出数据字。还公开了其它装置和方法。

9. 发明申请

US20150187775A1 SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME 有权
标题翻译：半导体器件及其驱动方法
公开(公告)号：US20150187775A1
公开(公告)日：2015-07-02
申请号：US14582319
申请日：2014-12-24
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yoshitaka Yamamoto , Kiyoshi Kato
IPC分类号： H01L27/108 , G11C7/12 , G11C5/14 , G11C11/419
CPC分类号： G11C5/14 , G11C7/12 , G11C8/08 , G11C8/10 , G11C8/16 , G11C11/24 , G11C11/405 , G11C11/4087 , G11C11/409 , G11C11/565 , G11C2207/108 , H01L23/528 , H01L27/0688 , H01L27/1052 , H01L27/10814 , H01L27/1082 , H01L27/10826 , H01L27/10855 , H01L27/10858 , H01L27/10873 , H01L27/10879 , H01L27/10897 , H01L27/1156 , H01L27/1207 , H01L27/1225 , H01L27/1255 , H01L27/1259 , H01L29/24 , H01L29/786 , H01L29/7869
摘要： A novel semiconductor device where multilevel data can be written and read. The semiconductor device includes first to fifth transistors, a capacitor, a bit line, and a power supply line. Write operation is performed in such a manner that first data is supplied to a gate of the fifth transistor through the first transistor; the first transistor is turned off; second data is supplied to a second electrode of the capacitor through the second transistor to convert the first data into third data; and the second electrode of the capacitor are made electrically floating. The second electrode of the capacitor is initialized to GND through the third transistor. Read operation is performed by charging or discharging the bit line through the fourth transistor and the fifth transistor. The first to third transistors are preferably oxide semiconductor transistors.
摘要翻译：可以写入和读取多级数据的新型半导体器件。半导体器件包括第一至第五晶体管，电容器，位线和电源线。以通过第一晶体管将第一数据提供给第五晶体管的栅极的方式执行写入操作; 第一个晶体管关闭; 第二数据通过第二晶体管提供给电容器的第二电极，以将第一数据转换为第三数据; 并且使电容器的第二电极电浮动。电容器的第二个电极通过第三个晶体管初始化为GND。通过对第四晶体管和第五晶体管的位线进行充电或放电来进行读操作。第一至第三晶体管优选为氧化物半导体晶体管。

10. 发明申请

US20150070990A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20150070990A1
公开(公告)日：2015-03-12
申请号：US14206102
申请日：2014-03-12
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Ryo FUKUDA
IPC分类号： G11C16/04 , H01L27/115
CPC分类号： G11C16/0483 , G11C7/1006 , G11C7/1012 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C2207/105 , G11C2207/108 , H01L27/11551 , H01L27/11578
摘要： According to an embodiment, a semiconductor device includes an IO terminal unit, an first IO line, and a second IO line. The IO terminal unit includes first and second IO terminals. The first IO line is electrically connected to one of both the first IO terminal and the second IO terminal. The second IO line is electrically connected to the other of both the first IO terminal and the second IO terminal. When the semiconductor device receives a first signal, the first IO terminal is electrically connected to the first IO line and the second IO terminal is electrically connected to the second IO line. When the semiconductor device receives a second signal, the first IO terminal is electrically connected to the second IO line and the second IO terminal is electrically connected to the first IO line. The second signal is different from the first signal.
摘要翻译：根据实施例，半导体器件包括IO端子单元，第一IO线和第二IO线。 IO终端单元包括第一和第二IO端子。第一IO线电连接到第一IO端子和第二IO端子中的一个。第二IO线与第一IO端子和第二IO端子中的另一个电连接。当半导体器件接收到第一信号时，第一IO端子电连接到第一IO线，而第二IO端子电连接到第二IO线。当半导体器件接收第二信号时，第一IO端子电连接到第二IO线，而第二IO端子电连接到第一IO线。第二信号与第一信号不同。

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