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81. 发明授权

US09543254B2 Chamfered corner crackstop for an integrated circuit chip 有权
标题翻译：用于集成电路芯片的倒角角裂缝
公开(公告)号：US09543254B2
公开(公告)日：2017-01-10
申请号：US14711109
申请日：2015-05-13
申请人： GLOBALFOUNDRIES INC.
发明人： Mark C. Lamorey , David B. Stone
IPC分类号： H01L23/00 , H01L23/58 , H01L21/768
CPC分类号： H01L23/562 , H01L21/76802 , H01L21/76877 , H01L23/585 , H01L2924/0002 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： A corner crackstop is formed in each of the four corners of an integrated circuit (IC) chip, in which the corner crackstop differs structurally from a portion of the crackstop disposed along the sides of the IC chip. Each corner crackstop includes a plurality of layers, formed on a top surface of a silicon layer of the IC chip, within a perimeter boundary region that comprises a triangular area, in which a right angle is disposed on a bisector of the corner, equilateral sides of the triangle are parallel to sides of the IC chip, and the right angle is proximate to the corner relative to a hypotenuse of the triangle. The plurality of layers of the corner crackstop include crackstop elements, each comprising a metal cap centered over a via bar, in which the plurality of layers of the corner crackstop is chamfered to deflect crack ingress forces by each corner crackstop.
摘要翻译：在集成电路（IC）芯片的四个角中的每一个角部形成有拐角裂缝，其中拐角裂缝在结构上与沿着IC芯片的侧面设置的裂纹阻挡部分不同。每个角裂缝包括形成在IC芯片的硅层的顶表面上的多个层，所述多个层在包括三角形区域的周边边界区域内，其中直角设置在角部的二等分线上，等边侧的三角形平行于IC芯片的两侧，并且直角相对于三角形的斜边接近角落。多个角落裂缝的层包括裂缝阻挡元件，每个裂缝元件都包括以通孔杆为中心的金属盖，其中角部裂纹器的多个层被倒角以通过每个拐角裂缝挡块来偏转裂纹侵入力。

82. 发明授权

US09542524B2 Static timing analysis (STA) using derived boundary timing constraints for out-of-context (OOC) hierarchical entity analysis and abstraction 有权
标题翻译：静态时序分析（STA）使用导出的边界时序约束进行上下文（OOC）分层实体分析和抽象
公开(公告)号：US09542524B2
公开(公告)日：2017-01-10
申请号：US14606053
申请日：2015-01-27
申请人： International Business Machines Corporation
发明人： James C. Gregerson , David J. Hathaway , Kerim Kalafala , Tsz-Mei Ko , Alex Rubin
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F17/504 , G06F2217/84
摘要： Disclosed are a system and a method for performing a timing analysis of an integrated circuit (IC). An internal timing constraint of a logic device in a first signal pathway of a hierarchical entity in an IC design is determined based on a reference value and, if necessary, on library information. A first boundary timing constraint associated with the first signal pathway is derived based on the internal timing constraint and a second boundary timing constraint associated with the first signal pathway is derived based on the first boundary timing constraint and a target slack value for the internal timing constraint. A static timing analysis is performed using the second boundary timing constraint. Based on the analysis, a timing abstraction for the hierarchical entity is generated. A timing model for the IC design is generated using the timing abstraction and other timing abstractions for other hierarchical entities in the design.
摘要翻译：公开了一种用于执行集成电路（IC）的定时分析的系统和方法。基于参考值，如果需要，根据图书馆信息来确定IC设计中分层实体的第一信号路径中的逻辑设备的内部时序约束。基于内部定时约束导出与第一信号路径相关联的第一边界时序约束，并且基于第一边界定时约束和内部定时约束的目标松弛值导出与第一信号路径相关联的第二边界定时约束。使用第二边界定时约束执行静态时序分析。基于分析，生成层次实体的时序抽象。使用设计中其他分层实体的时序抽象和其他定时抽象来生成IC设计的时序模型。

83. 发明授权

US09520391B1 Field effect transistor having delay element with back gate 有权
标题翻译：具有后栅的延迟元件的场效应晶体管
公开(公告)号：US09520391B1
公开(公告)日：2016-12-13
申请号：US14996371
申请日：2016-01-15
申请人： GLOBALFOUNDRIES INC.
发明人： Brent A. Anderson , Terence B. Hook , Myung-Hee Na , Edward J. Nowak
IPC分类号： H01L27/06 , H01L29/786 , H01L21/8238
CPC分类号： H01L27/0629 , H01L21/823857 , H01L27/092 , H01L27/0924 , H01L29/78648
摘要： Methods form complementary metal oxide semiconductor (CMOS) devices that include a first transistor and a complementary second transistor, and an output connected to the first transistor and the second transistor. The first transistor includes a first channel region, a first back gate, a first delay element between the output and the first back gate, and a first back gate insulator separating the first back gate from the first channel region. The second transistor includes a second channel region, a second back gate, a second delay element between the output and the second back gate, and a second back gate insulator separating the second back gate from the second channel region. The first delay element, the first back gate insulator, and the first channel region form a first resistor-capacitor (RC) circuit, and the second delay element, the second back gate insulator, and the second channel region form a second RC circuit.
摘要翻译：方法形成包括第一晶体管和互补第二晶体管的互补金属氧化物半导体（CMOS）器件，以及连接到第一晶体管和第二晶体管的输出。第一晶体管包括第一沟道区，第一后栅，在输出和第一后栅之间的第一延迟元件，以及将第一后栅与第一沟道区分开的第一后栅绝缘体。第二晶体管包括第二沟道区，第二后栅，输出与第二后栅之间的第二延迟元件，以及将第二栅极与第二沟道区分开的第二栅极绝缘体。第一延迟元件，第一背栅绝缘体和第一沟道区形成第一电阻 - 电容（RC）电路，第二延迟元件，第二后栅极绝缘体和第二沟道区形成第二RC电路。

84. 发明授权

US09472558B1 Semiconductor structures with stacked non-planar field effect transistors and methods of forming the structures 有权
标题翻译：具有堆叠非平面场效应晶体管的半导体结构和形成结构的方法
公开(公告)号：US09472558B1
公开(公告)日：2016-10-18
申请号：US14940499
申请日：2015-11-13
申请人： GLOBALFOUNDRIES INC.
发明人： Kangguo Cheng , Ali Khakifirooz , Carl Radens , Robert C. Wong
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/66 , H01L27/11 , H01L23/528 , H01L29/08 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/78 , H01L29/06
CPC分类号： H01L27/1116 , H01L21/823814 , H01L21/823821 , H01L21/823878 , H01L27/0688 , H01L27/0924 , H01L27/1104 , H01L29/0653 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/7848
摘要： Disclosed are semiconductor structures and methods of forming them. The structures include field effect transistors (FETs) with different type conductivities in different levels, respectively, of the same fin, wherein the numbers of FETs in the different levels are different. Specifically, in a fin, a first semiconductor layer has source/drain and channel regions for a first and a second transistor and a second semiconductor layer has source/drain and channel regions for a third transistor with a different type conductivity than first and second transistors. A gate is on the top surface and sides of the first semiconductor layer at the channel region of the first transistor. Another gate has a lower portion on the sides of the first semiconductor layer at the channel region of the second transistor and an upper portion on the top surface and sides of the second semiconductor layer at the channel region of the third transistor.
摘要翻译：公开了半导体结构及其形成方法。该结构分别包括具有不同级别的不同类型电导率的场效应晶体管（FET），其中不同级别的FET的数量是不同的。具体地，在散热片中，第一半导体层具有用于第一和第二晶体管的源极/漏极和沟道区，并且第二半导体层具有用于具有与第一和第二晶体管不同的导电类型的第三晶体管的源极/漏极和沟道区。栅极位于第一晶体管的沟道区的第一半导体层的顶表面和侧面上。另一个栅极在第二晶体管的沟道区域处具有在第一半导体层的侧面上的下部，在第三晶体管的沟道区域处的第二半导体层的顶部表面和侧面上的上部。

85. 发明授权

US09463945B2 Multi-stage collation system and method for high speed compiling sequentially ordered signage 有权
标题翻译：多级整理系统和方法，用于高速编译顺序指示牌
公开(公告)号：US09463945B2
公开(公告)日：2016-10-11
申请号：US14582426
申请日：2014-12-24
申请人： Xerox Corporation
发明人： Douglas K. Herrmann
IPC分类号： B65H37/00 , B65H39/00 , B65H35/00
CPC分类号： B65H37/00 , B65H31/24 , B65H31/3009 , B65H31/3081 , B65H35/008 , B65H39/00 , B65H39/075 , B65H2301/4212 , B65H2301/42172 , B65H2301/515 , B65H2701/124 , B65H2701/1914
摘要： According to exemplary systems and methods, signs are created using a document-processing device. The signs are removed from a processing path of the document-processing device using a transport device to move the signs to a compiler. Ordered stacks of the signs are compiled in the compiler. The signs are temporarily held in the compiler during a first operation of a collating system. Following actuation and reset of the collating system, the signs are moved to the collating system. The collating system includes a ramped collator that moves interim stacks of signs received from the compiler from the ramps of the ramped collator toward a final collated stack according to job-specific instructions.
摘要翻译：根据示例性系统和方法，使用文档处理设备创建符号。使用传送装置从文件处理装置的处理路径移除符号以将符号移动到编译器。符号的有序堆栈在编译器中编译。在整理系统的第一次操作期间，迹象被暂时保存在编译器中。在整理系统的致动和复位之后，标志被移动到整理系统。对照系统包括斜坡整理器，根据作业特定的指令，将从编译器接收的临时堆叠的标志从斜坡整理器的斜坡移向最终的堆叠堆叠。

86. 发明授权

US09448280B2 Circuit test system and method using a wideband multi-tone test signal 有权
标题翻译：电路测试系统和方法采用宽带多音测试信号
公开(公告)号：US09448280B2
公开(公告)日：2016-09-20
申请号：US13407811
申请日：2012-02-29
申请人： Timothy M. Platt , Mustapha Slamani , Tian Xia
发明人： Timothy M. Platt , Mustapha Slamani , Tian Xia
IPC分类号： G06F19/00 , G01R31/3167 , G01R31/28
CPC分类号： G01R31/3167 , G01R31/2837
摘要： A testing system and method incorporate a test signal generator for generating a test signal with multiple tones uniformly distributed across a wideband having a specific bandwidth. This test signal is generated based on user-specified test signal parameter(s) (e.g., using an orthogonal frequency-division multiplexing (OFDM) spread spectrum technique) and processed (e.g., converted from digital to analog or shifted to a different wideband having the same bandwidth), as necessary, so that it is suitable for application to a specific device under test and so that the tones account for the full range of frequencies with the wideband operation of that device under test. After it is applied to the device under test, the resulting output signal is captured, processed (e.g., converted back to digital or shifted back to the initial wideband), as necessary, and analyzed in order to determine the frequency responses associated with each of the tones.
摘要翻译：测试系统和方法包括测试信号发生器，用于产生具有均匀分布在具有特定带宽的宽带上的多个音调的测试信号。该测试信号基于用户指定的测试信号参数（例如，使用正交频分复用（OFDM）扩频技术）生成并被处理（例如，从数字到模拟或被转换到具有相同的带宽），因此它适合于应用于被测试的特定设备，并且使得该音调考虑到被测设备的宽带操作的全频率范围。在将其应用于被测设备之后，根据需要对所得到的输出信号进行捕获，处理（例如，转换回数字或移回到初始宽带），并进行分析，以便确定与每个音调。

87. 发明授权

US09437539B2 Dielectric region in a bulk silicon substrate providing a high-Q passive resonator 有权
标题翻译：提供高Q无源谐振器的体硅衬底中的介电区域
公开(公告)号：US09437539B2
公开(公告)日：2016-09-06
申请号：US14830816
申请日：2015-08-20
申请人： International Business Machines Corporation
发明人： James S. Dunn , Zhong-Xiang He , Qizhi Liu
IPC分类号： H01L23/522 , H01L23/66 , H01L49/02 , H01L29/06 , H01L21/762 , H01L23/31 , H01L23/528 , H01L23/532 , H01L29/16
CPC分类号： H01L23/5223 , H01L21/3083 , H01L21/762 , H01L21/76224 , H01L23/3171 , H01L23/5227 , H01L23/528 , H01L23/53295 , H01L23/66 , H01L28/10 , H01L28/40 , H01L29/0649 , H01L29/16 , H01L2223/6672 , H01L2924/0002 , H01L2924/00
摘要： Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.
摘要翻译：在混合信号集成电路（IC）的体硅（Si）衬底中制造电介质区域的结构和方法提供了高Q无源谐振器。通过湿法蚀刻在<100>方向内的本体Si衬底内的深沟槽扩大以形成连续的空腔，其由Si氧化物填充以形成电介质区域。电介质区域增强了在混合信号IC的金属化层中形成的覆盖无源谐振器的质量（Q）。

88. 发明授权

US09423748B1 Producing multi-pass output for different extension colorants on color press 有权
标题翻译：在彩色印刷机上生产不同延伸着色剂的多通道输出
公开(公告)号：US09423748B1
公开(公告)日：2016-08-23
申请号：US14792774
申请日：2015-07-07
申请人： Xerox Corporation
发明人： David C. Robinson , Katherine Loj
IPC分类号： G03G15/00
CPC分类号： G03G15/5016 , G03G15/0121 , G03G15/0865 , G03G15/0877 , G03G15/36 , G03G15/50 , G03G15/6585 , H04N2201/00
摘要： A processor receives a print job, identifies possible extension marking materials to use to print the print job, and optimizes the order in which the extension marking materials will be used in multiple printing passes. A user interface outputs instructions to insert, into a receptacle, a first interchangeable supply container containing a first extension marking material that is in addition to base marking materials. A printing engine prints first markings (using the first extension marking material) that comprise a first portion of the print job. The user interface outputs instructions to return the partially printed print media to a sheet supply and to insert a second interchangeable supply container containing a second extension marking material. The printing engine prints second markings (using the second extension marking material) that comprise a second portion of the print job, on the partially printed print media, to produce the finally printed print media.
摘要翻译：处理器接收打印作业，识别用于打印打印作业的可能的扩展标记材料，并优化在多个打印通行证中使用扩展标记材料的顺序。用户界面输出指令，以插入到容器中，第一可互换供应容器包含除基础标记材料之外的第一延伸标记材料。打印引擎打印包括打印作业的第一部分的第一标记（使用第一扩展标记材料）。用户界面输出指令以将部分打印的打印介质返回到纸张供应装置，并插入包含第二延伸标记材料的第二可互换供应容器。打印引擎在部分打印的打印介质上打印包括打印作业的第二部分的第二标记（使用第二延伸标记材料）以产生最终打印的打印介质。

89. 发明授权

US09401711B2 Driver output with dynamic switching bias 有权
标题翻译：驱动器输出具有动态开关偏置
公开(公告)号：US09401711B2
公开(公告)日：2016-07-26
申请号：US14541713
申请日：2014-11-14
申请人： International Business Machines Corporation
发明人： Francis Chan , Bo Qu , Si Shi , Songtao Xu
IPC分类号： H03K3/00 , H03K17/687
CPC分类号： H03K17/6872 , H03K17/08122 , H03K17/145
摘要： A circuit of an output stage of a push-pull driver having dynamic biasing may include a stacked configuration of field effect transistors (PFETs) having a first PFET, a second PFET, and a third PFET, whereby the first PFET is connected to a first supply voltage, the third PFET is connected to an output of a switchable voltage bias generator circuit, and the second PFET is electrically connected between the first PFET and the third PFET. A transmission gate may be connected to a second supply voltage, whereby the transmission gate electrically connects the second supply voltage to an electrical connection between the first PFET and the second PFET based on a first operating state for preventing a voltage breakdown condition associated with the stacked configuration of PFETs. The third PFET is bias controlled via the switching of the output of the switchable voltage bias generator circuit.
摘要翻译：具有动态偏置的推挽驱动器的输出级的电路可以包括具有第一PFET，第二PFET和第三PFET的场效应晶体管（PFET）的堆叠配置，由此第一PFET连接到第一电源电压，第三PFET连接到可切换电压偏置发生器电路的输出，并且第二PFET电连接在第一PFET和第三PFET之间。传输门可以连接到第二电源电压，由此传输门基于第一操作状态将第二电源电压电连接到第一PFET和第二PFET之间的电连接，用于防止与堆叠 PFET的配置。通过切换可切换电压偏置发生器电路的输出来对第三PFET进行偏置控制。

90. 发明授权

US09391065B1 Electrostatic discharge and passive structures integrated in a vertical gate fin-type field effect diode 有权
标题翻译：集成在垂直栅极鳍式场效应二极管中的静电放电和无源结构
公开(公告)号：US09391065B1
公开(公告)日：2016-07-12
申请号：US14753628
申请日：2015-06-29
申请人： International Business Machines Corporation
发明人： Robert J. Gauthier, Jr. , Tom C. Lee , You Li , Rahul Mishra , Souvick Mitra , Andreas Scholze
IPC分类号： H01L29/66 , H01L27/12 , H01L23/495 , H01L27/02 , H01L27/06 , H01L29/78
CPC分类号： H01L27/0255 , H01L27/0266 , H01L27/027 , H01L27/0288 , H01L27/0629 , H01L29/0649 , H01L29/0684 , H01L29/42372 , H01L29/7827 , H01L29/785 , H01L29/7855 , H01L2029/7858
摘要： Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion.
摘要翻译：场效应二极管结构使用横截面为L形的接合结构（从平面部分延伸的翅片）。阳极位于翅片的顶面，阴极位于平面部分的端面。翅片和平面部分的垂直度导致阳极和阴极彼此垂直。第一栅极绝缘体在顶表面和平面部分之间接触翅片。第一栅极导体接触第一栅极绝缘体，并且第一栅极绝缘体位于第一栅极导体与鳍的表面之间。另外，第二栅极绝缘体接触端面和鳍之间的平面部分。第二栅极导体与第二栅极绝缘体接触，第二栅极绝缘体位于第二栅极导体与平面部分的表面之间。

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