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    • 81. 发明授权
    • Power semiconductor device architecture for output transistor protection
    • 功率半导体器件架构,用于输出晶体管保护
    • US07606015B2
    • 2009-10-20
    • US12007440
    • 2008-01-10
    • Tsuyoshi Tanabe
    • Tsuyoshi Tanabe
    • H02H3/08H02H9/02H02H3/20H02H9/04
    • H03K17/063H03K17/0822H03K2017/066
    • A power semiconductor device is provided with an output transistor, a load control circuit, and a pull-up circuit. The output transistor is connected between a power supply terminal provided to receive a power supply voltage and an output terminal to be connected with a load. The load control circuit is adapted to feed the gate voltage to the gate of the output transistor. When short-circuiting of the load occurs, the load control circuit stops feeding the gate voltage to the output transistor. The pull-up circuit is connected between the power supply terminal and the gate of the output transistor. The pull-up circuit is adapted to discharge electric charges on said gate of said output transistor, when short-circuiting of the load occurs with the voltage level on the power supply terminal lowered than the power supply voltage.
    • 功率半导体器件设置有输出晶体管,负载控制电路和上拉电路。 输出晶体管连接在被提供以接收电源电压的电源端子和要与负载连接的输出端子之间。 负载控制电路适于将栅极电压馈送到输出晶体管的栅极。 当发生负载短路时,负载控制电路停止向输出晶体管供给栅极电压。 上拉电路连接在电源端子和输出晶体管的栅极之间。 所述上拉电路适于在所述输出晶体管的所述栅极上放电,当所述电源端子上的电压电平低于所述电源电压时,发生所述负载短路。
    • 89. 发明申请
    • Power semiconductor device architecture for output transistor protection
    • 功率半导体器件架构,用于输出晶体管保护
    • US20080170345A1
    • 2008-07-17
    • US12007440
    • 2008-01-10
    • Tsuyoshi Tanabe
    • Tsuyoshi Tanabe
    • H02H3/38H02H3/08
    • H03K17/063H03K17/0822H03K2017/066
    • A power semiconductor device is provided with an output transistor, a load control circuit, and a pull-up circuit. The output transistor is connected between a power supply terminal provided to receive a power supply voltage and an output terminal to be connected with a load. The load control circuit is adapted to feed the gate voltage to the gate of the output transistor. When short-circuiting of the load occurs, the load control circuit stops feeding the gate voltage to the output transistor. The pull-up circuit is connected between the power supply terminal and the gate of the output transistor. The pull-up circuit is adapted to discharge electric charges on said gate of said output transistor, when short-circuiting of the load occurs with the voltage level on the power supply terminal lowered than the power supply voltage.
    • 功率半导体器件设置有输出晶体管,负载控制电路和上拉电路。 输出晶体管连接在被提供以接收电源电压的电源端子和要与负载连接的输出端子之间。 负载控制电路适于将栅极电压馈送到输出晶体管的栅极。 当发生负载短路时,负载控制电路停止向输出晶体管供给栅极电压。 上拉电路连接在电源端子和输出晶体管的栅极之间。 所述上拉电路适于在所述输出晶体管的所述栅极上放电,当所述电源端子上的电压电平低于所述电源电压时,发生所述负载短路。
    • 90. 发明申请
    • Image recording apparatus
    • 图像记录装置
    • US20070146456A1
    • 2007-06-28
    • US11644846
    • 2006-12-26
    • Tsuyoshi Tanabe
    • Tsuyoshi Tanabe
    • B41J2/01
    • B41J11/057B41J11/0065
    • The image recording apparatus includes a recording head ejecting ink for image recording, a rotatable platen facing the head and has recording medium support surfaces supporting one or more recording media during the image recording, respectively, a driver rotating the platen and a controller controlling the driver so as to rotate the platen in such a way that a predetermined surface selected from the surfaces is stopped at a position facing the recording head. The surfaces support the one or more recording media transported in accordance with different transport patterns, respectively and have ink receivers receiving the ink having reached outside both sides of each of the one or more recording media transported during the image recording and being disposed in positions corresponding to vicinities of both sides of each of the one or more recording media.
    • 该图像记录装置包括:用于图像记录的喷墨打印头,与头部相对的可转动的打印台,分别具有在图像记录期间支撑一个或多个记录介质的记录介质支撑表面,旋转印版的驱动器和控制驱动器的控制器 从而以使从表面选择的预定表面停止在与记录头相对的位置的方式旋转压板。 这些表面分别支撑根据不同传送模式传送的一个或多个记录介质,并且具有接收墨水的墨水接收器已经到达在图像记录期间传送的一个或多个记录介质中的每一个的两侧的外部并且被布置在相应位置 到每个一个或多个记录媒体的两侧的附近。