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81. 发明授权

US08933434B2 Elemental semiconductor material contact for GaN-based light emitting diodes 有权
标题翻译： GaN基发光二极管的元素半导体材料接触
公开(公告)号：US08933434B2
公开(公告)日：2015-01-13
申请号：US13897508
申请日：2013-05-20
申请人： International Business Machines Corporation
发明人： Anirban Basu , Bahman Hekmatshoartabari , Davood Shahrjerdi
IPC分类号： H01L33/06 , H01L29/15 , H01L33/00 , H01L33/32
CPC分类号： H01L33/06 , H01L33/0075 , H01L33/02 , H01L33/20 , H01L33/32 , H01L2933/0016
摘要： A vertical stack including a p-doped GaN portion, a multi-quantum-well, and an n-doped GaN portion is formed on an insulator substrate. The p-doped GaN portion may be formed above, or below, the multi-quantum-well. A dielectric material liner is formed around the vertical stack, and is patterned to physically expose a top surface of the p-doped GaN portion. A selective low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material on the physically exposed surfaces of the p-doped GaN portion, thereby forming an elemental semiconductor material portion. Metallization is performed on a portion of the elemental semiconductor material portions to form an electrical contact structure that provides effective electrical contact to the p-doped GaN portion through the elemental semiconductor material portion. The elemental semiconductor material portion spreads electrical current between the electrical contact structure and the p-doped GaN portion.
摘要翻译：包括p掺杂GaN部分，多量子阱和n掺杂GaN部分的垂直堆叠形成在绝缘体基板上。 p掺杂的GaN部分可以形成在多量子阱的上方或下方。在垂直叠层周围形成电介质材料衬垫，并被图案化以物理暴露p掺杂GaN部分的顶表面。采用选择性低温外延工艺将包含至少一种元素半导体材料的半导体材料沉积在p掺杂GaN部分的物理暴露表面上，从而形成元素半导体材料部分。在元素半导体材料部分的一部分上进行金属化以形成通过元素半导体材料部分向p掺杂的GaN部分提供有效的电接触的电接触结构。元素半导体材料部分在电接触结构和p掺杂GaN部分之间扩展电流。

82. 发明申请

US20140342485A1 ELEMENTAL SEMICONDUCTOR MATERIAL CONTACT FOR HIGH INDIUM CONTENT InGaN LIGHT EMITTING DIODES 审中-公开
标题翻译：元素半导体材料接触高含量InGaN发光二极管
公开(公告)号：US20140342485A1
公开(公告)日：2014-11-20
申请号：US14019726
申请日：2013-09-06
申请人： International Business Machines Corporation
发明人： Anirban Basu , Wilfried Haensch , Bahman Hekmatshoartabari , Davood Shahrjerdi
IPC分类号： H01L33/32 , H01L33/06
CPC分类号： H01L33/06 , H01L33/0075 , H01L33/02 , H01L33/20 , H01L33/32 , H01L2933/0016
摘要： A vertical stack including a p-doped GaN portion, a multi-quantum-well including indium gallium nitride layers, and an n-doped transparent conductive material portion is formed on an insulator substrate. A dielectric material liner is formed around the vertical stack, and is patterned to physically expose a surface of the p-doped GaN portion. A selective low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material on the physically exposed surfaces of the p-doped GaN portion, thereby forming an elemental semiconductor material portion. The selective low temperature epitaxy process can be performed at a temperature lower than 600° C., thereby limiting diffusion of materials within the multi-quantum well and avoiding segregation of indium within the multi-quantum well. The light-emitting diode can generate a radiation of a wide range including blue and green lights in the visible wavelength range.
摘要翻译：包括p掺杂的GaN部分，包括氮化镓镓层的多量子阱和n掺杂的透明导电材料部分的垂直堆叠形成在绝缘体基板上。在垂直堆叠周围形成电介质材料衬垫，并被图案化以物理暴露p掺杂GaN部分的表面。采用选择性低温外延工艺将包含至少一种元素半导体材料的半导体材料沉积在p掺杂GaN部分的物理暴露表面上，从而形成元素半导体材料部分。选择性低温外延工艺可以在低于600℃的温度下进行，从而限制多量子阱内材料的扩散，并避免多量子阱内铟的偏析。发光二极管可以产生宽范围的辐射，包括可见光波长范围内的蓝光和绿光。

83. 发明申请

US20140335665A1 LOW EXTENSION RESISTANCE III-V COMPOUND FIN FIELD EFFECT TRANSISTOR 有权
公开(公告)号：US20140335665A1
公开(公告)日：2014-11-13
申请号：US14021336
申请日：2013-09-09
申请人： International Business Machines Corporation
发明人： Anirban Basu , Pouya Hashemi
IPC分类号： H01L29/66
CPC分类号： H01L29/66818 , H01L29/66522 , H01L29/6653 , H01L29/66795 , H01L29/785
摘要： A gate stack including a gate dielectric and a gate electrode is formed over at least one compound semiconductor fin provided on an insulating substrate. The at least one compound semiconductor fin is thinned employing the gate stack as an etch mask. Source/drain extension regions are epitaxially deposited on physically exposed surfaces of the at least one semiconductor fin. A gate spacer is formed around the gate stack. A raised source region and a raised drain region are epitaxially formed on the source/drain extension regions. The source/drain extension regions are self-aligned to sidewalls of the gate stack, and thus ensure a sufficient overlap with the gate electrode. Further, the combination of the source/drain extension regions and the raised source/drain regions provides a low-resistance path to the channel of the field effect transistor.

84. 发明申请

US20140131286A1 LARGE-SCALE ELECTRICITY-LESS DISINFECTION OF FLUENT WATER 有权
标题翻译：大规模电力消耗水的功能
公开(公告)号：US20140131286A1
公开(公告)日：2014-05-15
申请号：US13756734
申请日：2013-02-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Anirban Basu , Stephen W. Bedell , Wilfried E. Haensch , Davood Shahrjerdi
IPC分类号： C02F1/30
CPC分类号： C02F1/325 , A61L2/00 , A61L9/00 , C02F2201/009 , C02F2201/3222 , C02F2201/3227 , C02F2209/11 , C02F2209/36 , C02F2209/40 , C02F2303/04 , Y02A20/212
摘要： A system for disinfecting a water sample includes a pipe having an inlet for engaging a source of the water sample, a storage reservoir connected to an outlet of the pipe for holding the water sample, an array of photovoltaic cells coupled to the pipe for converting solar radiation into a current, and an array of light emitting diodes coupled to the pipe and powered by the current, wherein the array of light emitting diodes emits a germicidal wavelength of radiation. A method for disinfecting a fluent water sample includes generating a current using an array of photovoltaic cells, using the current to power an array of light emitting diodes, wherein the array of light emitting diodes emits a germicidal wavelength of radiation, and exposing the fluent water sample to the radiation while transporting the fluent water sample from a source to a storage reservoir.
摘要翻译：用于对水样品进行消毒的系统包括具有用于接合水样品源的入口的管道，连接到用于保持水样品的管道出口的储存容器，耦合到管道的太阳能电池阵列，用于转换太阳能辐射成电流，以及耦合到管道并由电流供电的发光二极管阵列，其中发光二极管阵列发射杀菌波长的辐射。用于消毒流体水样品的方法包括使用光伏电池阵列产生电流，使用电流为发光二极管阵列供电，其中发光二极管阵列发射杀菌波长的辐射，并暴露流光水将流态水样品从源运送到储存容器时将样品送入辐射。

85. 发明授权

US10249719B2 Device isolation using preferential oxidation of the bulk substrate 有权
公开(公告)号：US10249719B2
公开(公告)日：2019-04-02
申请号：US15797852
申请日：2017-10-30
申请人： International Business Machines Corporation
发明人： Anirban Basu , Guy M. Cohen , Amlan Majumdar , Yu Zhu
IPC分类号： H01L29/205 , H01L29/78 , H01L29/66 , H01L21/762 , H01L21/02
摘要： A method includes providing a structure including a substrate, a buffer layer formed on the substrate and a semiconductor layer formed on the buffer layer, etching the semiconductor layer so as to form a fin and exposing the buffer layer, etching the buffer layer such that a portion of the buffer layer, disposed under the fin, is exposed, and oxidizing the buffer layer and fin so as to form an oxide layer under the fin.

86. 发明授权

US10243050B2 Device isolation using preferential oxidation of the bulk substrate 有权
公开(公告)号：US10243050B2
公开(公告)日：2019-03-26
申请号：US15797809
申请日：2017-10-30
申请人： International Business Machines Corporation
发明人： Anirban Basu , Guy M. Cohen , Amlan Majumdar , Yu Zhu
IPC分类号： H01L29/205 , H01L29/78 , H01L29/66 , H01L21/762 , H01L21/02
摘要： A structure includes a semiconductor substrate, a semiconductor buffer layer disposed on the semiconductor substrate, an oxide layer disposed on the buffer layer, and a fin including a semiconductor material disposed on the oxide layer. The fin and the buffer layer are epitaxially aligned to the semiconductor substrate.

87. 发明申请

US20180350919A1 Device Isolation for III-V Substrates 审中-公开
公开(公告)号：US20180350919A1
公开(公告)日：2018-12-06
申请号：US16040233
申请日：2018-07-19
申请人： International Business Machines Corporation
发明人： Anirban Basu , Guy M. Cohen
IPC分类号： H01L29/205 , H01L21/02 , H01L21/3065 , H01L21/8234 , H01L21/8252 , H01L29/207 , H01L21/306 , H01L21/762 , H01L29/06
CPC分类号： H01L29/205 , H01L21/02178 , H01L21/02241 , H01L21/02461 , H01L21/02463 , H01L21/02488 , H01L21/02502 , H01L21/0251 , H01L21/02543 , H01L21/02546 , H01L21/30612 , H01L21/3065 , H01L21/762 , H01L21/823431 , H01L21/8252 , H01L29/0684 , H01L29/207
摘要： Techniques for device isolation for III-V semiconductor substrates are provided. In one aspect, a method of fabricating a III-V semiconductor device is provided. The method includes the steps of: providing a substrate having an indium phosphide (InP)-ready layer; forming an iron (Fe)-doped InP layer on the InP-ready layer; forming an epitaxial III-V semiconductor material layer on the Fe-doped InP layer; and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device. A III-V semiconductor device is also provided.

88. 发明申请

US20180130884A1 DEVICE ISOLATION USING PREFERENTIAL OXIDATION OF THE BULK SUBSTRATE 审中-公开
公开(公告)号：US20180130884A1
公开(公告)日：2018-05-10
申请号：US15797809
申请日：2017-10-30
申请人： International Business Machines Corporation
发明人： Anirban Basu , Guy M. Cohen , Amlan Majumdar , Yu Zhu
IPC分类号： H01L29/205 , H01L29/78 , H01L29/66 , H01L21/762 , H01L21/02
CPC分类号： H01L29/205 , H01L21/02241 , H01L21/762 , H01L29/66795 , H01L29/785
摘要： A structure includes a semiconductor substrate, a semiconductor buffer layer disposed on the semiconductor substrate, an oxide layer disposed on the buffer layer, and a fin including a semiconductor material disposed on the oxide layer. The fin and the buffer layer are epitaxially aligned to the semiconductor substrate.

89. 发明申请

US20170271458A1 Device Isolation for III-V Substrates 审中-公开
公开(公告)号：US20170271458A1
公开(公告)日：2017-09-21
申请号：US15608538
申请日：2017-05-30
申请人： International Business Machines Corporation
发明人： Anirban Basu , Guy M. Cohen
IPC分类号： H01L29/205 , H01L21/02 , H01L21/8252 , H01L29/06 , H01L29/207 , H01L21/306 , H01L21/8234 , H01L21/3065
CPC分类号： H01L29/205 , H01L21/02178 , H01L21/02241 , H01L21/02461 , H01L21/02463 , H01L21/02488 , H01L21/02502 , H01L21/0251 , H01L21/02543 , H01L21/02546 , H01L21/30612 , H01L21/3065 , H01L21/762 , H01L21/823431 , H01L21/8252 , H01L29/0684 , H01L29/207
摘要： Techniques for device isolation for III-V semiconductor substrates are provided. In one aspect, a method of fabricating a III-V semiconductor device is provided. The method includes the steps of: providing a substrate having an indium phosphide (InP)-ready layer; forming an iron (Fe)-doped InP layer on the InP-ready layer; forming an epitaxial III-V semiconductor material layer on the Fe-doped InP layer; and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device. A III-V semiconductor device is also provided.

90. 发明申请

US20170040486A1 MULTI-JUNCTION SOLAR CELL 审中-公开
公开(公告)号：US20170040486A1
公开(公告)日：2017-02-09
申请号：US15296269
申请日：2016-10-18
申请人： International Business Machines Corporation
发明人： Anirban Basu , Bahman Hekmatshoartabari , Davood Shahrjerdi
IPC分类号： H01L31/18 , H01L31/0376 , H01L31/0687 , H01L31/028
摘要： A multi-junction solar cell comprising a high-crystalline silicon solar cell and a high-crystalline germanium solar cell. The high-crystalline silicon solar including a first p-doped layer and a n+ layer and the high-crystalline germanium solar cell including a second p layer and a heavily doped layer. The multi-junction solar cell can also be comprised of a heavily doped silicon layer on a non-light receiving back surface of the high-crystalline germanium solar cell and a tunnel junction between the high-crystalline silicon solar cell and the high-crystalline germanium solar cell.

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