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81. 发明授权

US07234027B2 Instructions for test & set with selectively enabled cache invalidate 有权
标题翻译：有选择地启用的缓存无效的测试和设置说明
公开(公告)号：US07234027B2
公开(公告)日：2007-06-19
申请号：US10045591
申请日：2001-10-24
申请人： James R. Kohn , Robert J. Baird
发明人： James R. Kohn , Robert J. Baird
IPC分类号： G06F12/00 , G06F9/52
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/30087 , G06F12/0808
摘要： A method and system for selectively enabling a cache-invalidate function supplement to a resource-synchronization instruction such as test-and-set. Some embodiments include a first processor, a first memory, at least a first cache between the first processor and the first memory, wherein the first cache caches data accessed by the first processor from the first memory, wherein the first processor executes: a resource-synchronization instruction, an instruction that enables a cache-invalidate function to be performed upon execution of the resource-synchronization instruction, and an instruction that disables the cache-invalidate function from being performed upon execution of the resource-synchronization instruction.
摘要翻译：一种用于选择性地启用对诸如测试和设置的资源同步指令的高速缓存无效功能补充的方法和系统。一些实施例包括第一处理器，第一存储器，第一处理器和第一存储器之间的至少第一高速缓存，其中第一高速缓存从第一存储器缓存由第一处理器访问的数据，其中第一处理器执行：同步指令，执行资源同步指令时执行高速缓存无效功能的指令，以及执行资源同步指令时禁止高速缓存无效功能的指令。

82. 发明申请

US20070088932A1 SYSTEM AND METHOD FOR ADDRESSING MEMORY AND TRANSFERRING DATA 有权
标题翻译：用于寻址存储器和传输数据的系统和方法
公开(公告)号：US20070088932A1
公开(公告)日：2007-04-19
申请号：US11611092
申请日：2006-12-14
申请人： Roger Bethard
发明人： Roger Bethard
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/1081
摘要： A system and method for addressing memory and transferring data, which in some embodiments include one or more processor translation look-aside buffers (TLBs) and optionally one or more I/O TLBs, and/or a block transfer engine (BTE) that optionally includes a serial cabinet-to-cabinet communications path (MLINK). In some embodiments, the processor TLBs are located within one or more common memory sections, each memory section being connected to a plurality of processors, wherein each processor TLB is associated with one of the processors. The BTE performs efficient memory-to-memory data transfers without further processor intervention. The MLINK extends the BTE functionality beyond a single cabinet.
摘要翻译：用于寻址存储器和传送数据的系统和方法，其在一些实施例中包括一个或多个处理器转换后备缓冲器（TLB）以及可选地一个或多个I / O TLB和/或块传输引擎（BTE），其可选地包括串行柜到柜通信路径（MLINK）。在一些实施例中，处理器TLB位于一个或多个公共存储器部分内，每个存储器部分连接到多个处理器，其中每个处理器TLB与处理器之一相关联。 BTE执行高效的内存到内存数据传输，无需进一步的处理器干预。 MLINK将BTE功能扩展到单个机柜之外。

83. 发明申请

US20070067556A1 APPARATUS AND METHOD FOR MEMORY BIT-SWAPPING-WITHIN-ADDRESS-RANGE CIRCUIT 失效
标题翻译：存储器位置转换 - 地址范围电路的装置和方法
公开(公告)号：US20070067556A1
公开(公告)日：2007-03-22
申请号：US11558454
申请日：2006-11-10
申请人： R. Dixon , David Resnick , Van Snyder
发明人： R. Dixon , David Resnick , Van Snyder
IPC分类号： G06F13/28
CPC分类号： G06F11/106 , G11C11/401 , G11C29/44 , G11C29/4401 , G11C29/848 , G11C2029/0401
摘要： A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.
摘要翻译：提供读取刷新（也称为“分布式刷新”）操作模式的存储器控制器和方法，其中在存储器部件的刷新速率要求内读取存储器的每一行，其中来自不同列的数据在随后的读取刷新循环中读取行，直到读取每个列地址的所有行，如果找到则擦除错误，从而提供集成到读取刷新操作中的擦除功能，而不是独立操作。为了进行擦除，安排了原子读取 - 正确写入操作。描述了可变优先级的可变定时刷新间隔。描述了集成卡自测试器和/或卡互换测试器。描述了地址范围内的存储器位交换电路，以及用于在飞行和测试中进行位交换的方法和装置。

84. 发明授权

US07191444B2 Stream management in a multithreaded environment 有权
标题翻译：在多线程环境中进行流管理
公开(公告)号：US07191444B2
公开(公告)日：2007-03-13
申请号：US10663897
申请日：2003-09-16
申请人： Gail A. Alverson , Charles David Callahan, II , Susan L. Coatney , Brian D. Koblenz , Richard D. Korry , Burton J. Smith
发明人： Gail A. Alverson , Charles David Callahan, II , Susan L. Coatney , Brian D. Koblenz , Richard D. Korry , Burton J. Smith
IPC分类号： G06F9/46
CPC分类号： G06F9/485 , G06F9/461 , G06F9/4812 , G06F9/52 , G06F2209/481
摘要： A method and system that prepares a task for being swapped out from processor utilization that is executing on a computer with multiple processors that each support multiple streams. The task has one or more teams of threads, where each team represents threads executing on a single processor. The task designates, for each stream that is executing a thread, one stream as a team master stream and one stream as a task master stream. For each team master stream, the task notifies the operating system that the team is ready to be swapped out when each other thread of the team has saved its state and has quit its stream. Finally, for the task master stream, the task notifies the operating system that the task is ready to be swapped when it has saved its state and each other team has notified that it is ready to be swapped out.
摘要翻译：一种方法和系统，准备一个从处理器利用率交换的任务，该处理器利用率在每台支持多个流的多个处理器的计算机上执行。该任务具有一个或多个线程团队，每个团队都表示在单个处理器上执行的线程。该任务为执行线程的每个流指定一个流作为团队主流，一个流作为任务主流。对于每个团队主流，任务通知操作系统，当团队的每个其他线程已保存其状态并已退出其流时，该团队已准备好进行交换。最后，对于任务主流，任务通知操作系统当任务准备好被交换时，它已经保存了状态，并且每个其他的团队已经通知它已经准备好被换出了。

85. 发明授权

US07184916B2 Apparatus and method for testing memory cards 有权
标题翻译：用于测试存储卡的装置和方法
公开(公告)号：US07184916B2
公开(公告)日：2007-02-27
申请号：US10850044
申请日：2004-05-19
申请人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
发明人： David R. Resnick , Gerald A. Schwoerer , Kelly J. Marquardt , Alan M. Grossmeier , Michael L. Steinberger , Van L. Snyder , Roger A. Bethard
IPC分类号： G06F19/00
CPC分类号： G11C29/4401 , G11C11/401 , G11C29/26 , G11C29/44 , G11C2029/0401 , G11C2029/4002
摘要： A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to be programmed and controlled by a test controller on a test fixture that allows simultaneous testing of a single MDC or one or more pairs of MDCs, one MDC in a pair (e.g., the “golden” MDC) testing the other MDC of that pair. Other methods are also described, wherein one MDC executes a series of reads and writes and other commands to another MDC to test at least some of the other card's functions, or wherein one port executes a series of test commands to another port on the same MDC to test at least some of the card's functions.
摘要翻译：描述了一种存储器子卡（MDC），具有非常高速的串行接口和一个卡片MDC测试引擎，允许一个MDC直接连接到另一个MDC进行测试。在一些实施例中，控制接口允许测试引擎由测试夹具上的测试控制器编程和控制，所述测试夹具允许同时测试单个MDC或一对或多对MDC，一对MDC（例如“ 金“MDC）测试该对的其他MDC。还描述了其他方法，其中一个MDC执行一系列读写和其他命令到另一个MDC以测试其他卡的至少一些功能，或者其中一个端口对同一MDC上的另一个端口执行一系列测试命令至少测试一些卡的功能。

86. 发明授权

US07146517B2 Clock pulse shaver with selective enable pulse width 有权
标题翻译：时钟脉冲剃须刀，带有选择使能脉冲宽度
公开(公告)号：US07146517B2
公开(公告)日：2006-12-05
申请号：US10137060
申请日：2002-05-02
申请人： Stephen B. Smetana
发明人： Stephen B. Smetana
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A clock for a computing system. The clock includes a first pulse shaver and a first pin connected to the first pulse shaver. The first pin selectively enables the first pulse shaver to reduce the width of enabling pulses in a clock signal passing through the first pulse shaver. A method for synchronizing data flow in a computing system. The method includes generating pulses; selectively reducing the width of the pulses; and delivering the pulses to a memory element.
摘要翻译：计算系统的时钟。时钟包括第一脉冲剃须刀和连接到第一脉冲剃须刀的第一引脚。第一针选择性地使第一脉冲剃须刀能够减小通过第一脉冲剃须刀的时钟信号中的使能脉冲的宽度。一种用于在计算系统中同步数据流的方法。该方法包括产生脉冲; 选择性地减小脉冲的宽度; 并将脉冲传送到存储元件。

87. 发明申请

US20040150446A1 Systems and methods for phase detector circuit with reduced offset 失效
标题翻译：具有减小偏移的相位检测器电路的系统和方法
公开(公告)号：US20040150446A1
公开(公告)日：2004-08-05
申请号：US10357716
申请日：2003-02-04
申请人： Cray Inc.
发明人： Mark S. Birrittella
IPC分类号： H03L007/06
CPC分类号： H03L7/091 , H03L7/0814
摘要： Systems and methods for synchronizing a system clock signal with a reference clock signal having a reduced phased offset to improve operating speeds of integrated circuits. This is accomplished by generating delayed system and reference clock signals by using the system and reference clock signals. The generated delayed clock signals are then monitored to determine the arrival of the raising and falling edges of the delayed clock signals. The system clock signal is then compensated based on the determination of the arrival of the delayed clock signals to substantially synchronize the system clock signal with respect to the reference clock signal.
摘要翻译：用于使系统时钟信号与具有减小的相位偏移的参考时钟信号同步的系统和方法，以提高集成电路的操作速度。这可以通过使用系统和参考时钟信号产生延迟的系统和参考时钟信号来实现。然后监视产生的延迟时钟信号以确定延迟的时钟信号的上升沿和下降沿的到达。然后，基于延迟的时钟信号的到达的确定来补偿系统时钟信号，以基本上使系统时钟信号相对于参考时钟信号同步。

88. 发明申请

US20040003367A1 Boolean gate definition 有权
公开(公告)号：US20040003367A1
公开(公告)日：2004-01-01
申请号：US10185177
申请日：2002-06-28
申请人： Cray Inc.
发明人： Robert J. Lutz
IPC分类号： G06F017/50
CPC分类号： G06F17/5045
摘要： A method of instantiating a leaf cell having various connections and designed to be called using a fixed syntax includes defining a template syntax different from the fixed syntax, setting default values for connections not designated by the template syntax, and mapping the template syntax to a hardware design language. The description of the leaf cell has values for the designated connections and non-designated connections. The non-designated connections have the default values. Another method includes instantiating a leaf cell using a first template syntax or a second template syntax. The second template syntax instantiates the same leaf cell as the first template syntax or the fixed syntax. In addition, more than one leaf cell, also known as a branch, can be instantiated using the template syntax. Articles of manufacture that include a computer readable media having instructions thereon for causing a suitably programmed system to execute one or more of the above methods of instantiating a leaf cell or leaf cells are also discussed.

89. 发明申请

US20030079090A1 Instructions for test & set with selectively enabled cache invalidate 有权
标题翻译：有选择地启用的缓存无效的测试和设置说明
公开(公告)号：US20030079090A1
公开(公告)日：2003-04-24
申请号：US10045591
申请日：2001-10-24
申请人： Cray Inc.
发明人： James R. Kohn , Robert J. Baird
IPC分类号： G06F012/00
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/30087 , G06F12/0808
摘要： A method and system for selectively enabling a cache-invalidate function supplement to a resource-synchronization instruction such as test-and-set. Some embodiments include a first processor, a first memory, at least a first cache between the first processor and the first memory, wherein the first cache caches data accessed by the first processor from the first memory, wherein the first processor executes: a resource-synchronization instruction, an instruction that enables a cache-invalidate function to be performed upon execution of the resource-synchronization instruction, and an instruction that disables the cache-invalidate function from being performed upon execution of the resource-synchronization instruction.
摘要翻译：一种用于选择性地启用对诸如测试和设置的资源同步指令的高速缓存无效功能补充的方法和系统。一些实施例包括第一处理器，第一存储器，第一处理器和第一存储器之间的至少第一高速缓存，其中第一高速缓存从第一存储器缓存由第一处理器访问的数据，其中第一处理器执行：同步指令，执行资源同步指令时执行高速缓存无效功能的指令，以及执行资源同步指令时禁止高速缓存无效功能的指令。

90. 发明申请

US20210274648A1 ASYMMETRIC DIFFERENTIAL VIA STUBS FOR SKEW COMPENSATION 有权
公开(公告)号：US20210274648A1
公开(公告)日：2021-09-02
申请号：US16805517
申请日：2020-02-28
申请人： Cray Inc.
发明人： Hyunjun Kim , Andrew J. Becker , Paul T. Wildes
IPC分类号： H05K1/02 , H01P3/08 , H01P11/00 , H05K3/00 , H05K3/42 , H05K3/46
摘要： One embodiment can provide a method and system for compensating for timing skew in a differential pair transmission line on a printed circuit board (PCB). During operation, the system obtains a PCB comprising one or more layers and at least a differential pair transmission line. The differential pair transmission line comprises first and second transmission lines, with a respective transmission line coupled to at least one via extending through the one or more layers of the PCB. The system determines a difference in length between first and second transmission lines and determines a stub length of the at least one via based on the determined difference in length between the first and second transmission lines, thereby compensating for the time skew in the differential pair transmission line.

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