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81. 发明申请

US20110252206A1 MEMORY PROGRAMMING USING VARIABLE DATA WIDTH 失效
标题翻译：使用可变数据宽度进行存储器编程
公开(公告)号：US20110252206A1
公开(公告)日：2011-10-13
申请号：US13008522
申请日：2011-01-18
申请人： Hong Beom Pyeon
发明人： Hong Beom Pyeon
IPC分类号： G06F12/02 , G11C11/00
CPC分类号： G11C7/1015 , G11C7/1006 , G11C13/0004 , G11C13/0069 , G11C2013/0085 , G11C2013/0088
摘要： A memory system comprises a memory including a plurality of bits arranged as one or more words. Each bit in each word is capable of being programmed either to a particular logical state or to another logical state. A variable data width controller is in communication with the memory. The variable data width controller comprises an adder to determine a programming number of bits in a word to be programmed into a memory. Each bit to be programmed is in the particular logical state. A partitioning block divides the word in to two or more sub-words when the programming number exceeds a maximum number. A switch is in communication with the partitioning block. The switch sequentially provides one or more write pulses. Each write pulse enables a separate communication path between the memory and one of the word and the sub-words.
摘要翻译：存储器系统包括存储器，该存储器包括排列成一个或多个单词的多个位。每个单词中的每个位都能够被编程到特定的逻辑状态或另一个逻辑状态。可变数据宽度控制器与存储器通信。可变数据宽度控制器包括加法器，用于确定要编程到存储器中的一个字中的位的编程位数。要编程的每个位处于特定的逻辑状态。当编程号码超过最大数量时，划分块将字分成两个或多个子字。开关与分区块通信。开关依次提供一个或多个写入脉冲。每个写入脉冲使得存储器与字和子字中的一个之间的单独通信路径成为可能。

82. 发明授权

US08000430B2 Wide frequency range delay locked loop 有权
标题翻译：宽频率范围延迟锁定环路
公开(公告)号：US08000430B2
公开(公告)日：2011-08-16
申请号：US11999162
申请日：2007-12-04
申请人： Peter Vlasenko , Dieter Haerle
发明人： Peter Vlasenko , Dieter Haerle
IPC分类号： H03D3/24
CPC分类号： H03L7/081 , H03L7/0814 , H03L7/0818 , H03L7/0891 , H03L7/095 , H03L7/10
摘要： A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.
摘要翻译：延迟锁定环路在宽频率范围内工作，具有高精度，小面积使用，低功耗和短锁定时间。该DLL结合了模拟域和数字域。数字域负责初始锁定和操作点稳定性，并在达到锁定后冻结。模拟域在达到锁定后负责正常运行，并使用较小的硅面积和低功耗提供高精度。

83. 发明申请

US20110194365A1 BRIDGE DEVICE ARCHITECTURE FOR CONNECTING DISCRETE MEMORY DEVICES TO A SYSTEM 有权
标题翻译：用于将分离存储器件连接到系统的桥接器件结构
公开(公告)号：US20110194365A1
公开(公告)日：2011-08-11
申请号：US13091465
申请日：2011-04-21
申请人： Jin-Ki KIM , HakJune OH , Hong Beom PYEON
发明人： Jin-Ki KIM , HakJune OH , Hong Beom PYEON
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C5/02 , G11C5/025
摘要： Bridge device architecture for connecting discrete memory devices is disclosed. A bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device comprises a local control interface connected to the at least one discrete memory device, a local input/output interface connected to the at least one discrete memory device, and a global input/output interface interposed between the local control interface and the local input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device.
摘要翻译：公开了用于连接分立存储器件的桥接器件架构。桥接器件与包括至少一个分立存储器件的复合存储器件结合使用。桥接设备包括连接到至少一个分立存储器设备的本地控制接口，连接到至少一个分立存储器设备的本地输入/输出接口以及插入本地控制接口和本地控制接口之间的全局输入/输出接口输入/输出接口。全局输入/输出接口接收并提供全局存储器控制信号，并且还接收并向至少一个离散存储器件提供写入数据和从其读取数据。

84. 发明授权

US07983099B2 Dual function compatible non-volatile memory device 有权
标题翻译：双功能兼容的非易失性存储设备
公开(公告)号：US07983099B2
公开(公告)日：2011-07-19
申请号：US12258056
申请日：2008-10-24
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C7/00
CPC分类号： G11C16/06 , G11C5/14 , G11C5/143 , G11C7/20 , G11C16/20
摘要： A dual function memory device architecture compatible with asynchronous operation and synchronous serial operation. The dual function memory device architecture includes one set of physical ports having two different functional assignments. Coupled between the physical ports and core circuits of the memory device are asynchronous and synchronous input and output signal paths or circuits. The signal paths include shared or dedicated buffers coupled to the ports, asynchronous and synchronous command decoders, a network of switches, and a mode detector. The mode detector determines the operating mode of the dual function memory device from a port, and provides the appropriate switch selection signal. The network of switches routes the input or output signals through the asynchronous or synchronous circuits in response to the switch selection signal. The appropriate command decoder interprets the input signals and provides common control logic with the necessary signals for initiating the corresponding operation.
摘要翻译：兼容异步操作和同步串行操作的双功能存储器件架构。双功能存储设备架构包括具有两个不同功能分配的一组物理端口。存储器件的物理端口和核心电路之间的耦合是异步和同步的输入和输出信号路径或电路。信号路径包括耦合到端口的共享或专用缓冲器，异步和同步命令解码器，开关网络和模式检测器。模式检测器从端口确定双功能存储器件的工作模式，并提供适当的开关选择信号。开关网络响应于开关选择信号，通过异步或同步电路路由输入或输出信号。适当的命令解码器解释输入信号，并提供公共控制逻辑与启动相应操作的必要信号。

85. 发明申请

US20110170367A1 DYNAMIC RANDOM ACCESS MEMORY WITH FULLY INDEPENDENT PARTIAL ARRAY REFRESH FUNCTION 有权
标题翻译：具有完全独立部分阵列刷新功能的动态随机访问记忆
公开(公告)号：US20110170367A1
公开(公告)日：2011-07-14
申请号：US13072097
申请日：2011-03-25
申请人： Jin-Ki KIM , HakJune OH
发明人： Jin-Ki KIM , HakJune OH
IPC分类号： G11C11/402
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/40622
摘要： A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store cells are connected. Partial array self-refresh (PASR) configuration settings are independently made. In accordance with the PASR settings, the memory subblocks are addressed for refreshing. The PASR settings are made by a memory controller. Any kind of combinations of subblock addresses may be selected. Thus, the memory subblocks are fully independently refreshed. User selectable memory arrays for data retention provide effective memory control programming especially for low power mobile application.
摘要翻译：动态随机存取存储器件包括多个存储器子块。每个子块具有连接多个数据存储单元的多个字线。部分阵列自刷新（PASR）配置设置是独立制作的。根据PASR设置，内存子块被寻址以进行刷新。 PASR设置由内存控制器进行。可以选择子块地址的任何种类的组合。因此，存储器子块被完全独立地刷新。用于数据保留的用户可选择的存储器阵列提供有效的存储器控制编程，特别是对于低功率

86. 发明申请

US20110153974A1 SYSTEM AND METHOD OF OPERATING MEMORY DEVICES OF MIXED TYPE 有权
标题翻译：混合型记忆装置的操作系统及方法
公开(公告)号：US20110153974A1
公开(公告)日：2011-06-23
申请号：US13038997
申请日：2011-03-02
申请人： Jin-Ki Kim , HakJune Oh , Hong Beom Pyeon
发明人： Jin-Ki Kim , HakJune Oh , Hong Beom Pyeon
IPC分类号： G06F12/00
CPC分类号： G06F13/4239 , G11C16/08 , G11C16/20 , G11C2216/30
摘要： A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, NAND-type flash memory, NOR-type flash memory, random access memory and static random access memory. Each memory command is specific to the memory type of a target memory device. A data path for the memory commands and the memory responses is provided by the interconnection. A given memory command traverses memory devices in order to reach its intended memory device of the serial interconnection configuration. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to a next memory device. The memory response is transferred to the memory controller.
摘要翻译：提供了存储器系统结构，其中存储器控制器控制串行互连配置中的存储器件。存储器控制器具有用于发送存储器命令的输出端口和用于接收用于请求这样的响应的那些存储器命令的存储器响应的输入端口。每个存储器件包括诸如NAND型闪存，NOR型闪速存储器，随机存取存储器和静态随机存取存储器之类的存储器。每个存储器命令特定于目标存储器件的存储器类型。存储器命令和存储器响应的数据路径由互连提供。给定的存储器命令遍历存储器件以达到其串行互连配置的预期存储器件。在其接收时，预期的存储器件执行给定的存储器命令，并且如果适当的话，向下一个存储器件发送存储器响应。存储器响应被传送到存储器控制器。

87. 发明授权

US07962758B2 Method and apparatus for processing arbitrary key bit length encryption operations with similar efficiencies 有权
标题翻译：用于处理类似效率的任意密钥位长加密操作的方法和装置
公开(公告)号：US07962758B2
公开(公告)日：2011-06-14
申请号：US12287864
申请日：2008-10-14
申请人： Hafid Zaabab
发明人： Hafid Zaabab
IPC分类号： G06F21/00 , G06F11/30
CPC分类号： G06F7/728
摘要： A calculating apparatus, or system, having a plurality of stages, such as in a pipeline arrangement, has the clocking rail or conductor positioned alongside the stages. With a large number, i.e., hundreds, of stages arranged in parallel sub-arrays, the clocking conductor is snaked alongside the sub-arrays. In individual stages it is arranged that the shortest of the two calculations taking place in a stage, takes place in the return path. An array can be divided into separate sections for independent processing.
摘要翻译：具有多个级的计算装置或系统，例如在管道装置中，具有定时轨道或者导体位于该级的旁边。具有排列成并行子阵列的大量，即数百个级，时钟导体与子阵列一起被蛇形。在单个阶段，排列是在一个阶段中进行的最短的两次计算发生在返回路径中。阵列可分为独立的部分，用于独立处理。

88. 发明授权

US07957173B2 Composite memory having a bridging device for connecting discrete memory devices to a system 有权
标题翻译：具有用于将分立存储器件连接到系统的桥接装置的复合存储器
公开(公告)号：US07957173B2
公开(公告)日：2011-06-07
申请号：US12401963
申请日：2009-03-11
申请人： Jin-Ki Kim
发明人： Jin-Ki Kim
IPC分类号： G11C7/02
CPC分类号： G11C7/00 , G11C5/02 , G11C5/025
摘要： A composite memory device including discrete memory devices and a bridge device for controlling the discrete memory devices in response to global memory control signals having a format or protocol that is incompatible with the memory devices. The discrete memory devices can be commercial off-the-shelf memory devices or custom memory devices which respond to native, or local memory control signals. The global and local memory control signals include commands and command signals each having different formats. The composite memory device includes a system in package including the semiconductor dies of the discrete memory devices and the bridge device, or can include a printed circuit board having packaged discrete memory devices and a packaged bridge device mounted thereto.
摘要翻译：一种复合存储器件，包括分立存储器件和用于响应具有与存储器件不兼容的格式或协议的全局存储器控制信号来控制分立存储器件的桥接器件。分立存储器件可以是对现有或本地存储器控制信号进行响应的商业现成存储器件或定制存储器件。全局和本地存储器控制信号包括各自具有不同格式的命令和命令信号。复合存储器件包括包括分立存储器件和桥接器件的半导体管芯的封装的系统，或者可以包括具有封装的分立存储器件的印刷电路板和安装在其上的封装桥接器件。

89. 发明申请

US20110110388A1 METHOD AND APPARATUS FOR REDUCING THE AMPLITUDE MODULATION OF OPTICAL SIGNALS IN EXTERNAL CAVITY LASERS 有权
标题翻译：用于减少外部激光激光器中光信号振幅调制的方法和装置
公开(公告)号：US20110110388A1
公开(公告)日：2011-05-12
申请号：US12936723
申请日：2008-04-11
申请人： Paolo Baroni , Marco De Donno , Anna Ronchi
发明人： Paolo Baroni , Marco De Donno , Anna Ronchi
IPC分类号： H01S3/10
CPC分类号： H01S3/10038 , H01S3/1055 , H01S5/02216 , H01S5/02248 , H01S5/02284 , H01S5/02415 , H01S5/02476 , H01S5/02492 , H01S5/062 , H01S5/06213 , H01S5/06246 , H01S5/06251 , H01S5/0653 , H01S5/0683 , H01S5/10 , H01S5/101 , H01S5/141
摘要： The present invention concerns a laser apparatus (200) comprising an external cavity laser (ECL) in which the optical signal is modulated by an electrical modulation signal with the purpose of modulating in frequency the laser output signal. The modulation in frequency produces in turn a modulation of intensity (power) of the laser output signal, also denoted amplitude modulation (AM). A method is described of control of the AM amplitude of a signal emitted by an ECL that comprises a gain medium (205), a phase element (206) with variable transmissivity induced by the modulation and a spectrally selective optical filter (209) and that selects and keeps the AM amplitude below a certain desired value or minimizes such value. A control method and a laser apparatus (200) are also described in which the reduction of the AM component of the output power is achieved by acting on the gain of the gain medium of the ECL in such way that the variation of transmissivity caused by the modulation applied to a phase element (206) is at least partially compensated by a corresponding variation of the gain current of the gain medium so as to reduce or to minimize the variation of the loop gain of the laser cavity induced by the modulation.
摘要翻译：本发明涉及一种包括外腔激光器（ECL）的激光装置（200），其中光信号由电调制信号调制，目的是在频率上调制激光输出信号。频率调制又产生激光输出信号的强度（功率）的调制，也称为振幅调制（AM）。描述了一种控制由ECL发射的信号的AM幅度的控制，其包括增益介质（205），由调制引起的具有可变透射率的相位元件（206）和光谱选择性滤光器（209），并且选择并保持AM振幅低于一定的期望值或使这个值最小化。还描述了一种控制方法和激光装置（200），其中通过以ECL的增益介质的增益作用于输出功率的AM分量的减小，使得由至少部分地通过增益介质的增益电流的相应变化补偿施加到相位元件（206）的调制，以便减少或最小化由调制引起的激光腔的环路增益的变化。

90. 发明申请

US20110110165A1 CLOCK MODE DETERMINATION IN A MEMORY SYSTEM 有权
标题翻译：记忆系统中的时钟模式确定
公开(公告)号：US20110110165A1
公开(公告)日：2011-05-12
申请号：US13006005
申请日：2011-01-13
申请人： Peter B. GILLINGHAM , Graham ALLAN
发明人： Peter B. GILLINGHAM , Graham ALLAN
IPC分类号： G11C8/18 , G11C7/10
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/0688 , G06F13/1694 , G11C7/1045 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C14/0018 , G11C16/0483 , G11C16/10 , G11C16/28 , G11C16/32 , H03K2005/00247 , Y02D10/14
摘要： A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.
摘要翻译：描述了用于存储器件的时钟模式配置电路。存储器系统包括彼此串行连接的任何数量的存储器件，其中每个存储器件接收时钟信号。可以将时钟信号并行地提供给所有存储器件，或者通过公共时钟输入从存储器件到存储器器件串行提供。每个存储器件中的时钟模式配置电路被设置为用于接收并行时钟信号的并行模式，以及用于从先前存储器件接收源同步时钟信号的串行模式。根据设置的工作模式，数据输入电路将被配置为相应的数据信号格式，相应的时钟输入电路将被启用或禁用。通过感测提供给每个存储器件的参考电压的电压电平来设置并联模式和串行模式。

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