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81. 发明授权

US09477441B2 Double rounded combined floating-point multiply and add 有权
公开(公告)号：US09477441B2
公开(公告)日：2016-10-25
申请号：US14948943
申请日：2015-11-23
申请人： Intel Corporation
发明人： Sridhar Samudrala , Grigorios Magklis , Marc Lupon , David R. Ditzel
IPC分类号： G06F7/38 , G06F7/487 , G06F7/483 , G06F7/544 , G06F7/485 , G06F7/499
CPC分类号： G06F7/4876 , G06F7/483 , G06F7/485 , G06F7/4991 , G06F7/49915 , G06F7/5443 , G06F2207/4802
摘要： Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector SIMD instructions or as fused micro-operations. Embodiments include detecting floating-point (FP) multiplication operations and subsequent FP operations specifying as source operands results of the FP multiplications. The FP multiplications and the subsequent FP operations are encoded as combined FP operations including rounding of the results of FP multiplication followed by the subsequent FP operations. The encoding of said combined FP operations may be stored and executed as part of an executable thread portion using fused-multiply-add hardware that includes overflow detection for the product of FP multipliers, first and second FP adders to add third operand addend mantissas and the products of the FP multipliers with different rounding inputs based on overflow, or no overflow, in the products of the FP multiplier. Final results are selected respectively using overflow detection.

82. 发明申请

US20160239266A1 Executing Perform Floating Point Operation Instructions 审中-公开
标题翻译：执行浮点运算指令
公开(公告)号：US20160239266A1
公开(公告)日：2016-08-18
申请号：US15137272
申请日：2016-04-25
申请人： International Business Machines Corporation
发明人： Michael H. T. Hack , Ronald M. Smith, SR.
IPC分类号： G06F7/483 , G06F7/499
CPC分类号： G06F7/483 , G06F7/4991 , G06F9/30014 , G06F9/30025 , G06F9/30094 , G06F9/30181
摘要： A method and system are disclosed for executing a machine instruction in a central processing unit. The method comprises the steps of obtaining a perform floating-point operation instruction; obtaining a test bit; and determining a value of the test bit. If the test bit has a first value, (a) a specified floating-point operation function is performed, and (b) a condition code is set to a value determined by said specified function. If the test bit has a second value, (c) a check is made to determine if said specified function is valid and installed on the machine, (d) if said specified function is valid and installed on the machine, the condition code is set to one code value, and (e) if said specified function is either not valid or not installed on the machine, the condition code is set to a second code value.
摘要翻译：公开了用于在中央处理单元中执行机器指令的方法和系统。该方法包括以下步骤：获取执行浮点运算指令; 获得一个测试位; 并确定测试位的值。如果测试位具有第一值，则（a）执行指定的浮点运算功能，并且（b）条件代码被设置为由所述指定函数确定的值。如果测试位具有第二个值，（c）进行检查以确定所述指定的功能是否有效并且安装在机器上，（d）如果所述指定的功能是有效的并且安装在机器上，则设置条件代码到一个代码值，以及（e）如果所述指定的功能无效或未安装在机器上，则条件代码被设置为第二代码值。

83. 发明授权

US09361100B2 Packing saturated lower 8-bit elements from two source registers of packed 16-bit elements 有权
标题翻译：从包装的16位元素的两个源寄存器中包装饱和的低8位元素
公开(公告)号：US09361100B2
公开(公告)日：2016-06-07
申请号：US13730845
申请日：2012-12-29
申请人： Intel Corporation
发明人： Alexander D. Peleg , Yaakov Yaari , Millind Mittal , Larry M. Mennemeier , Benny Eitan
IPC分类号： G06F9/315 , G06F9/30 , G06F7/499
CPC分类号： G06F9/30036 , G06F7/49921 , G06F9/30025 , G06F9/30032 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/30196
摘要： A processor includes a first register with first, second, third, and fourth data elements. A second register to hold fifth, sixth, seventh, and eighth data elements, and a third register. A decoder to decode a packed instruction to identify the first and second registers as source registers and the third register as a destination register. And to decode a pack instruction to identify a fourth and a fifth register each having 16-bit data elements. At least one functional unit, responsive to the packed instruction, to store a result in the third register including only half of all data elements of each of the first and second registers, including only corresponding data elements from corresponding positions in the first and second registers, and responsive to the pack instruction to store a result that is to include an 8-bit data element for each 16-bit data element in the fourth and fifth registers.
摘要翻译：处理器包括具有第一，第二，第三和第四数据元素的第一寄存器。第二寄存器，用于保存第五，第六，第七和第八数据元素，以及第三寄存器。解码器，用于解码压缩指令以将第一和第二寄存器识别为源寄存器，将第三寄存器识别为目的地寄存器。并且解码包指令以识别每个具有16位数据元素的第四和第五寄存器。响应于打包指令的至少一个功能单元将结果存储在第三寄存器中，仅包括第一和第二寄存器中的每一个的所有数据元素的一半，其中仅包括来自第一和第二寄存器中的相应位置的相应数据元素并且响应于包指令来存储在第四和第五寄存器中为每个16位数据元素包括8位数据元素的结果。

84. 发明申请

US20160124714A1 EXCEPTION GENERATION WHEN GENERATING A RESULT VALUE WITH PROGRAMMABLE BIT SIGNIFICANCE 有权
标题翻译：当产生具有可编程位意义的结果值时的异常生成
公开(公告)号：US20160124714A1
公开(公告)日：2016-05-05
申请号：US14582978
申请日：2014-12-24
申请人： ARM Limited
发明人： David Raymond LUTZ , Neil BURGESS , Christopher Neal HINDS
IPC分类号： G06F7/499 , G06F7/483
CPC分类号： G06F7/483 , G06F5/012 , G06F7/38 , G06F7/48 , G06F7/4991 , G06F7/49915 , G06F7/49921 , G06F7/49942 , G06F7/506 , G06F7/507 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30036 , G06F9/30112 , G06F9/3016 , G06F9/30185 , G06F9/30192 , G06F9/3885 , G06F11/3404 , G06F11/3476 , G06F11/348 , G06F11/3636 , G06F11/3644 , G06F11/3648 , G06F17/16 , G06F2201/865 , G06F2207/483 , H03M7/12 , H03M7/24
摘要： A data processing system performs processing operations upon input operand(s) having a programmable bit significance. Exception generating circuitry generates exception indications representing exceptions such as overflow, underflow and inexact in respect of a result value having the programmable bit significance.
摘要翻译：数据处理系统对具有可编程位有效位的输入操作数执行处理操作。异常产生电路产生异常指示，表示异常，例如溢出，下溢和不精确的具有可编程位重要性的结果值。

85. 发明申请

US20160077802A1 DOUBLE ROUNDED COMBINED FLOATING-POINT MULTIPLY AND ADD 有权
标题翻译：双重圆形组合浮点数乘法和加法
公开(公告)号：US20160077802A1
公开(公告)日：2016-03-17
申请号：US14948943
申请日：2015-11-23
申请人： Intel Corporation
发明人： Sridhar Samudrala , Grigorios Magklis , Marc Lupon , David R. Ditzel
IPC分类号： G06F7/487 , G06F7/499 , G06F7/485
CPC分类号： G06F7/4876 , G06F7/483 , G06F7/485 , G06F7/4991 , G06F7/49915 , G06F7/5443 , G06F2207/4802
摘要： Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector SIMD instructions or as fused micro-operations. Embodiments include detecting floating-point (FP) multiplication operations and subsequent FP operations specifying as source operands results of the FP multiplications. The FP multiplications and the subsequent FP operations are encoded as combined FP operations including rounding of the results of FP multiplication followed by the subsequent FP operations. The encoding of said combined FP operations may be stored and executed as part of an executable thread portion using fused-multiply-add hardware that includes overflow detection for the product of FP multipliers, first and second FP adders to add third operand addend mantissas and the products of the FP multipliers with different rounding inputs based on overflow, or no overflow, in the products of the FP multiplier. Final results are selected respectively using overflow detection.
摘要翻译：公开了提供双向组合浮点乘法和附加功能作为标量或向量SIMD指令或作为融合微操作的方法，装置，指令和逻辑。实施例包括检测浮点（FP）乘法运算和指定作为FP乘法的源操作数结果的后续FP操作。 FP乘法和随后的FP操作被编码为组合FP操作，包括对FP乘法的结果进行舍入，随后是随后的FP操作。所述组合FP操作的编码可以作为可执行线程部分的一部分使用融合乘法硬件来存储和执行，所述融合乘法加法器包括用于FP乘法器的乘积的溢出检测，第一和第二FP加法器来添加第三操作数加法尾数，基于FP乘法器产品中溢出或不溢出的FP乘法器的不同舍入输入的产品。分别使用溢出检测选择最终结果。

86. 发明授权

US09244654B2 Decimal floating-point quantum exception detection 有权
标题翻译：十进制浮点量子异常检测
公开(公告)号：US09244654B2
公开(公告)日：2016-01-26
申请号：US13544338
申请日：2012-07-09
申请人： Michael F. Cowlishaw , Silvia Melitta Mueller , Eric Schwarz , Phil C. Yeh
发明人： Michael F. Cowlishaw , Silvia Melitta Mueller , Eric Schwarz , Phil C. Yeh
IPC分类号： G06F11/00 , G06F7/499 , G06F9/30 , G06F9/38
CPC分类号： G06F7/49905 , G06F9/30014 , G06F9/30094 , G06F9/3865 , G06F2207/4911
摘要： A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.
摘要翻译：用于检测十进制浮点数据处理异常的系统和方法。一个处理器接受至少一个十进制浮点操作数，并对至少一个十进制浮点运算执行十进制浮点运算，以产生一个十进制浮点运算结果。确定十进制浮点结果是否不能保持优选的量子。优选的量子表示由十进制浮点结果的有效位的最低有效位表示的值。提供输出，响应于确定十进制浮点结果不能保持优选量子，指示量子异常的发生。可以生成立即捕获或稍后检测到的可屏蔽异常以控制条件处理。

87. 发明授权

US09223751B2 Performing rounding operations responsive to an instruction 有权
标题翻译：根据指令执行舍入操作
公开(公告)号：US09223751B2
公开(公告)日：2015-12-29
申请号：US11525420
申请日：2006-09-22
申请人： Ronen Zohar , Shane Story
发明人： Ronen Zohar , Shane Story
IPC分类号： G06F9/30 , G06F17/10 , G06F7/499
CPC分类号： G06F9/30014 , G06F7/49947 , G06F9/30025 , G06F9/30036 , G06F9/30167 , G06F9/30181 , G06F9/30185 , G06F17/10
摘要： In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在处理器中接收舍入指令和立即值的方法，确定立即值的舍入模式超驰指示符是否是活动的，并且如果这样执行对源操作数的舍入操作处理器的浮点单元响应于舍入指令，并根据立即操作数中列出的舍入模式。描述和要求保护其他实施例。

88. 发明授权

US09141586B2 Method, apparatus, system for single-path floating-point rounding flow that supports generation of normals/denormals and associated status flags 有权
标题翻译：用于单路径浮点舍入流的方法，装置，系统，其支持法线/代数的生成和相关联的状态标志
公开(公告)号：US09141586B2
公开(公告)日：2015-09-22
申请号：US13725268
申请日：2012-12-21
申请人： Warren E. Ferguson , Brian J. Hickmann , Thomas D. Fletcher
发明人： Warren E. Ferguson , Brian J. Hickmann , Thomas D. Fletcher
IPC分类号： G06F7/499 , G06F17/10 , G06F7/00
CPC分类号： G06F17/10 , G06F7/00 , G06F7/4991 , G06F7/49942 , G06F7/49968 , G06F7/49973 , G06F9/30014 , G06F9/30094
摘要： A mechanism for performing single-path floating-point rounding in a floating point unit is disclosed. A system of the disclosure includes a memory and a processing device communicably coupled to the memory. In one embodiment, the processing device comprises a floating point unit (FPU) to generate a plurality of status flags for a rounded value of a finite nonzero number. The plurality of status flags are generated based on the finite nonzero number without calculating the rounded value of the finite nonzero number. The plurality of status flags comprises an overflow flag and an underflow flag. The FPU determines whether a rounded value should be calculated for the finite nonzero number based on the plurality of status flags and whether the overflow flag is asserted. Upon determining that the rounded value should be calculated for the finite nonzero number based on the plurality of status flags and that the overflow flag is asserted, the FPU calculates the rounded value of the finite nonzero number based on an overflow rounding. Upon determining that the rounded value should be calculated for the finite nonzero number based on the plurality of status flags and that the overflow flag is not asserted, the FPU calculates the rounded value of the finite nonzero number based on a blended reduced precision rounding.
摘要翻译：公开了一种用于在浮点单元中执行单路径浮点舍入的机构。本公开的系统包括可通信地耦合到存储器的存储器和处理装置。在一个实施例中，处理装置包括浮点单元（FPU），用于为有限非零数的舍入值生成多个状态标志。在不计算有限非零数的舍入值的情况下，基于有限非零数生成多个状态标志。多个状态标志包括溢出标志和下溢标志。基于多个状态标志，FPU确定是否应针对有限非零数计算舍入值，以及是否断言溢出标志。在确定对于基于多个状态标志的有限非零数量计算舍入值并且断言溢出标志时，FPU基于溢出舍入来计算有限非零数的舍入值。在确定基于多个状态标志对于有限非零数进行舍入值计算并且不断言溢出标志时，FPU基于混合减少的精度舍入来计算有限非零数的舍入值。

89. 发明授权

US08972473B2 Efficient and reliable computation of results for mathematical functions 有权
标题翻译：高效可靠地计算数学函数的结果
公开(公告)号：US08972473B2
公开(公告)日：2015-03-03
申请号：US13479040
申请日：2012-05-23
申请人： John Robert Ehrman
发明人： John Robert Ehrman
IPC分类号： G06F7/499 , G06F17/17
CPC分类号： G06F17/17 , G06F7/49905
摘要： For efficient computation of results for mathematical functions, a method receives a mathematical function call. The call includes a plurality of arguments for which a range of computable results for the mathematical function of the function call varies with respect to the values for the arguments. The method determines whether executing the mathematical function using the plurality of arguments will produce a result within the range of computable results. The method further aborts the mathematical function call prior to initiating execution of the mathematical function in response to determining that the values for the plurality of arguments produce a result outside the range of computable results.
摘要翻译：为了有效计算数学函数的结果，一种方法接收一个数学函数调用。该调用包括多个参数，对于该参数，函数调用的数学函数的可计算结果的范围相对于参数的值而变化。该方法确定是否使用多个参数执行数学函数将在可计算结果的范围内产生结果。响应于确定多个参数的值在可计算结果的范围之外产生结果，该方法进一步中止数学函数调用之前启动数学函数的执行。

90. 发明授权

US08964919B2 System and method for determining a time for safely sampling a signal of a clock domain 有权
标题翻译：用于确定用于安全采样时钟域的信号的时间的系统和方法
公开(公告)号：US08964919B2
公开(公告)日：2015-02-24
申请号：US13674864
申请日：2012-11-12
申请人： NVIDIA Corporation
发明人： Stephen G. Tell
IPC分类号： H04L7/00 , G06F5/10 , G06F7/499
CPC分类号： H04L7/0012 , G06F5/10 , G06F7/49989 , G06F2205/106 , H04L7/005
摘要： A system and method are provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a phase estimate of a first clock domain is calculated based on a relative frequency estimate between a second clock domain and the first clock domain and, based on the phase estimate, a first time during which a signal from the first clock domain is unchanging such that the signal is capable of being safely sampled by the second clock domain is determined to generate a first sampled signal in the second clock domain. Additionally, an updated phase estimate is calculated, and, based on the updated phase estimate, a second time during which the signal from the first clock domain is changing such that the signal is not capable of being safely sampled by the second clock domain is determined. During the second time the first sampled signal in the second clock domain is maintained.
摘要翻译：提供了一种用于确定对时钟域的信号进行安全采样的时间的系统和方法。在一个实施例中，基于第二时钟域和第一时钟域之间的相对频率估计，并且基于相位估计，计算来自第一时钟域的信号的第一时间，第一时钟域的相位估计是不变的，使得能够被第二时钟域安全采样的信号被确定为在第二时钟域中产生第一采样信号。另外，计算更新的相位估计，并且基于更新的相位估计，确定来自第一时钟域的信号改变的第二时间，使得信号不能被第二时钟域安全地采样。在第二时间期间，维持第二时钟域中的第一采样信号。

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