专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10073676B2 Reduced floating-point precision arithmetic circuitry 有权
公开(公告)号：US10073676B2
公开(公告)日：2018-09-11
申请号：US15272231
申请日：2016-09-21
申请人： Altera Corporation
发明人： Martin Langhammer
IPC分类号： G06F7/487 , G06F17/16
CPC分类号： G06F7/485 , G06F7/4876 , G06F7/49957 , G06F7/5443 , G06F9/30014 , G06F17/16 , G06F2207/382 , G06F2207/483
摘要： The present embodiments relate to performing reduced-precision floating-point arithmetic operations using specialized processing blocks with higher-precision floating-point arithmetic circuitry. A specialized processing block may receive four floating-point numbers that represent two single-precision floating-point numbers, each separated into an LSB portion and an MSB portion, or four half-precision floating-point numbers. A first partial product generator may generate a first partial product of first and second input signals, while a second partial product generator may generate a second partial product of third and fourth input signals. A compressor circuit may generate carry and sum vector signals based on the first and second partial products; and circuitry may anticipate rounding and normalization operations by generating in parallel based on the carry and sum vector signals at least two results when performing the single-precision floating-point operation and at least four results when performing the two half-precision floating-point operations.

2. 发明授权

US10061561B2 Floating point addition with early shifting 有权
公开(公告)号：US10061561B2
公开(公告)日：2018-08-28
申请号：US15258051
申请日：2016-09-07
申请人： ARM Limited
发明人： David Raymond Lutz
IPC分类号： G06F7/485 , G06F5/01
CPC分类号： G06F7/485 , G06F5/01 , G06F2205/00 , G06F2207/483
摘要： A floating point adder includes leading zero anticipation circuitry to determine a number of leading zeros within a result significand value of a sum of a first floating point operand and a second floating point operand. This number of leading zeros is used to generate a mask which in turn selects input bits from a non-normalized significand produced by adding the first significand value and the second significand value. The non-normalized significand is then normalized at the same time as the output rounding bits used to round the normalized significand value are generated by rounding bit generation circuitry.

3. 发明授权

US09665347B2 Apparatus and method for performing conversion operation 有权
公开(公告)号：US09665347B2
公开(公告)日：2017-05-30
申请号：US14582812
申请日：2014-12-24
申请人： ARM Limited
发明人： David Raymond Lutz , Neil Burgess , Christopher Neal Hinds
IPC分类号： G06F5/00 , G06F7/483 , G06F7/499 , G06F9/30 , G06F17/16 , H03M7/12 , H03M7/24 , G06F11/34 , G06F11/36 , G06F5/01 , G06F7/38 , G06F7/48 , G06F7/507 , G06F9/38 , G06F7/506
CPC分类号： G06F7/483 , G06F5/012 , G06F7/38 , G06F7/48 , G06F7/4991 , G06F7/49915 , G06F7/49921 , G06F7/49942 , G06F7/506 , G06F7/507 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30036 , G06F9/30112 , G06F9/3016 , G06F9/30185 , G06F9/30192 , G06F9/3885 , G06F11/3404 , G06F11/3476 , G06F11/348 , G06F11/3636 , G06F11/3644 , G06F11/3648 , G06F17/16 , G06F2201/865 , G06F2207/483 , H03M7/12 , H03M7/24
摘要： An apparatus comprises processing circuitry to perform a conversion operation to convert a vector comprising a plurality of data elements representing respective bit significance portions of a binary value to a scalar value comprising an alternative representation of said binary value.

4. 发明申请

US20170017466A1 ARITHMETIC PROCESSING DEVICE AND METHOD OF CONTROLLING ARITHMETIC PROCESSING DEVICE 审中-公开
标题翻译：算术处理装置和控制算术处理装置的方法
公开(公告)号：US20170017466A1
公开(公告)日：2017-01-19
申请号：US15204304
申请日：2016-07-07
申请人： FUJITSU LIMITED
发明人： Mikio Hondo
IPC分类号： G06F7/483
CPC分类号： G06F7/4833 , G06F7/556 , G06F2207/483
摘要： An arithmetic processing device includes: a first memory configured to store values of a first coefficient of a logarithmic function, where the logarithmic function is decomposed into a series operation term and the coefficient term, depending on respective values of a first bit group included in operand data of a first instruction to calculate the value of the first coefficient; a second memory configured to store values of a second coefficient included in the series operation term depending on the respective values of the first bit group included in operand data of a second instruction to calculate the value of the second coefficient; and a selector configured to select the value of the first coefficient read from the first memory based on the execution of the first instruction and select the value of the second coefficient read from the second memory based on the execution of the second instruction.
摘要翻译：算术处理装置包括：第一存储器，被配置为存储对数函数的第一系数的值，其中对数函数被分解为串联运算项和系数项，这取决于包括在操作数中的第一位组的相应值用于计算第一系数的值的第一指令的数据; 第二存储器，被配置为根据包括在第二指令的操作数数据中的第一位组的各个值来存储包括在串联运算项中的第二系数的值，以计算第二系数的值; 以及选择器，被配置为基于第一指令的执行来选择从第一存储器读取的第一系数的值，并且基于第二指令的执行来选择从第二存储器读取的第二系数的值。

5. 发明申请

US20160126974A1 APPARATUS AND METHOD FOR PERFORMING CONVERSION OPERATION 有权
标题翻译：用于执行转换操作的装置和方法
公开(公告)号：US20160126974A1
公开(公告)日：2016-05-05
申请号：US14582812
申请日：2014-12-24
申请人： ARM Limited
发明人： David Raymond LUTZ , Neil BURGESS , Christopher Neal HINDS
IPC分类号： H03M7/12 , H03M7/24
CPC分类号： G06F7/483 , G06F5/012 , G06F7/38 , G06F7/48 , G06F7/4991 , G06F7/49915 , G06F7/49921 , G06F7/49942 , G06F7/506 , G06F7/507 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30036 , G06F9/30112 , G06F9/3016 , G06F9/30185 , G06F9/30192 , G06F9/3885 , G06F11/3404 , G06F11/3476 , G06F11/348 , G06F11/3636 , G06F11/3644 , G06F11/3648 , G06F17/16 , G06F2201/865 , G06F2207/483 , H03M7/12 , H03M7/24
摘要： An apparatus comprises processing circuitry to perform a conversion operation to convert a vector comprising a plurality of data elements representing respective bit significance portions of a binary value to a scalar value comprising an alternative representation of said binary value.
摘要翻译：一种装置包括处理电路，以执行转换操作，以将包含表示二进制值的相应比特有效部分的多个数据元素的矢量转换为包括所述二进制值的替代表示的标量值。

6. 发明申请

US20160124711A1 SIGNIFICANCE ALIGNMENT 有权
标题翻译：意义对齐
公开(公告)号：US20160124711A1
公开(公告)日：2016-05-05
申请号：US14582974
申请日：2014-12-24
申请人： ARM Limited
发明人： David Raymond LUTZ , Neil BURGESS , Christopher Neal HINDS
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F5/012 , G06F7/38 , G06F7/48 , G06F7/4991 , G06F7/49915 , G06F7/49921 , G06F7/49942 , G06F7/506 , G06F7/507 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30036 , G06F9/30112 , G06F9/3016 , G06F9/30185 , G06F9/30192 , G06F9/3885 , G06F11/3404 , G06F11/3476 , G06F11/348 , G06F11/3636 , G06F11/3644 , G06F11/3648 , G06F17/16 , G06F2201/865 , G06F2207/483 , H03M7/12 , H03M7/24
摘要： A data processing system uses alignment circuitry to align input operands in accordance with a programmable significance parameter to form aligned input operands. The aligned input operands are supplied to arithmetic circuitry, such as an integer adder or an integer multiplier, where a result value is formed. The result value is stored in an output operand storage element, such as a result register. The programmable significance parameter is independent of the result value.
摘要翻译：数据处理系统使用对准电路根据可编程有效参数来对准输入操作数，以形成对准的输入操作数。对齐的输入操作数被提供给算术电路，例如形成结果值的整数加法器或整数乘法器。结果值存储在输出操作数存储元素中，如结果寄存器。可编程有效值参数与结果值无关。

7. 发明申请

US20160124710A1 DATA PROCESSING APPARATUS AND METHOD USING PROGRAMMABLE SIGNIFICANCE DATA 有权
标题翻译：数据处理设备和使用可编程意义数据的方法
公开(公告)号：US20160124710A1
公开(公告)日：2016-05-05
申请号：US14582836
申请日：2014-12-24
申请人： ARM Limited
发明人： David Raymond LUTZ , Neil BURGESS , Christopher Neal HINDS
IPC分类号： G06F7/483
CPC分类号： G06F7/483 , G06F5/012 , G06F7/38 , G06F7/48 , G06F7/4991 , G06F7/49915 , G06F7/49921 , G06F7/49942 , G06F7/506 , G06F7/507 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30036 , G06F9/30112 , G06F9/3016 , G06F9/30185 , G06F9/30192 , G06F9/3885 , G06F11/3404 , G06F11/3476 , G06F11/348 , G06F11/3636 , G06F11/3644 , G06F11/3648 , G06F17/16 , G06F2201/865 , G06F2207/483 , H03M7/12 , H03M7/24
摘要： An apparatus may have processing circuitry to perform one or more arithmetic operations for generating a result value based on at least one operand. For at least one arithmetic operation, the processing circuitry is responsive to programmable significance data indicative of a target significance for the result value, to generate the result value having the target significance. For example, this allows programmers to set a significance boundary for the arithmetic operation so that it is not necessary for the processing circuitry to calculate bit values having a significance outside the specified boundary, enabling a performance improvement.
摘要翻译：装置可以具有处理电路，用于执行一个或多个算术运算，用于基于至少一个操作数生成结果值。对于至少一个算术运算，处理电路响应于指示结果值的目标有效性的可编程有效数据，以产生具有目标有效性的结果值。例如，这允许程序员为算术运算设置一个有效边界，使得处理电路不需要计算具有超出指定边界的重要性的位值，从而能够提高性能。

8. 发明申请

US20150067010A1 FLOATING-POINT ADDER CIRCUITRY 有权
标题翻译：浮点补偿电路
公开(公告)号：US20150067010A1
公开(公告)日：2015-03-05
申请号：US14019196
申请日：2013-09-05
申请人： Altera Corporation
发明人： Tomasz Czajkowski
IPC分类号： G06F17/10
CPC分类号： G06F7/485 , G06F5/012 , G06F7/49915 , G06F17/10 , G06F2207/483
摘要： An integrated circuit is provided that performs floating-point addition or subtraction operations involving at least three floating-point numbers. The floating-point numbers are pre-processed by dynamically extending the number of mantissa bits, determining the floating-point number with the biggest exponent, and shifting the mantissa of the other floating-point numbers to the right. Each extended mantissa has at least twice the number of bits of the mantissa entering the floating-point operation. The exact bit extension is dependent on the number of floating-point numbers to be added. The mantissas of all floating-point numbers with an exponent smaller than the biggest exponent are shifted to the right. The number of right shift bits is dependent on the difference between the biggest exponent and the respective floating-point exponent.
摘要翻译：提供一种集成电路，其执行涉及至少三个浮点数的浮点加法或减法运算。通过动态扩展尾数位数，以最大指数确定浮点数，将其他浮点数的尾数向右移动，对浮点数进行预处理。每个扩展尾数具有进入浮点运算的尾数的位数的至少两倍。精确的位扩展取决于要添加的浮点数的数量。指数小于最大指数的所有浮点数的尾数向右移动。右移位的数量取决于最大指数和相应浮点指数之间的差异。

9. 发明申请

US20140379772A1 PROCESSOR AND CONTROL METHOD OF PROCESSOR 有权
标题翻译：处理器的处理器和控制方法
公开(公告)号：US20140379772A1
公开(公告)日：2014-12-25
申请号：US14479392
申请日：2014-09-08
申请人： FUJITSU LIMITED
发明人： Mikio Hondo
IPC分类号： G06F7/556 , G06F7/483
CPC分类号： G06F7/556 , G06F7/483 , G06F2207/483 , G06F2207/556
摘要： A processor includes: an exponent generating unit that generates an exponent part of a coefficient represented by a floating point number format based on a first part of received input data, the coefficient being obtained when an exponential function is decomposed into a series operation and the coefficient for the series operation; a storage unit that stores a mantissa part of the coefficient; a constant generating unit that reads constant data corresponding to a second part of the input data from the storage unit; and a selecting unit that selects and outputs the constant data from the constant generating unit when an instruction to be executed is a coefficient calculation instruction for calculation of the coefficient of the exponential function.
摘要翻译：处理器包括：指数生成单元，其基于接收到的输入数据的第一部分生成由浮点数格式表示的系数的指数部分，将指数函数分解为串联运算时获得的系数，并且系数用于系列操作; 存储单元，其存储所述系数的尾数部分; 常数生成单元，其从所述存储单元读取与所述输入数据的第二部分相对应的恒定数据; 以及选择单元，当要执行的指令是用于计算指数函数的系数的系数计算指令时，从常数生成单元选择并输出常数数据。

10. 发明授权

US08849881B2 Modal interval processor 有权
标题翻译：模态间隔处理器
公开(公告)号：US08849881B2
公开(公告)日：2014-09-30
申请号：US13114672
申请日：2011-05-24
申请人： Nathan T. Hayes
发明人： Nathan T. Hayes
IPC分类号： G06F7/00 , G06F7/499
CPC分类号： G06F7/485 , G06F7/49989 , G06F2207/483
摘要： A logic circuit computes various modal interval arithmetic values using a plurality of arithmetic function units. A multiplexer gates the desired arithmetic values to a storage register.
摘要翻译：逻辑电路使用多个算术功能单元来计算各种模态间隔算术值。多路复用器将期望的算术值门控到存储寄存器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式