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81. 发明申请

US20170041016A1 SUCCESSIVE COMPARISON A/D CONVERSION CIRCUIT 有权
标题翻译：成功的比较A / D转换电路
公开(公告)号：US20170041016A1
公开(公告)日：2017-02-09
申请号：US15299660
申请日：2016-10-21
申请人： OLYMPUS CORPORATION
发明人： Yasunari Harada
IPC分类号： H03M1/38 , H03M1/12 , G11C27/02
CPC分类号： H03M1/38 , G11C27/02 , G11C27/024 , H03M1/0682 , H03M1/1245 , H03M1/46
摘要： A successive comparison A/D conversion circuit includes: an comparison circuit including a differential amplification circuit which includes a pair of differential input terminals, amplifies a pair of first differential signals input into the pair of differential input terminals, and outputs a pair of second differential signals, and a latch circuit which compares voltages of the second differential signals output from the differential amplification circuit, retains an comparison result, and outputs the retained comparison result; a digital circuit which generates a digital signal corresponding to the first differential signal, based on the comparison result; an arithmetic circuit which generates a reference signal based on the digital signal, generates the first differential signal by subtracting the reference signal from a third differential signal or adding the reference signal to the third differential signal, and outputs the generated first differential signal to the pair of differential input terminals; and a control circuit.
摘要翻译：连续比较A / D转换电路包括：包括差分放大电路的比较电路，差分放大电路包括一对差分输入端，放大输入到该对差分输入端的一对第一差分信号，并输出一对第二差分信号，以及比较从差分放大电路输出的第二差分信号的电压的锁存电路，保持比较结果，并输出保留的比较结果; 基于比较结果生成对应于第一差分信号的数字信号的数字电路; 产生基于数字信号的参考信号的算术电路，通过从第三差分信号中减去参考信号或将参考信号与第三差分信号相加来产生第一差分信号，并将产生的第一差分信号输出到对的差分输入端子; 和控制电路。

82. 发明申请

US20160336930A1 AMPLIFYING CIRCUIT, AD CONVERTER, INTEGRATED CIRCUIT, AND WIRELESS COMMUNICATION APPARATUS 有权
标题翻译：放大电路，AD转换器，集成电路和无线通信设备
公开(公告)号：US20160336930A1
公开(公告)日：2016-11-17
申请号：US15092977
申请日：2016-04-07
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Junya MATSUNO , Masanori FURUTA , Tetsuro ITAKURA
IPC分类号： H03K5/02 , H03M1/12 , H04B1/40 , G11C27/02
CPC分类号： H03K5/02 , G11C27/026 , H03F3/45183 , H03F3/45475 , H03F2203/45138 , H03F2203/45551 , H03F2203/45634
摘要： An amplifying circuit according to an embodiment includes an input terminal, an output terminal, first and second operational amplifiers, first and second input impedance elements, first to third feedback impedance elements, and an adder. The first (second) operational amplifier includes an inversion input terminal connected to a first (third) node and an output terminal connected to a second (fourth) node. The first (second) input impedance element has one end connected to the input terminal and the other end connected to the first (third) node. The first (second) feedback impedance element has one end connected to the first (third) node and the other end connected to the second (fourth) node. The third feedback impedance element has one end connected to the first node and the other end connected to the fourth node. The adder adds output voltages of the first and second operational amplifiers.
摘要翻译：根据实施例的放大电路包括输入端子，输出端子，第一和第二运算放大器，第一和第二输入阻抗元件，第一至第三反馈阻抗元件以及加法器。第一（第二）运算放大器包括连接到第一（第三）节点的反相输入端子和连接到第二（第四）节点的输出端子。第一（第二）输入阻抗元件的一端连接到输入端，另一端连接到第一（第三）节点。第一（第二）反馈阻抗元件的一端连接到第一（第三）节点，另一端连接到第二（第四）节点。第三反馈阻抗元件的一端连接到第一节点，另一端连接到第四节点。该加法器加上第一和第二运算放大器的输出电压。

83. 发明申请

US20160329881A1 AMPLIFYING CIRCUIT 审中-公开
标题翻译：放大电路
公开(公告)号：US20160329881A1
公开(公告)日：2016-11-10
申请号：US15061562
申请日：2016-03-04
申请人： KABUSHIKI KAISHA TOSHIBA , Tokyo University of Science Foundation
发明人： Junya MATSUNO , Masanori FURUTA , Tetsuro ITAKURA , Akira HYOGO , Tatsuji MATSUURA , Takuya HARA
IPC分类号： H03K3/0233 , H03M1/12 , H04B1/04 , G11C27/02
CPC分类号： H03K3/0233 , G11C27/026 , H03F1/02 , H03F3/24 , H03F3/45475 , H03F2203/45512 , H03F2203/45551 , H03F2203/45634 , H04B1/0458 , H04B2001/045
摘要： An amplifying circuit according to an embodiment includes a sample and hold circuit, an operational amplifier, a feedback capacitance, and a level shift circuit. The sample and hold circuit includes a sampling capacitance to sample an analog input signal in a sampling phase. The operational amplifier amplifies and outputs the analog input signal held by the sampling capacitance in the amplifying phase. The feedback capacitance is connected between the input terminal of the operational amplifier and the analog output terminal. The level shift circuit includes a level shift capacitance to sample the analog input signal in the sampling phase. A plurality of level shift capacitances is provided and connected in cascade between the output terminal of the operational amplifier and the analog output terminal.
摘要翻译：根据实施例的放大电路包括采样和保持电路，运算放大器，反馈电容和电平移位电路。采样和保持电路包括采样电容，以在采样阶段对模拟输入信号进行采样。运算放大器在放大阶段放大并输出由采样电容保持的模拟输入信号。反馈电容连接在运算放大器的输入端和模拟输出端之间。电平移位电路包括在采样阶段对模拟输入信号进行采样的电平移位电容。提供多个电平移位电容并级联连接在运算放大器的输出端和模拟输出端之间。

84. 发明授权

US09460808B2 Method and device for controlling a sample and hold circuit 有权
标题翻译：用于控制采样和保持电路的方法和装置
公开(公告)号：US09460808B2
公开(公告)日：2016-10-04
申请号：US14549291
申请日：2014-11-20
申请人： STMicroelectronics (Rousset) SAS
发明人： Bruno Gailhard , Yohan Joly
IPC分类号： H03K5/00 , G11C27/02 , G11C29/50 , G11C29/02 , H03K3/0231
CPC分类号： G11C27/024 , G11C29/023 , G11C29/028 , G11C29/50016 , H03K3/0231
摘要： A method is provided for controlling a sample and hold circuit that includes a switching module coupled to a storage capacitor. A circuit external to the sample and hold circuit of generates at least one main current representative of at least one leakage current of the switching module in its off state. The at least one main current is delivered to at least one auxiliary capacitor. An initial pulse signal is generated from the charging and discharging of the at least one auxiliary capacitor. The sampling phase of the sample and hold circuit is triggered at the rate of the pulses of a pulse signal derived from the initial pulse signal.
摘要翻译：提供了一种用于控制采样和保持电路的方法，该采样和保持电路包括耦合到存储电容器的开关模块。采样和保持电路外部的电路产生代表切换模块处于其关闭状态的至少一个泄漏电流的至少一个主电流。至少一个主电流被传送到至少一个辅助电容器。从至少一个辅助电容器的充电和放电产生初始脉冲信号。采样和保持电路的采样相位以从初始脉冲信号得到的脉冲信号脉冲的速率被触发。

85. 发明授权

US09444479B2 Analogue-to-digital conversion circuitry 有权
标题翻译：模数转换电路
公开(公告)号：US09444479B2
公开(公告)日：2016-09-13
申请号：US14553598
申请日：2014-11-25
申请人： SOCIONEXT INC.
发明人： Ian Juso Dedic , Gavin Lambertus Allen
IPC分类号： H03M1/12 , H03M1/06 , G11C27/02 , H01H9/54 , H03K17/00 , H03M1/10 , H03L7/00 , H03M1/08 , H03L7/091 , H03M1/00
CPC分类号： H03M1/0614 , G11C27/02 , H01H9/54 , H03K17/00 , H03L7/00 , H03L7/091 , H03M1/002 , H03M1/0881 , H03M1/1009 , H03M1/12 , H03M1/121 , H03M1/1215 , H03M1/1245 , H03M1/126 , Y10T307/76
摘要： There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.
摘要翻译：公开了被配置为由基本正弦时钟信号驱动的电流模式时间交织采样电路。这种电路可以并入ADC电路中，例如作为IC芯片上的集成电路。所公开的电路能够自行校准而不脱机。

86. 发明授权

US09437602B2 Temperature compensation method for high-density floating-gate memory 有权
标题翻译：高密度浮栅存储器温度补偿方法
公开(公告)号：US09437602B2
公开(公告)日：2016-09-06
申请号：US14362256
申请日：2012-11-27
申请人： Board of Trustees of Michigan State University
发明人： Shantanu Chakrabartty , Ming Gu , Chenling Huang
IPC分类号： H01L29/788 , H01L27/115 , G11C7/04 , G11C16/04 , G11C27/00 , G11C27/02 , H01L27/06 , H01L49/02
CPC分类号： H01L27/11526 , G11C7/04 , G11C16/0408 , G11C16/0441 , G11C27/005 , G11C27/028 , H01L27/0629 , H01L28/40
摘要： A temperature compensation technique is provided for a non-volatile memory arrangement. The memory arrangement includes: a memory circuit (12) having a floating gate transistor (P3) operating in weak-inversion mode and a varactor (Cv) with a terminal electrically coupled to a gate node of the floating gate transistor; a first current reference circuit (14) having a floating gate transistor (PI); a second current reference circuit (16) having a floating gate transistor (P2); and a control module (18) configured to selectively receive a reference current (I1, I2) from a drain of the floating gate transistor in each of the first and second current reference circuits. The control module operates to determine a ratio between the reference currents received from the first and second current reference circuits, generate a tuning voltage (Vx) in accordance with the ratio between the reference currents and apply the tuning voltage to the varactor in the memory circuit.
摘要翻译：为非易失性存储器装置提供温度补偿技术。存储器装置包括：具有以弱反相模式工作的浮栅晶体管（P3）的存储器电路（12）和与浮栅晶体管的栅极节点电耦合的端子的变容二极管（Cv）; 具有浮置栅极晶体管（PI）的第一电流参考电路（14）; 具有浮置栅极晶体管（P2）的第二电流参考电路（16）; 以及控制模块（18），被配置为从所述第一和第二电流参考电路中的每一个中的所述浮动栅极晶体管的漏极选择性地接收参考电流（I1，I2）。控制模块操作以确定从第一和第二电流参考电路接收的参考电流之间的比率，根据参考电流之间的比率产生调谐电压（Vx），并将调谐电压施加到存储器电路中的变容二极管。

87. 发明申请

US20160226506A1 SWITCH CIRCUIT, ANALOG-TO-DIGITAL CONVERTER, AND INTEGRATED CIRCUIT 有权
标题翻译：开关电路，模数转换器和集成电路
公开(公告)号：US20160226506A1
公开(公告)日：2016-08-04
申请号：US14757547
申请日：2015-12-24
申请人： SOCIONEXT INC.
发明人： Seiji OKAMOTO
IPC分类号： H03M1/12 , G11C27/02 , H03K17/06
CPC分类号： G11C27/02 , G11C27/024 , H03K17/063 , H03K17/08122 , H03K2217/0054 , H03M1/1245
摘要： A switch circuit includes: a sampling transistor including a source connected to an input node and a drain connected to an output node; a control circuit which is connected to a gate of the sampling transistor and configured to control turning on or off of the sampling transistor; a voltage holding circuit which is provided between the gate and the source of the sampling transistor and configured to maintain a voltage between the gate and the source of the sampling transistor constant when the sampling transistor is turned on; and a protection circuit which is provided in parallel to the control circuit and configured to lower a voltage that is applied to the gate of the sampling transistor when the sampling transistor makes a transition from on to off.
摘要翻译：开关电路包括：采样晶体管，包括连接到输入节点的源极和连接到输出节点的漏极; 控制电路，其连接到采样晶体管的栅极并被配置为控制采样晶体管的导通或截止; 电压保持电路，其设置在所述采样晶体管的栅极和源极之间，并且被配置为当所述采样晶体管导通时保持所述采样晶体管的栅极和源极之间的电压恒定; 以及保护电路，其与所述控制电路并联设置并且被配置为当所述采样晶体管从接通切换到断开时降低施加到所述采样晶体管的栅极的电压。

88. 发明授权

US09378844B2 Semiconductor device including transistor whose gate is electrically connected to capacitor 有权
标题翻译：半导体器件包括其栅极电连接到电容器的晶体管
公开(公告)号：US09378844B2
公开(公告)日：2016-06-28
申请号：US14445311
申请日：2014-07-29
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Kei Takahashi
IPC分类号： G11C27/02 , H03K17/16 , H01L27/06
CPC分类号： H03F1/0233 , G11C27/024 , H01L27/0688 , H01L27/1225 , H01L27/124 , H01L27/1251 , H01L27/1255 , H01L29/78651 , H01L29/7869 , H03F3/45273 , H03F2200/555 , H03F2203/45288 , H03K4/06
摘要： Electric charge is stored, in accordance with a bias voltage, in a gate of a transistor performing switching operation between an input terminal and an output terminal, and the gate is brought into an electrically floating state at the time of completing the storage of electric charge in the gate. One electrode of a capacitor is connected to the gate in an electrically floating state, and the potential of the other electrode of the capacitor is increased, so that the voltage of the gate is increased using capacitive coupling. The potential of the gate of the transistor is increased, and the bias voltage is sampled without being decreased. Each of the transistor performing switching operation and a transistor connected to the gate of the transistor is a transistor with an extremely low off-state current.
摘要翻译：根据偏置电压在输入端子和输出端子之间进行开关动作的晶体管的栅极中存储电荷，并且在完成电荷存储时使栅极进入电浮置状态在门口电容器的一个电极以电浮动状态连接到栅极，并且电容器的另一个电极的电位增加，使得使用电容耦合来提高栅极的电压。晶体管的栅极的电位增加，并且偏置电压被采样而不降低。执行开关操作的晶体管和连接到晶体管的栅极的晶体管是具有非常低的截止电流的晶体管。

89. 发明授权

US09355742B2 Sampling device with time-interleaved optical clocking 有权
标题翻译：具有时间交错光时钟的采样设备
公开(公告)号：US09355742B2
公开(公告)日：2016-05-31
申请号：US14398123
申请日：2013-04-23
申请人： Rohde & Schwarz GmbH & Co. KG
发明人： Oliver Landolt
IPC分类号： G11C27/02 , H03K5/00 , G02F7/00 , G02B6/125 , H03K3/42 , H03M1/12 , G11C13/04 , G02B6/28 , G02B6/12
CPC分类号： G11C27/02 , G02B6/125 , G02B6/2861 , G02B2006/12147 , G02B2006/1215 , G02B2006/12154 , G02F7/00 , G11C13/04 , G11C27/024 , H03K3/42 , H03M1/1215 , H03M1/1245
摘要： A sampling device comprising a first input port and a second input port, wherein an input-signal is fed to the first input port and wherein an optical clock signal is fed to the second input port. The sampling device comprises a plurality of track and hold units, wherein each of the plurality of track and hold units is connected to the first input port. The plurality of the track and hold units is further connected to the second input port through an optical waveguide in such a manner that the plurality of tack and hold units operate in a time-interleaved mode.
摘要翻译：一种采样装置，包括第一输入端口和第二输入端口，其中输入信号被馈送到第一输入端口，并且其中光时钟信号被馈送到第二输入端口。采样装置包括多个跟踪和保持单元，其中多个跟踪和保持单元中的每一个连接到第一输入端口。多个轨道和保持单元通过光波导进一步连接到第二输入端口，使得多个定位和保持单元以时间交织模式工作。

90. 发明申请

US20160148706A1 COMPACT SAMPLE-AND-HOLD DEVICE 有权
标题翻译：紧凑型样品保持装置
公开(公告)号：US20160148706A1
公开(公告)日：2016-05-26
申请号：US14889813
申请日：2014-05-14
申请人： THALES
发明人： Patrick GREMILLET
IPC分类号： G11C27/02
CPC分类号： G11C27/024
摘要： The sample-and-hold device comprises a holding capacitor and operates according to a track phase during which the voltage on the terminals of the capacitor tracks the input signal and according to a hold phase during which the capacitor is isolated from the input signal, it comprises: a differential pair comprising a first transistor Q1 and a second transistor Q2 connected as common emitters, the collector of the transistor Q2 being connected to the holding capacitor, the input signal being applied to the base of the transistor Q1; a third transistor Q3, of which the base is connected to the collector of the transistor Q2 and the emitter is connected to the base of the transistor Q2, the signal present on the emitter of the transistor Q3 forming the output signal of the sample-and-hold device; a current source I connected to the collector of the transistor Q2; during the track phase, the differential pair Q1, Q2 being supplied by a current 2I, the transistor Q2 being charged by the current source and by the holding capacitor, during the hold phase, the current 2I supplying the differential pair Q1, Q2 being disconnected and the holding capacitor being charged by two opposite currents having the same value, equal to the current I of the source.
摘要翻译：采样和保持装置包括保持电容器，并根据磁道相位进行操作，在该阶段期间，电容器端子上的电压跟踪输入信号，并且根据电容器与输入信号隔离的保持相位，包括：包括作为公共发射极连接的第一晶体管Q1和第二晶体管Q2的差分对，晶体管Q2的集电极连接到保持电容器，输入信号施加到晶体管Q1的基极; 第三晶体管Q3，其基极连接到晶体管Q2的集电极，发射极连接到晶体管Q2的基极，存在于晶体管Q3的发射极上的信号形成样品的输出信号，以及固定装置连接到晶体管Q2的集电极的电流源I; 在跟踪期间，差动对Q1，Q2由电流2I提供，晶体管Q2由电流源和保持电容充电，在保持阶段期间，提供差动对Q1，Q2的电流2I断开并且保持电容器由具有相同值的两个相反电流充电，等于源极的电流I.

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