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81. 发明授权

US6038183A Semiconductor memory device having burn-in mode operation stably accelerated 失效
标题翻译：具有老化模式操作的半导体存储器件稳定地加速
公开(公告)号：US6038183A
公开(公告)日：2000-03-14
申请号：US288019
申请日：1999-04-08
申请人： Masaki Tsukude
发明人： Masaki Tsukude
IPC分类号： G01R31/28 , G01R31/30 , G11C5/00 , G11C11/401 , G11C11/407 , G11C29/06 , G11C7/00
CPC分类号： G11C29/06 , G11C29/12005 , G11C29/26 , G11C29/34 , G11C29/50 , G11C5/00 , G11C11/401 , G11C2029/1202 , G11C2029/2602
摘要： Current is reduced in driving a word line in stress acceleration testing such as burn-in, and the time required for the stress acceleration testing is reduced. For an address signal applied from an address buffer, a predetermined internal address signal bit is degenerated and a remaining address signal bit is rendered valid in response to an activation of a stress acceleration mode designation signal to simultaneously drive a desired number of word lines of all word lines to selected state. Any number of word lines can be simultaneously selected and hence current flowing in driving word lines can be reduced in the stress acceleration mode. In the stress acceleration mode of operation, bit line voltage and cell plate voltage are changed, and a current required for driving a plurality of word lines into a selected state is limited.
摘要翻译：压力加速度测试（如老化）中的字线驱动电流减少，应力加速测试所需的时间减少。对于从地址缓冲器施加的地址信号，预定的内部地址信号位退化，并且剩余地址信号位响应于应力加速模式指定信号的激活而变为有效，以同时驱动所需数量的所有字线字线到选定状态。可以同时选择任何数量的字线，因此在应力加速模式中可以减少在驱动字线中流动的电流。在应力加速操作模式中，位线电压和单元板电压发生变化，并且将多条字线驱动到选定状态所需的电流受到限制。

82. 发明授权

US5999457A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US5999457A
公开(公告)日：1999-12-07
申请号：US183646
申请日：1998-10-30
申请人： Katsuhiko Sato
发明人： Katsuhiko Sato
IPC分类号： G01R31/28 , G11C29/02 , G11C29/06 , G11C29/18 , H01L21/66 , H01L27/10 , G11C16/04 , G11C8/00
CPC分类号： G11C29/18
摘要： A semiconductor integrated circuit incorporating DRAM 2 and a logic circuit 3 includes a vector generating circuit 40 formed on the common substrate. Upon a burn-in process, the vector generating circuit 40 and a refresh counter and control circuit 23 are activated to generate addresses, commands and data required for activating DRAM 2. In this manner, DRAM 2 and the logic circuit 3 can be activated independently, simultaneously, and the time required for the burn-in process can be reduced.
摘要翻译：包含DRAM2和逻辑电路3的半导体集成电路包括形成在公共基板上的矢量生成电路40。在老化过程中，矢量生成电路40和刷新计数器和控制电路23被激活以产生激活DRAM2所需的地址，命令和数据。以这种方式，可以独立地激活DRAM2和逻辑电路3 同时，可以减少老化过程所需的时间。

83. 发明授权

US5995427A Semiconductor memory device having test mode 失效
标题翻译：具有测试模式的半导体存储器件
公开(公告)号：US5995427A
公开(公告)日：1999-11-30
申请号：US985219
申请日：1997-12-04
申请人： Yasuhiko Tsukikawa
发明人： Yasuhiko Tsukikawa
IPC分类号： G11C11/401 , G11C11/4094 , G11C29/06 , G11C29/34 , G11C29/50 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4094 , G11C29/50 , G11C11/401 , G11C29/34
摘要： In a DRAM, a bit-line potential inputting node of an equalizer provided for each odd-numbered pair of bit lines is provided separately from a bit-line potential inputting node of an equalizer provided for each even-numbered pair of bit lines. In burn-in testing, one node receives a high level and the other node receives a low level to simultaneously apply electric field stress between adjacent pairs of bit lines. This allows sufficient acceleration of initial failures in burn-in testing.
摘要翻译：在DRAM中，为每个奇数位位线提供的均衡器的位线电位输入节点与为每个偶数位位线提供的均衡器的位线电位输入节点分开提供。在老化测试中，一个节点接收高电平，另一个节点接收低电平，以在相邻的位线对之间同时施加电场应力。这样可以在老化测试中充分加速初始故障。

84. 发明授权

US5949731A Semiconductor memory device having burn-in mode operation stably accelerated 失效
公开(公告)号：US5949731A
公开(公告)日：1999-09-07
申请号：US941215
申请日：1997-09-30
申请人： Masaki Tsukude
发明人： Masaki Tsukude
IPC分类号： G01R31/28 , G01R31/30 , G11C5/00 , G11C11/401 , G11C11/407 , G11C29/06 , G11C8/00
CPC分类号： G11C29/06 , G11C29/12005 , G11C29/26 , G11C29/34 , G11C29/50 , G11C5/00 , G11C11/401 , G11C2029/1202 , G11C2029/2602
摘要： Current is reduced in driving a word line in stress acceleration testing such as burn-in, and the time required for the stress acceleration testing is reduced. For an address signal applied from an address buffer, a predetermined internal address signal bit is degenerated and a remaining address signal bit is rendered valid in response to an activation of a stress acceleration mode designation signal to simultaneously drive a desired number of word lines of all word lines to selected state. Any number of word lines can be simultaneously selected and hence current flowing in driving word lines can be reduced in the stress acceleration mode. In the stress acceleration mode of operation, bit line voltage and cell plate voltage are changed, and a current required for driving a plurality of word lines into a selected state is limited.

85. 发明授权

US5803938A Liquid vaporizing apparatus 失效
标题翻译：液体蒸发装置
公开(公告)号：US5803938A
公开(公告)日：1998-09-08
申请号：US856575
申请日：1997-05-15
申请人： Tooru Yamaguchi , Kouichirou Tsutahara , Takayuki Suenaga
发明人： Tooru Yamaguchi , Kouichirou Tsutahara , Takayuki Suenaga
IPC分类号： H01L21/205 , B01D1/00 , B01D1/14 , B01D1/26 , B01D3/34 , B01J7/02 , C23C16/448 , G06F1/26 , G11C7/00 , G11C11/407 , G11C29/00 , G11C29/06 , H01L21/31 , B01F3/04
CPC分类号： B01D1/0076 , B01D1/0082 , B01D1/14 , B01D1/26 , B01D3/343 , B01D3/346
摘要： A liquid vaporizing apparatus includes a container for holding a liquid at a constant temperature with a temperature adjustment unit and a gas that does not react with the liquid is bubbled through the liquid in the container to vaporize the liquid. The container for holding the liquid has an internal space above the liquid and a second temperature adjustment unit for controlling the temperature of the internal space separately from the temperature of the liquid in the container. Since the internal space is maintained at a constant temperature, higher than the temperature of the liquid, the quantity of the vaporized liquid produced is stable.
摘要翻译：液体蒸发装置包括用温度调节单元保持恒定温度的液体的容器，并且不与液体反应的气体鼓泡通过容器中的液体以蒸发液体。用于保持液体的容器具有在液体上方的内部空间和用于独立于容器中的液体的温度来控制内部空间的温度的第二温度调节单元。由于内部空间维持在比液体温度高的恒定温度下，所生成的气化液体的量是稳定的。

86. 发明授权

US5745415A Circuit for SRAM test mode isolated bitline modulation 失效
公开(公告)号：US5745415A
公开(公告)日：1998-04-28
申请号：US734064
申请日：1996-10-18
申请人： Kenneth W. Marr
发明人： Kenneth W. Marr
IPC分类号： G01R31/28 , G01R31/3185 , G11C7/00 , G11C11/413 , G11C29/06 , G11C29/14 , G11C29/46 , G11C29/50
CPC分类号： G11C29/46 , G11C29/50 , G11C11/41 , G11C2029/5004
摘要： A circuit and method provide isolated modulation of SRAM bitline voltage levels for improved voltage bump retention testing of the SRAM cells. A first FET is connected to Vcc, bitline load gates of the SRAM cell, and test mode operation control logic. A second FET is connected to the bitline load gates, the test mode logic, and an external pin of the SRAM device. During test mode operation, the first FET disables Vcc to the bitlines, and the second FET enables the internal bitline voltage levels to be modulated by a voltage supply received through the external pin of the device. Modulation of the bitline voltage levels is isolated from normal operating voltage levels of peripheral circuitry such as the wordlines. An alternate embodiment provides a CMOS transmission gate in place of the second FET.

87. 发明授权

US5706233A Semiconductor memory device allowing acceleration testing, and a semi-finished product for an integrated semiconductor device that allows acceleration testing 失效
公开(公告)号：US5706233A
公开(公告)日：1998-01-06
申请号：US601750
申请日：1996-02-15
申请人： Tsukasa Ooishi
发明人： Tsukasa Ooishi
IPC分类号： G11C11/413 , G11C7/00 , G11C11/401 , G11C11/404 , G11C11/407 , G11C29/00 , G11C29/06 , G11C29/34 , H01L21/8242 , H01L27/108
CPC分类号： G11C29/006 , G11C11/34 , G11C11/4087 , G11C29/12015 , G11C29/14 , G11C29/18 , G11C29/20 , G11C29/34 , G11C29/48 , G11C11/401 , G11C2029/1202 , G11C2029/1204 , G11C2029/1802 , G11C2029/2602
摘要： A DRAM includes a row predecoder responsive to an multi-selection signal for activating all predecode signals independent of a row address signal, and a row decoder unit responsive to the multi-selection signal for activating all decode signals independent of the row address signal. As a result, all word drivers are activated in an acceleration test independent of the row address signal, and all the word lines are driven simultaneously.

88. 发明授权

US5675546A On-chip automatic procedures for memory testing 失效
标题翻译：片上自动程序进行内存测试
公开(公告)号：US5675546A
公开(公告)日：1997-10-07
申请号：US659811
申请日：1996-06-07
申请人： Yu-Ying Jackson Leung
发明人： Yu-Ying Jackson Leung
IPC分类号： G01R31/28 , G01R31/30 , G11C29/02 , G11C29/06 , G11C29/16 , G11C29/50 , G11C7/00 , G11C29/00
CPC分类号： G11C29/021 , G11C29/02 , G11C29/16 , G11C29/50 , G06F2201/88 , G11C16/04 , G11C2029/5004
摘要： The on-chip endurance test (Autocycle) and the parametric characterization test (Auto VccMax/Min) of this invention save test time and hardware by performance automatically on the memory chip upon transmittal of a single command (CONTROL CODE) to the chip from the tester. The automated test procedures of this invention run faster because the on-chip tester requires fewer externally issued commands (CONTROL CODEs) and requires fewer external status checks. The procedures of this invention permit the external tester to have a smaller number of input/output pins (CONTROL), decreasing the cost of the external test hardware. Specifically, the endurance test (Autocycle), automatically cycles the memory chip through any combination of programming, erasing, and/or compaction operations until either a failure has been detected or the required number of the test cycles has been completed. The parametric characterization test (AutoVccMax/Min) determines automatically the maximum supply voltage and/or the minimum supply voltage for data operation of the memory chip. The endurance test (Autocycle) uses a microsequencer (MC) and an on-chip built-in-logic-block-observation (BILBO) register to check information in a control-read-only memory (CROM). Output data from the control-read-only memory is latched in a BILBO register enhanced for use as a counter for large count. During the endurance test (Autocycle), the microsequencer (MC), using enhanced counter, monitors the number of on-chip controlled endurance test cycles. During the parametric characterization test (AutoVccMax/Min), an on-chip digital-analog converter (DAC) causes stepped changes in the supply voltage (Vcc) furnished to both the data cells (10) and the reference cells (10) of the memory.
摘要翻译：本发明的片上耐久性测试（Autocycle）和参数化特性测试（Auto VccMax / Min）在将单个命令（控制代码）传送到芯片上时，可以在存储器芯片上自动保存测试时间和硬件测试仪本发明的自动测试程序运行速度更快，因为片上测试仪需要更少的外部发出的命令（控制代码），并且需要更少的外部状态检查。本发明的程序允许外部测试仪具有较少数量的输入/输出引脚（CONTROL），降低外部测试硬件的成本。具体来说，耐久性测试（Autocycle）通过编程，擦除和/或压缩操作的任何组合自动循环存储器芯片，直到检测到故障或已经完成所需的测试周期数。参数化特性测试（AutoVccMax / Min）自动确定存储器芯片的数据操作的最大电源电压和/或最小电源电压。耐力测试（Autocycle）使用微定序器（MC）和片上内置逻辑块观测（BILBO）寄存器来检查控制只读存储器（CROM）中的信息。来自控制只读存储器的输出数据被锁存在增强的BILBO寄存器中，用作大计数器的计数器。在耐力测试（Autocycle）期间，使用增强型计数器的微定序器（MC）监控片上受控耐久性测试周期的数量。在参数特征测试（AutoVccMax / Min）期间，片上数模转换器（DAC）引起提供给数据单元（10）和参考单元（10）的电源电压（Vcc）的阶梯式变化记忆。

89. 发明授权

US5657282A Semiconductor memory device with stress circuit and method for supplying a stress voltage thereof 失效
标题翻译：具有应力电路的半导体存储器件及其应力电压的提供方法
公开(公告)号：US5657282A
公开(公告)日：1997-08-12
申请号：US400995
申请日：1995-03-09
申请人： Kyu-Chan Lee
发明人： Kyu-Chan Lee
IPC分类号： G11C11/413 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/02 , G11C29/06 , G11C29/50 , G11C29/56
CPC分类号： G11C29/50 , G11C11/401
摘要： A semiconductor integrated circuit with a stress circuit and a stress voltage supplying method thereof ensures the reliability of the device. The semiconductor integrated circuit has a stress enable circuit for generating an enable signal during a test operation of the chip and for enabling the test operation, a stress voltage supplying circuit for supplying a first stress voltage and a second stress voltage in response to an output signal of the stress enable circuit during the test operation, and a sensing delay control circuit for receiving the first and second stress voltages and for delaying an operation of the sense amp control circuit during the test operation. During the test operation, the first and second stress voltages are supplied to word lines adjacent to each other in response to the output signal of the stress enable circuit, and a state of a selected memory cell by the word line is sensed in response to an output signal of the sensing delay control circuit.
摘要翻译：具有应力电路和应力电压提供方法的半导体集成电路确保了器件的可靠性。半导体集成电路具有应力使能电路，用于在芯片的测试操作期间产生使能信号并使能测试操作;应力电压供应电路，用于响应输出信号提供第一应力电压和第二应力电压以及用于接收第一和第二应力电压并用于在测试操作期间延迟读出放大器控制电路的操作的感测延迟控制电路。在测试操作期间，第一和第二应力电压响应于应力使能电路的输出信号被提供给彼此相邻的字线，并且响应于一个字线检测所选择的存储单元的状态感测延迟控制电路的输出信号。

90. 发明授权

US5606528A Semiconductor memory device allowing data rewriting electrically 失效
标题翻译：半导体存储器件允许电气数据重写
公开(公告)号：US5606528A
公开(公告)日：1997-02-25
申请号：US553910
申请日：1995-11-06
申请人： Yutaka Ikeda
发明人： Yutaka Ikeda
IPC分类号： G11C11/401 , G11C11/409 , G11C29/00 , G11C29/04 , G11C29/06 , G11C29/34 , G11C8/00
CPC分类号： G11C29/34
摘要： A memory array block MK of the same structure is arranged in all the memory array regions MA of a DRAM. An IO line control circuit connects the other end of a pair of local signal input/output lines to one end of a pair of global signal input/output lines in an opposite phase or a positive phase in response to one end of the corresponding pair of local signal input/output lines being connected to an even numbered bit line pair of the upper row of memory array region MA or an odd numbered bit line pair of the lower row of memory array region MA. Since the memory array blocks MK in all the memory array region MA have the same structure, a memory cell corresponding to a defective address detected in a BI test can easily be identified.
摘要翻译：具有相同结构的存储器阵列块MK被布置在DRAM的所有存储器阵列区域MA中。 IO线路控制电路将一对本地信号输入/输出线路的另一端连接到一对全局信号输入/输出线路的一端，以响应相应的一对本地信号输入/输出线连接到存储器阵列区域MA的上一行或存储器阵列区域MA的下行的奇数位线对中的偶数位线对。由于所有存储器阵列区域MA中的存储器阵列块MK具有相同的结构，因此可以容易地识别与在BI测试中检测到的缺陷地址相对应的存储单元。

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