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81. 发明授权

US5105103A Integrated binary amplifier having a Darlington configuration 失效
标题翻译：具有DARLINGTON配置的集成二进制放大器
公开(公告)号：US5105103A
公开(公告)日：1992-04-14
申请号：US430668
申请日：1989-11-02
申请人： Georges Neu
发明人： Georges Neu
IPC分类号： H03K5/02 , H03K19/013 , H03K19/0175 , H03K19/08 , H03K19/0944
CPC分类号： H03K19/09448 , H03K19/0136
摘要： An integrated binary amplifier connected to a bus such as a precharged bus and having a field effect transistor receiving an input signal and coupled to series-connected bipolar transistors including an output transistor. The base of the output transistor is connected to a fixed potential by a field effect transistor of which the type and the control means assure its conduction when the bipolar transistors are conductive. The output signal thus has its low level to ground.
摘要翻译：连接到诸如预充电总线的总线并具有接收输入信号并且耦合到包括输出晶体管的串联双极晶体管的场效应晶体管的集成二进制放大器。输出晶体管的基极通过场效应晶体管连接到固定电位，其中类型和控制装置在双极晶体管导通时确保其导通。因此，输出信号的接地电平低。

82. 发明授权

US5075571A PMOS wordline boost cricuit for DRAM 失效
标题翻译：用于DRAM的PMOS字线升压电路
公开(公告)号：US5075571A
公开(公告)日：1991-12-24
申请号：US636840
申请日：1991-01-02
申请人： Sang H. Dhong , Wei Hwang , Yoichi Taira
发明人： Sang H. Dhong , Wei Hwang , Yoichi Taira
IPC分类号： G11C11/407 , G11C11/408 , H01L21/76 , H01L21/8242 , H01L27/10 , H01L27/108 , H03K5/02
CPC分类号： H03K5/023 , G11C11/4085
摘要： A wordline driver circuit is shown for a DRAM, the circuit comprising a PMOS transistor structure having one contact coupled to a wordline, a second contact coupled to a negative voltage supply and a gate coupled to a control input, the transistor having an N-well about the gate, first and second contacts. An isolating structure is positioned about the N-well to enable it to be a separately controlled from surrounding N-well structures. Pulse circuits are coupled to the transistor for applying, when activated, a potential that enables the wordline to transition to a more negative potential. A bias circuit is also provided for biasing the N-well at a first potential and a second lower potential, the second lower potential applied when the pulse circuits are activated. As a result, body effects in the PMOS transistor are minimized while at the same time enabling a boost potential to be applied to the wordline.

83. 发明授权

US5072278A Monolithic integrated structure for a two-stage driving system with level translator circuit component of the driving signal for power transistors 失效
标题翻译：用于功率晶体管驱动信号的电平转换器电路的两级驱动系统的单片集成结构
公开(公告)号：US5072278A
公开(公告)日：1991-12-10
申请号：US480162
申请日：1990-02-14
申请人： Mario Paparo , Sergio Palara
发明人： Mario Paparo , Sergio Palara
IPC分类号： H01L21/822 , H01L21/8222 , H01L27/04 , H01L27/06 , H03K5/02
CPC分类号： H01L27/0623
摘要： The monolithic integrated structure comprises a semiconductor substrate, a superimposed first epitaxial stratum having characteristics such as to withstand a high supply voltage applied to the driving system and a first and a second isolation pocket which may be connected to a high voltage and to ground, respectively, and diffused in said first epitaxial stratum at a distance such as to define an interposed area of said first stratum capable of isolating said isolating pockets from one another. Within the latter pockets, there are provided respective embedded strata and superimposed regions of a second epitaxial stratum having characteristics such as to withstand the low voltage applied across the two driving stages. A further region of said second epitaxial stratum is superimposed over said area of said first epitaxial stratum. The above regions of isolation pockets are designed for the formation of two high and low voltage driving stages, while the above further region of the second epitaxial stratum may be used for the formation of a level translator circuit component. Means are provided for the protection of said circuit component against high supply voltages.

84. 发明授权

US5043606A Apparatus and method for programmably controlling the polarity of an I/O signal of a magnetic disk drive 失效
标题翻译：用于可编程地控制磁盘驱动器的I / O信号的极性的装置和方法
公开(公告)号：US5043606A
公开(公告)日：1991-08-27
申请号：US502568
申请日：1990-03-30
申请人： David M. Lewis
发明人： David M. Lewis
IPC分类号： G06F13/40 , G11B19/00 , H03K5/02 , H03K19/173
CPC分类号： H03K19/1736 , G06F13/4072 , G11B19/00 , H03K5/026
摘要： A programmable register stores a control bit for settting the logic polarity of an I/O signal at an I/O terminal of an integrated circuit. The I/O polarity control signal is combined in an exclusive-OR logic circuit with the I/O signal to provide a given logic polarity for the I/O signal. For a bi-directional I/O terminal, two exclusive-OR gates are used, one for controlling polarity of output signals from the integrated circuit to the I/O terminal and the other for controlling the polarity of input signals to the integrated circuits which are received at the I/O terminal. The control of the I/O signal polarity is particularly useful for a disk-drive controller which interfaces with different magnetic disk drive units, having different I/O signal polarity requirements.
摘要翻译：可编程寄存器存储用于设置集成电路的I / O端子处的I / O信号的逻辑极性的控制位。 I / O极性控制信号在异或逻辑电路中与I / O信号组合，为I / O信号提供给定的逻辑极性。对于双向I / O端子，使用两个异或门，一个用于控制从集成电路到I / O端子的输出信号的极性，另一个用于控制到集成电路的输入信号的极性，在I / O终端接收。 I / O信号极性的控制对于具有不同I / O信号极性要求的不同磁盘驱动单元的磁盘驱动器控制器特别有用。

85. 发明授权

US5030853A High speed logic and memory family using ring segment buffer 失效
标题翻译：高速逻辑和存储器系列使用环形缓冲区
公开(公告)号：US5030853A
公开(公告)日：1991-07-09
申请号：US497103
申请日：1990-03-21
申请人： Albert W. Vinal
发明人： Albert W. Vinal
IPC分类号： H01L21/8249 , H01L27/06 , H01L27/07 , H01L27/10 , H01L27/118 , H03K3/03 , H03K3/356 , H03K5/02 , H03K5/13 , H03K17/567 , H03K19/017 , H03K19/08 , H03K19/0944 , H03K19/0948
CPC分类号： H03K19/01707 , H03K17/567 , H03K19/09448 , H03K19/0948 , H03K3/03 , H03K3/356156 , H01L27/0716 , H01L27/11898
摘要： A logic and memory family using CMOS technology operates at high speeds using a Ring Segment Buffer to couple logic gates to one another in an integrated circuit chip, and to couple memory cells to other circuits to provide shift registers, triggers, clock pulse generators and other memory related circuits. The Ring Segment Buffer comprises one or more serially connected complementary field effect transistor (FET) inverter stages, with the output of a preceding stage being connected to the input of a succeeding stage. The N-channel FET in each inverter stage has a channel width which is less than a predetermined factor (K) times the width of the N-channel of the immediately preceding stage. By maintaining the K channel width relationship, the Ring Segment Buffer can drive large capacitive loads at high speed. The Ring Segment Buffer may also provide a predetermined delay which is a function of channel length and the number of stages. For large capacitive loads, the last stage of the Ring Segment Buffer may be replaced by a bipolar transistor-FET driver in which minority carrier lifetime controlled bipolar transistors are used.The Buffer Cell Logic and Delay Storage technology of the present invention may operate at speeds of 300 megahertz or more using conventional semiconductor fabrication processes in which conventional CMOS logic and memory technology operates at 70 megahertz or less. A fourfold speed improvement is thereby obtained.
摘要翻译：使用CMOS技术的逻辑和存储器系列使用环形段缓冲器以高速度运行，以在集成电路芯片中将逻辑门耦合到彼此，并将存储器单元耦合到其他电路以提供移位寄存器，触发器，时钟脉冲发生器等存储器相关电路。环形段缓冲器包括一个或多个串联的互补场效应晶体管（FET）反相器级，前级的输出连接到后级的输入端。每个逆变器级的N沟道FET的通道宽度小于前一级的N沟道的宽度的预定因子（K）。通过保持K通道宽度关系，环形段缓冲器可以高速驱动大容量负载。环段缓冲器还可以提供预定的延迟，其是信道长度和级数的函数。对于大容性负载，环形段缓冲器的最后一级可以由其中使用少数载流子寿命受控双极晶体管的双极型晶体管FET驱动器代替。本发明的缓冲器单元逻辑和延迟存储技术可以使用传统的CMOS逻辑和存储器技术在70兆赫或更小的工作条件下使用的常规半导体制造工艺以300兆赫或更高的速度工作。从而获得四倍的速度改善。

86. 发明授权

US5013943A Single ended sense amplifier with improved data recall for variable bit line current 失效
标题翻译：单端读出放大器，具有改进的位线电流数据调用功能
公开(公告)号：US5013943A
公开(公告)日：1991-05-07
申请号：US393489
申请日：1989-08-11
申请人： Ryan T. Hirose
发明人： Ryan T. Hirose
IPC分类号： G11C17/00 , G11C7/06 , G11C16/06 , H03K5/02
CPC分类号： H03K5/023 , G11C7/067
摘要： A single ended sense amplifier senses whether or not a memory cell in an array conducts current from a bit line conductor to which the sense amplifier is connected. A first stage of the sense amplifier includes a number of separately biased transistors which establish a lower voltage level at a node when the cell conducts current than the higher voltage level at the node when the cell does not conduct current. A second stage of the sensed amplifier includes transistors connected in an inverting arrangement to receive the signal from the node and supply an output signal at an output terminal in response thereto. An equalizing transistor is selectively connected between the node and the output terminal and establishes a high gain bias point voltage at the node when conductive. The high gain bias point in intermediate the higher and lower voltages established at the node by the first stage. As soon as the equalizing transistor becomes nonconductive, the second stage is immediately driven to the correct output signal level by the voltage at the node from the first stage. A precharge transistor is conneced to the bit line to raise the voltage on it to a predetermined high level, thereafter allowing the voltage to decay before sensing the logical state of the cell. Precharging the bit line avoids the uncertainties associated with charging the bit line capacitance.
摘要翻译：单端读出放大器检测阵列中的存储单元是否从连接读出放大器的位线导体传导电流。读出放大器的第一级包括多个单独偏置的晶体管，当单元不传导电流时，当单元传导电流时，在节点处，当节点传导电流时，在节点处建立较低的电压电平。感测放大器的第二级包括以反相装置连接的晶体管，用于接收来自节点的信号，并响应于此在输出端提供输出信号。均衡晶体管选择性地连接在节点和输出端之间，并在导电时在节点处建立高增益偏置点电压。在第一级在节点处建立的较高和较低电压中间的高增益偏置点。一旦均衡晶体管变得不导通，第二级立即从第一级的节点处的电压驱动到正确的输出信号电平。将预充电晶体管连接到位线，以将其上的电压升高到预定的高电平，之后允许电压在感测电池的逻辑状态之前衰减。预充电位线避免了与位线电容充电相关的不确定性。

87. 发明授权

US4980583A CMOS level shift circuit with active pull-up and pull-down 失效
标题翻译：具有主动上拉和下拉功能的CMOS电平移位电路
公开(公告)号：US4980583A
公开(公告)日：1990-12-25
申请号：US292809
申请日：1989-01-03
申请人： Paul H. Dietz
发明人： Paul H. Dietz
IPC分类号： H03K5/02 , H03K3/356 , H03K19/0185
CPC分类号： H03K3/356104
摘要： A CMOS level shift circuit with active pull-up uses a pair of pull up transistors activated during the period when an output node needs to be rapidly pulled up. The pull up transistors are activated by the outputs of a combinatorial logic or memory circuit detecting when a change of input signal has occurred and activating the respective pull up transistor to bring the output to the proper state.

88. 发明授权

US4962343A Signal transmission circuit 失效
标题翻译：信号传输电路
公开(公告)号：US4962343A
公开(公告)日：1990-10-09
申请号：US303797
申请日：1989-01-27
申请人： Shin-ichi Nakagawa , Hiroyuki Kawai
发明人： Shin-ichi Nakagawa , Hiroyuki Kawai
IPC分类号： G06F3/00 , H03K5/02 , H03K17/687 , H03K17/693 , H04L25/02
CPC分类号： H03K17/6872 , H03K17/693 , H03K5/023 , H03K5/026
摘要： A signal transmission circuit constructed such that, when a signal of one channel is transmitted in two-divided signal transmission lines, discharge switching elements on two precharged signal transmission lines are controlled by four switching elements (three P-channel MOS transistors and one N-channel MOS transistor). Therefore, when one signal transmission line is at a low level during a signal transmission period, the discharge switching elements of both the signal transmitting lines conduct, leading one signal transmission line to be discharged. This causes the low level signal to be transmitted to the other signal transmitting line.
摘要翻译：一种信号传输电路，其被构造成使得当在两分信号传输线中发送一个信道的信号时，两个预充电信号传输线上的放电开关元件由四个开关元件（三个P沟道MOS晶体管和一个N- 通道MOS晶体管）。因此，在信号传输期间，当一个信号传输线处于低电平时，两个信号传输线的放电开关元件导通，导致一个信号传输线被放电。这使得低电平信号被发送到另一个信号传输线。

89. 发明授权

US4958094A Emitter follower circuit with MOSFET 失效
标题翻译：发射极跟随电路与MOSFET
公开(公告)号：US4958094A
公开(公告)日：1990-09-18
申请号：US391605
申请日：1989-06-28
申请人： Yasuhiro Ishii , Isao Fukushi
发明人： Yasuhiro Ishii , Isao Fukushi
IPC分类号： H03K5/02 , H03K3/356 , H03K19/00 , H03K19/01 , H03K19/0175
CPC分类号： H03K3/356017 , H03K19/0016
摘要： In an emitter follower circuit including an emitter follower transistor (Q3, Q4), and a series-connected circuit connected to the emitter of the emitter follower transistor and including a current source (Q3, Q4) and a current source resistor, the current source resistor being formed by a MOS transistor (N4, N5), the emitter follower circuit being switched to active and inactive states by switching the state of the MOS transistor (N4, N5) by a control signal, there is provided current path means provided between the source and drain of the MOS transistor, for providing a resistance considerably larger than a resistance of the MOS transistor provided during conducting when the MOS transistor is at least cut off and passing an extremely small current passes therethrough at that time.

90. 发明授权

US4918341A High speed static single-ended sense amplifier 失效
标题翻译：高速静态单端感测放大器
公开(公告)号：US4918341A
公开(公告)日：1990-04-17
申请号：US230764
申请日：1988-09-23
申请人： Douglas C. Galbraith , Michael G. Ahrens
发明人： Douglas C. Galbraith , Michael G. Ahrens
IPC分类号： G11C7/06 , H03F3/70 , H03K5/02
CPC分类号： H03F3/70 , G11C7/06 , H03K5/023
摘要： A high speed static single ended sense amplifier is disclosed, including, an input node, an output node, a first P-channel input transistor having its source connected to a source of positive voltage, its drain connected to the input node and its gate connected to a feedback node, a first N-channel input transistor having its drain connected to the input node, its source connected to a source of negative voltage and its gate connected to the feedback node, a first output P-channel transistor having its source connected to a source of positive voltage, its drain connected to the output node, and its gate connected to the feedback node, a first N-channel output transistor having its drain connected to the output node, its source connected to a source of positive voltage and its gate connected to the feedback node, an N-channel feedback transistor having its gate connected to the output node, its drain connected to a source of positive voltage and its source connected to the feedback node, a capacitive voltage divider connected between the source of negative voltage, the source of positive voltage, and the input node, the capacitive voltage divider including a parasitic capacitance and a P-channel gate capacitor connected between the input node and one of the positive or negative voltage sources, the capacitance ratio of the capacitive voltage divider being such as to give the same voltage divider ratio as the voltage divider ratio resulting from the first P-channel MOS input transistor and the first N-channel MOS input transistor.
摘要翻译：公开了一种高速静态单端读出放大器，其包括输入节点，输出节点，其源极连接到正电压源的第一P沟道输入晶体管，其漏极连接到输入节点，并且其栅极连接到反馈节点，第一N沟道输入晶体管的漏极连接到输入节点，其源极连接到负电源并且其栅极连接到反馈节点，第一输出P沟道晶体管的源极连接到正电压源，其漏极连接到输出节点，其栅极连接到反馈节点，第一N沟道输出晶体管的漏极连接到输出节点，其源极连接到正电压源，其栅极连接到反馈节点，N沟道反馈晶体管的栅极连接到输出节点，其漏极连接到正电压源，其源极连接到反馈节点连接在负电压源，正电压源和输入节点之间的电容分压器，电容分压器包括寄生电容和连接在输入节点与其中一个正极或负极之间的P沟道栅极电容器负电压源，电容分压器的电容比使得能够提供与由第一P沟道MOS输入晶体管和第一N沟道MOS输入晶体管产生的分压比相同的分压比。

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