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81. 发明申请

US20170069526A1 CHUCK ASSEMBLY WITH TILTABLE CHUCK AND SEMICONDUCTOR FABRICATION SYSTEM INCLUDING THE SAME 审中-公开
标题翻译：具有可折叠式卡盘和包括其中的半导体制造系统的卡盘组件
公开(公告)号：US20170069526A1
公开(公告)日：2017-03-09
申请号：US15170151
申请日：2016-06-01
申请人： Jongsoon PARK , Jong-Kyu KIM , Jung-Ik OH , Sang-Kuk KIM , Jongchul PARK
发明人： Jongsoon PARK , Jong-Kyu KIM , Jung-Ik OH , Sang-Kuk KIM , Jongchul PARK
IPC分类号： H01L21/687 , H01J37/305 , H01L21/263
CPC分类号： H01L21/68764 , H01J37/20 , H01J37/3056 , H01J2237/20207 , H01J2237/20214 , H01J2237/31 , H01L21/2633 , H01L21/68792
摘要： A chuck assembly includes a chuck to hold a substrate, and a pillar coupled to the chuck to support the chuck, an axis of the pillar passing through a center of the pillar in a longitudinal direction of the pillar, wherein the chuck has a top surface, which is inclined with respect to the axis of the pillar, the top surface of the chuck being precessionally rotatable about the axis of the pillar.
摘要翻译：卡盘组件包括夹持基板的卡盘，以及联接到卡盘以支撑卡盘的支柱，支柱的轴线沿着柱的纵向方向穿过柱的中心，其中卡盘具有顶表面，其相对于柱的轴线倾斜，卡盘的顶表面可以围绕柱的轴线进行旋转。

82. 发明申请

US20170069482A1 FLOAT ZONE SILICON WAFER MANUFACTURING SYSTEM AND RELATED PROCESS 审中-公开
标题翻译： FLOAT ZONE SILICON WAFER制造系统及相关流程
公开(公告)号：US20170069482A1
公开(公告)日：2017-03-09
申请号：US15354957
申请日：2016-11-17
申请人： Rayton Solar Inc.
发明人： Andrew X. Yakub , James Benjamin Rosenzweig , Mark Stanley Goorsky
IPC分类号： H01L21/02 , H01L21/263 , C30B33/02 , C30B13/20 , C30B29/06
CPC分类号： H01L21/02035 , B28D5/00 , C30B13/20 , C30B13/24 , C30B29/06 , C30B29/64 , C30B33/02 , C30B33/06 , H01L21/263 , Y10T117/1088
摘要： The process for manufacturing a silicon wafer includes steps for mounting a float zone silicon work piece for exfoliation, energizing a microwave device for generating an energized beam sufficient for penetrating an outer surface layer of the float zone silicon work piece, exfoliating the outer surface layer of the float zone silicon work piece with the energized beam, and removing the exfoliated outer surface layer from the float zone silicon work piece as the silicon wafer having a thickness less than 100 micrometers.
摘要翻译：用于制造硅晶片的工艺包括用于安装用于剥离的浮动区硅工件的步骤，为微波装置通电以产生足以穿透浮动区硅工件的外表面层的通电束，使外表面层具有通电束的浮区硅工件，并且将硅剥离的外表面层从浮区硅工件中去除，其厚度小于100微米。

83. 发明授权

US09583434B2 Metal line structure and method 有权
标题翻译：金属线结构及方法
公开(公告)号：US09583434B2
公开(公告)日：2017-02-28
申请号：US14334929
申请日：2014-07-18
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hsiang-Lun Kao , Hsiang-Wei Liu , Tai-I Yang , Jian-Hua Chen , Yu-Chieh Liao , Yung-Chih Wang , Tien-Lu Lin
IPC分类号： H01L23/528 , H01L23/522 , H01L21/311 , H01L21/768 , H01L21/263 , H01L23/532
CPC分类号： H01L23/5283 , H01L21/2633 , H01L21/31111 , H01L21/7682 , H01L21/76834 , H01L21/76879 , H01L21/76885 , H01L23/5222 , H01L23/5226 , H01L23/528 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A device comprises a first rounded metal line in a metallization layer over a substrate, a second rounded metal line in the metallization layer, a first air gap between sidewalls of the first rounded metal line and the second metal line, a first metal line in the metallization layer, wherein a top surface of the first metal line is higher than a top surface of the second rounded metal line and a bottom surface of the first metal line is substantially level with a bottom surface of the second rounded metal line and a second air gap between sidewalls of the second rounded metal line and the first metal line.
摘要翻译：器件包括在衬底上的金属化层中的第一圆形金属线，金属化层中的第二圆形金属线，第一圆形金属线的侧壁与第二金属线之间的第一气隙，金属化层，其中第一金属线的顶表面高于第二圆形金属线的顶表面，并且第一金属线的底表面基本上与第二圆形金属线的底表面平齐，第二空气第二圆形金属线的侧壁与第一金属线之间的间隙。

84. 发明授权

US09577081B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09577081B2
公开(公告)日：2017-02-21
申请号：US15006164
申请日：2016-01-26
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA
发明人： Satoru Kameyama , Shinya Iwasaki
IPC分类号： H01L29/74 , H01L29/739 , H01L29/08 , H01L29/10 , H01L29/32 , H01L29/66 , H01L29/861 , H01L21/263 , H01L21/265
CPC分类号： H01L29/7397 , H01L21/263 , H01L21/26506 , H01L27/0727 , H01L29/0804 , H01L29/0821 , H01L29/0834 , H01L29/1095 , H01L29/32 , H01L29/407 , H01L29/6609 , H01L29/66348 , H01L29/861 , H01L29/8613
摘要： A semiconductor device includes a semiconductor substrate that includes an IGBT region. A first lifetime control layer extending along a planar direction of the semiconductor substrate is provided in a range in a drift region that is closer to the rear surface than an intermediate portion of the semiconductor substrate in a thickness direction. A crystal defect density in the first lifetime control layer is higher than any of a crystal defect density in a region adjacent to the first lifetime control layer on the rear surface side and a crystal defect density in a region adjacent to the first lifetime control layer on a front surface side. A crystal defect density in a region between the first lifetime control layer and the rear surface is lower than a crystal defect density in a region between the first lifetime control layer and the front surface.
摘要翻译：半导体器件包括包括IGBT区域的半导体衬底。在半导体衬底的平面方向上延伸的第一寿命控制层设置在比半导体衬底的厚度方向的中间部分更靠近后表面的漂移区域的范围内。第一寿命控制层中的晶体缺陷密度高于与背面侧的第一寿命控制层相邻的区域的晶体缺陷密度以及与第一寿命控制层相邻的区域的晶体缺陷密度前表面侧。在第一寿命控制层和后表面之间的区域中的晶体缺陷密度低于第一寿命控制层和前表面之间的区域中的晶体缺陷密度。

85. 发明授权

US09548209B2 Method for integrated circuit fabrication 有权
标题翻译：集成电路制造方法
公开(公告)号：US09548209B2
公开(公告)日：2017-01-17
申请号：US14625341
申请日：2015-02-18
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ching-Fang Yu , Chia-Ching Huang , Ting-Hao Hsu
IPC分类号： B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00 , H01L21/308 , H01L21/263 , G03F7/20 , H01L21/027
CPC分类号： H01L21/3086 , G03F7/203 , G03F7/70433 , G03F7/70466 , H01L21/0274 , H01L21/2633 , H01L21/3088
摘要： Provided is an integrated circuit (IC) fabrication method. The method includes receiving a mask, the mask having a plurality of dies and receiving a wafer, the wafer having a resist layer. The method further includes exposing the resist layer using the mask with a fraction radiation dose thereby forming a first plurality of images; re-positioning the mask relative to the wafer; and exposing the resist layer using the mask with another fraction radiation dose. A second plurality of images is formed, wherein a portion of the second plurality of images is superimposed over another portion of the first plurality of images.
摘要翻译：提供了一种集成电路（IC）制造方法。所述方法包括接收掩模，所述掩模具有多个管芯并接收晶片，所述晶片具有抗蚀剂层。该方法还包括使用掩模以分数辐射剂量曝光抗蚀剂层，从而形成第一多个图像; 将掩模相对于晶片重新定位; 并用另一分数辐射剂量使用掩模曝光抗蚀剂层。形成第二多个图像，其中第二多个图像的一部分叠加在第一多个图像的另一部分上。

86. 发明申请

US20170005013A1 Workpiece Processing Technique 审中-公开
标题翻译：工件加工技术
公开(公告)号：US20170005013A1
公开(公告)日：2017-01-05
申请号：US14788306
申请日：2015-06-30
申请人： Varian Semiconductor Equipment Associates, Inc.
发明人： Morgan D. Evans , Kevin Anglin , Ross Bandy
IPC分类号： H01L21/66 , H01L21/265 , H01L21/02 , H01L21/285 , H01L21/3065 , H01L21/263
CPC分类号： H01L21/28506 , H01J2237/30433 , H01J2237/31 , H01L22/12 , H01L22/20
摘要： Methods for processing of a workpiece are disclosed. The actual rate at which different portions of an ion beam can process a workpiece, referred to as the processing rate profile, is determined by measuring the amount of material removed from, or added to, a workpiece by the ion beam as a function of ion beam position. An initial thickness profile of a workpiece to be processed is determined. Based on the initial thickness profile, a target thickness profile, and the processing rate profile of the ion beam, a first set of processing parameters are determined. The workpiece is then processed using this first set of processing parameters. In some embodiments, an updated thickness profile is determined after the first process and a second set of processing parameters are determined. A second process is performed using the second set of processing parameters. Optimizations to improve throughput are also disclosed.
摘要翻译：公开了加工工件的方法。离子束的不同部分可以处理工件的实际速率（称为加工速率曲线）通过测量离子束作为离子的函数从工件移除或添加到工件中的量来确定梁位置。确定要处理的工件的初始厚度分布。基于初始厚度分布，目标厚度分布和离子束的处理速率分布，确定第一组处理参数。然后使用该第一组处理参数处理工件。在一些实施例中，在第一过程和第二组处理参数被确定之后确定更新的厚度分布。使用第二组处理参数来执行第二处理。还公开了提高吞吐量的优化。

87. 发明授权

US09536948B2 Semiconductor device, method of manufacturing the same, and power module 有权
标题翻译：半导体装置及其制造方法以及电源模块
公开(公告)号：US09536948B2
公开(公告)日：2017-01-03
申请号：US15086153
申请日：2016-03-31
申请人： ROHM CO., LTD.
发明人： Toshio Nakajima
IPC分类号： H01L29/06 , H01L29/32 , H01L29/66 , H01L29/78 , H01L21/265 , H02M7/5387 , H02P6/14 , H01L21/324 , H01L27/088 , H02P27/06 , H01L21/263
CPC分类号： H01L29/7802 , H01L21/263 , H01L21/265 , H01L21/26506 , H01L21/324 , H01L27/088 , H01L27/0883 , H01L29/0634 , H01L29/0684 , H01L29/0696 , H01L29/32 , H01L29/66666 , H01L29/66712 , H01L29/7827 , H02M7/5387 , H02P6/14 , H02P27/06
摘要： A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer.
摘要翻译：半导体器件包括n型漏极层，设置在n型漏极层上的n型基极层，部分地形成在n型漏极层的表面层部分中的p型基极层和n型源极层基极层和p型基极层，形成在n型源极层和n型基极层之间的p型基极层的表面上的栅极绝缘膜，形成在栅极绝缘体上的栅电极覆盖栅极绝缘膜的p型基底层的膜，从n型基极层形成的p型列层，从p型基极层朝向n型漏极层延伸，耗尽层缓和区域布置在p型列层和n型漏极层之间，并且包括转换为馈电体的第一重子，连接到n型源极层的源电极和连接到n型漏极层的漏电极。

88. 发明授权

US09536754B2 Method of forming contact structure of gate structure 有权
标题翻译：形成栅极结构接触结构的方法
公开(公告)号：US09536754B2
公开(公告)日：2017-01-03
申请号：US14840099
申请日：2015-08-31
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Audrey Hsiao-Chiu Hsu , Fu-Kai Yang , Mei-Yun Wang , Hsien-Cheng Wang , Shih-Wen Liu , Hsin-Ying Lin
IPC分类号： H01L21/00 , H01L21/3205 , H01L27/088 , H01L21/768 , H01L21/8234 , H01L29/66 , H01L29/49 , H01L21/321 , H01L23/485 , H01L23/532 , H01L21/263 , H01L21/311 , H01L21/285
CPC分类号： H01L21/76897 , H01L21/2633 , H01L21/28518 , H01L21/31116 , H01L21/32051 , H01L21/32053 , H01L21/32105 , H01L21/3212 , H01L21/76805 , H01L21/76831 , H01L21/7684 , H01L21/823425 , H01L21/823475 , H01L23/485 , H01L23/53261 , H01L23/53266 , H01L23/535 , H01L27/088 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate are etched to expose an underlying silicon substrate. A silicide portion defined by a contact profile is deposited in the exposed portion of the silicon substrate. A second sidewall layer substantially covers the first sidewall layer and at least partially covering the silicide portion is formed after depositing the silicide portion. A metal glue layer is deposited around the first metal gate and the second metal gate defining a trench above the silicide portion. A metal plug is deposited within the trench.
摘要翻译：提供一种形成栅极结构的接触结构的方法。在该方法中，蚀刻设置在第一金属栅极和第二金属栅极之间的氧化层和第一侧壁层，以暴露下面的硅衬底。由接触轮廓限定的硅化物部分沉积在硅衬底的暴露部分中。在沉积硅化物部分之后形成基本上覆盖第一侧壁层并且至少部分地覆盖硅化物部分的第二侧壁层。金属胶层沉积在第一金属栅极周围，第二金属栅极限定硅化物部分之上的沟槽。金属塞被沉积在沟槽内。

89. 发明授权

US09530650B2 Method of creation of defects using X-ray radiation and electric field and its application 有权
标题翻译：使用X射线辐射和电场产生缺陷的方法及其应用
公开(公告)号：US09530650B2
公开(公告)日：2016-12-27
申请号：US14436934
申请日：2013-10-16
申请人： VILNIUS UNIVERSITY
发明人： Romaldas Purlys , Arvydas Juozapas Janavicius , Vitalij Balandin , Mindaugas Viliunas , Saulius Balakauskas , Andrius Poskus
IPC分类号： H01L21/00 , H01L21/268 , H01L21/263 , H01L21/326 , H01L31/068 , H01L31/18 , H01L21/22
CPC分类号： H01L21/2683 , H01L21/22 , H01L21/263 , H01L21/326 , H01L31/068 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： The goal is the improvement of technologies of modification of material properties by decreasing expenditures of energy and time and extending possibilities for modification of the materials by creating and maintaining a metastable state, which is characterized by a change in the structure of the material. The invention belongs to the technological field of manufacturing materials with desired properties, and in part to the field of methods of defect generation in crystals, and it can be applied in industries that apply the process of material doping with impurities in order to manufacture materials having a desired concentration of defects and an increased concentration of charge carriers, to create a metastable structural state of the material, as well as to measure energy and doses of radio waves.
摘要翻译：目标是通过减少能量和时间的支出来改进材料性质的改进技术，并且通过产生和保持亚稳态（通过材料结构的变化来表征）来延长材料的修饰的可能性。本发明属于具有所需性能的制造材料的技术领域，部分地涉及晶体缺陷产生方法领域，并且可应用于应用材料掺杂杂质的工艺以制造具有期望的缺陷浓度和电荷载体的增加浓度，以产生材料的亚稳态结构状态，以及测量无线电波的能量和剂量。

90. 发明申请

US20160351671A1 METHODS FOR FORMING WRAP AROUND CONTACT 有权
标题翻译：形成接缝的方法
公开(公告)号：US20160351671A1
公开(公告)日：2016-12-01
申请号：US15231967
申请日：2016-08-09
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chan Syun David Yang
IPC分类号： H01L29/417 , H01L29/40 , H01L29/08 , H01L21/263 , H01L21/265 , H01L29/45 , H01L29/78 , H01L21/311
CPC分类号： H01L29/41791 , H01L21/263 , H01L21/26506 , H01L21/26533 , H01L21/31116 , H01L21/823431 , H01L27/0886 , H01L29/0847 , H01L29/165 , H01L29/401 , H01L29/45 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L29/7851 , H01L2029/7858
摘要： Some embodiments of the present disclosure relate to a contact formed to a source or drain region of a “finned” field-effect transistor (FinFET). An epitaxial material is formed over the source or drain region, which includes a diamond-shaped cross-section with top and bottom surfaces. A capping layer is formed over the top and bottom surfaces. The source or drain region is subjected to a first etch to remove the capping layer surrounding the top surfaces of the diamond-shaped cross-section. A protective layer is formed within the top surfaces. A second etch of the capping layer is performed to remove the capping layer surrounding the bottom surfaces of the diamond-shaped cross-section, while using the protective layer to prevent etching of the top surfaces by the second etch. A contact is formed to the source or drain region, which surrounds the source or drain region on the top and bottom surfaces.
摘要翻译：本公开的一些实施例涉及形成于“鳍状”场效应晶体管（FinFET）的源极或漏极区域的接触。在源极或漏极区域上形成外延材料，其包括具有顶部和底部表面的菱形横截面。在顶表面和底表面上形成覆盖层。对源极或漏极区域进行第一蚀刻以去除围绕菱形横截面的顶表面的封盖层。在顶表面内形成保护层。执行覆盖层的第二次蚀刻以去除围绕钻石形横截面的底表面的覆盖层，同时使用保护层以防止通过第二蚀刻蚀刻顶表面。接触件形成在源极或漏极区域，其围绕顶部和底部表面上的源极或漏极区域。

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