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1. 发明公开

US20240274462A1 SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PLACING METHOD 审中-公开
公开(公告)号：US20240274462A1
公开(公告)日：2024-08-15
申请号：US18441518
申请日：2024-02-14
申请人： Tokyo Electron Limited
发明人： Makoto Fujiwara , Kenji Sugakawa , Hideyuki Fukushima , Norifumi Kohama , Daisuke Ikemoto
IPC分类号： H01L21/683 , H01L21/02 , H01L21/67 , H01L21/687
CPC分类号： H01L21/6838 , H01L21/02035 , H01L21/67092 , H01L21/67288 , H01L21/68714
摘要： A substrate processing apparatus is equipped with a holder having, on an attraction surface configured to attract a substrate, a circular central region and an annular outer region disposed outside the central region. The substrate processing apparatus includes an attracting pressure generator configured to generate an attracting pressure in the central region and each of multiple zones separated along a circumferential direction of the outer region individually; a transforming device configured to transform the central region relative to an outer edge of the holder. A controller controls: attracting the substrate to the attraction surface, based on a bending state of the substrate, by generating the attracting pressure in at least some of the multiple zones of the outer region; and transforming, after the attracting of the substrate, the attraction surface while carrying on the attracting of the substrate.

2. 发明授权

US11710691B2 Semiconductor device and method of forming micro interconnect structures 有权
公开(公告)号：US11710691B2
公开(公告)日：2023-07-25
申请号：US17082512
申请日：2020-10-28
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Francis J. Carney , Jefferson W. Hall , Michael J. Seddon
IPC分类号： H01L23/498 , H01L23/495 , H01L21/48 , H01L23/00 , H01L21/3065 , H01L21/78 , H01L21/67 , H01L21/66 , H01L21/56 , H01L23/31 , H02M3/158 , H01L23/482 , H01L25/065 , H01L25/00 , H01L23/544 , H01L21/02 , H01L21/304 , H01L21/308 , H01L27/146 , H01L21/288 , H01L21/683 , H01L21/768 , H01L23/48 , H01L27/02 , H01L27/088 , H01L27/14 , H01L29/08 , H01L23/15 , H01L23/367 , H01L23/14
CPC分类号： H01L23/49827 , H01L21/02035 , H01L21/288 , H01L21/304 , H01L21/308 , H01L21/3065 , H01L21/3083 , H01L21/486 , H01L21/4825 , H01L21/4853 , H01L21/565 , H01L21/67069 , H01L21/6835 , H01L21/76877 , H01L21/76898 , H01L21/78 , H01L22/12 , H01L22/26 , H01L23/3107 , H01L23/3114 , H01L23/481 , H01L23/4822 , H01L23/4951 , H01L23/49503 , H01L23/49541 , H01L23/49562 , H01L23/49575 , H01L23/49811 , H01L23/49838 , H01L23/49866 , H01L23/544 , H01L23/562 , H01L24/00 , H01L24/05 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L27/0207 , H01L27/088 , H01L27/14 , H01L27/14683 , H01L29/0847 , H02M3/158 , H01L23/147 , H01L23/15 , H01L23/3677 , H01L23/49816 , H01L27/14625 , H01L27/14685 , H01L2221/68327 , H01L2223/5446 , H01L2223/54426 , H01L2224/0401 , H01L2224/04042 , H01L2224/05083 , H01L2224/05084 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05171 , H01L2224/05172 , H01L2224/05184 , H01L2224/13025 , H01L2224/13111 , H01L2224/13116 , H01L2225/06555 , H01L2225/06593 , H01L2225/06596 , H01L2924/13055 , H01L2924/13091 , H01L2924/3511 , H01L2924/3511 , H01L2924/00
摘要： A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

3. 发明公开

US20230207303A1 SEMICONDUCTOR PACKAGING METHOD 审中-公开
公开(公告)号：US20230207303A1
公开(公告)日：2023-06-29
申请号：US18068586
申请日：2022-12-20
申请人： Semiconductor Manufacturing International (Beijing) Corporation , Semiconductor Manufacturing International (Shanghai) Corporation
发明人： Qingzhao LIU , Rex YAN , Yajun ZHAO , Elegant LIU , Yang WANG
IPC分类号： H01L21/02 , H01L23/00 , H01L25/065 , H01L21/3105
CPC分类号： H01L21/02035 , H01L21/0214 , H01L21/0228 , H01L21/02016 , H01L21/02021 , H01L21/31053 , H01L24/29 , H01L24/32 , H01L24/83 , H01L25/0657 , H01L2224/29187 , H01L2224/32145 , H01L2224/83894 , H01L2225/06524 , H01L2225/06568 , H01L2924/1011
摘要： The present disclosure relates to a semiconductor packaging method. The method includes: providing a first wafer; and performing a wafer stacking operation a plurality of times. The wafer stacking operation includes: forming a first to-be-bonded wafer in the shape of a boss, where the first to-be-bonded wafer includes a base and a protrusion from the base, and orientating the protrusion toward a second to-be-bonded wafer and bonding the protrusion to the second to-be-bonded wafer; forming a first dielectric layer on a surface of the protrusion; and performing second trimming on an edge region of the protrusion and an edge region of the second to-be-bonded wafer, so that the remainder of the second to-be-bonded wafer after the second trimming is in the shape of a boss, and using the remainder of the wafer stack after the second trimming as the first to-be-bonded wafer for next wafer stacking.

4. 发明申请

US20180151514A1 SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRIC POWER CONVERSION DEVICE 审中-公开
公开(公告)号：US20180151514A1
公开(公告)日：2018-05-31
申请号：US15815872
申请日：2017-11-17
申请人： HITACHI, LTD.
发明人： Yuan BU
IPC分类号： H01L23/58 , H01L23/522 , H01L21/02
CPC分类号： H01L23/585 , H01L21/02019 , H01L21/02035 , H01L21/02167 , H01L23/5228 , H01L29/0615 , H01L29/0619 , H01L29/1608 , H01L29/36 , H01L29/6606 , H01L29/8613
摘要： A technology is proposed in which the improvement of the capability of a semiconductor device can be realized by satisfying both reduction of leakage currents and suppression of the degradation of the conductive characteristic of the semiconductor device. An electric field relaxation region ERR is formed in an outer edge region on the outside of a mesa structure MS. In addition, an electric charge implantation region EIR formed on a drift layer EPI, a resistance reduction region RR formed on the electric charge implantation region EIR, and a leakage reduction region LR formed at a sidewall portion of the mesa structure MS are formed in the mesa structure MS. In this case, the impurity concentration of the leakage reduction region LR is set larger than the impurity concentration of the electric field relaxation region ERR, and is set smaller than the impurity concentration of the resistance reduction region RR.

5. 发明授权

US09905522B1 Semiconductor copper metallization structure and related methods 有权
公开(公告)号：US09905522B1
公开(公告)日：2018-02-27
申请号：US15254640
申请日：2016-09-01
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Yusheng Lin
IPC分类号： H01L23/52 , H01L23/00 , H01L21/304 , H01L21/265 , H01L21/324 , H01L21/02
CPC分类号： H01L24/05 , H01L21/02035 , H01L21/26513 , H01L21/304 , H01L21/324 , H01L24/03 , H01L24/45 , H01L2224/0218 , H01L2224/0219 , H01L2224/02205 , H01L2224/02215 , H01L2224/03462 , H01L2224/0362 , H01L2224/04042 , H01L2224/05124 , H01L2224/05147 , H01L2224/05184 , H01L2224/05582 , H01L2224/05647 , H01L2224/0603 , H01L2224/45015 , H01L2224/45147 , H01L2924/01028 , H01L2924/01046 , H01L2924/01047 , H01L2924/01079 , H01L2924/07025 , H01L2924/1203 , H01L2924/13055 , H01L2924/2076 , H01L2924/00014
摘要： Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip.

6. 发明授权

US09786527B2 Substrate processing device and substrate processing method for carrying out chemical treatment for substrate 有权
公开(公告)号：US09786527B2
公开(公告)日：2017-10-10
申请号：US15442833
申请日：2017-02-27
申请人： SCREEN Holdings Co., Ltd.
发明人： Nobuyuki Shibayama
IPC分类号： H01L21/67 , H01L21/687 , H01L21/02
CPC分类号： H01L21/6708 , H01L21/02035 , H01L21/02087 , H01L21/0209 , H01L21/30604 , H01L21/32134 , H01L21/67028 , H01L21/67109 , H01L21/68792
摘要： It is an object to reduce a chemical treating width in a peripheral edge part of a substrate while suppressing deterioration in each of uniformity of the chemical treating width and processing efficiency. In order to achieve the object, a substrate processing device for carrying out a chemical treatment for a substrate using a processing liquid having a reaction rate increased with a rise in temperature includes a substrate holding portion, a rotating portion for rotating the substrate held in the substrate holding portion in a substantially horizontal plane, a heating portion for injecting heating steam to a central part of a lower surface of the substrate to entirely heat the substrate, and a peripheral edge processing portion for supplying the processing liquid from above to a peripheral edge part of the substrate heated by the heating portion, thereby carrying out a chemical treatment for the peripheral edge part.

7. 发明申请

US20170263737A1 SEMICONDUCTOR DEVICES WITH CAVITIES 审中-公开
公开(公告)号：US20170263737A1
公开(公告)日：2017-09-14
申请号：US15601905
申请日：2017-05-22
申请人： Great Wall Semiconductor Corporation
发明人： Patrick M. Shea
IPC分类号： H01L29/739 , H01L29/06 , H01L29/78 , H01L29/66 , H01L23/544 , H01L21/8234 , H01L21/02
CPC分类号： H01L21/187 , H01L21/02035 , H01L21/185 , H01L21/2007 , H01L21/7624 , H01L21/823418 , H01L21/823481 , H01L23/544 , H01L29/0634 , H01L29/0661 , H01L29/0696 , H01L29/0882 , H01L29/4175 , H01L29/66681 , H01L29/66734 , H01L29/7395 , H01L29/7396 , H01L29/7813 , H01L29/7816 , H01L33/0079 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises a first semiconductor wafer including a cavity formed in the first semiconductor die. A second semiconductor die is bonded to the first semiconductor die over the cavity. A first transistor includes a portion of the first transistor formed over the cavity.

8. 发明授权

US09548378B2 Epitaxial channel formation methods and structures 有权
标题翻译：外延通道形成方法和结构
公开(公告)号：US09548378B2
公开(公告)日：2017-01-17
申请号：US13369856
申请日：2012-02-09
申请人： Stephan Kronholz , Nadja Zakowsky , Yew Tuck Chow
发明人： Stephan Kronholz , Nadja Zakowsky , Yew Tuck Chow
IPC分类号： H01L21/20 , H01L29/66 , H01L29/78 , H01L29/10 , H01L21/02
CPC分类号： H01L29/66651 , H01L21/02035 , H01L21/0243 , H01L21/0245 , H01L21/02532 , H01L21/02617 , H01L29/1054 , H01L29/7833
摘要： A method for forming field effect transistors (FETs) in a multiple wafers per batch epi-reactor includes, providing substrates having therein at least one semiconductor (SC) region with a substantially flat outer surface, modifying such substantially flat outer surface to form a convex-outward curved surface, forming an epitaxial semiconductor layer on the curved surface, and incorporating the epitaxial layer in a field effect transistor formed on the substrate. Where the SC region is of silicon, the epitaxial layer can include silicon-germanium. In a preferred embodiment, the epi-layer forms part of the FET channel. Because of the convex-outward curved surface, the epi-layer grown thereon has much more uniform thickness even when formed in a high volume reactor holding as many as 100 or more substrates per batch. FETs with much more uniform properties are obtained, thereby greatly increasing the manufacturing yield and reducing the cost.
摘要翻译：在每个批处理反应器的多个晶片中形成场效应晶体管（FET）的方法包括：在其中提供具有至少一个具有基本上平坦的外表面的至少一个半导体（SC）区域的衬底，修改该基本平坦的外表面以形成凸在曲面上形成外延半导体层，并且在形成在基板上的场效应晶体管中并入外延层。当SC区域是硅时，外延层可以包括硅 - 锗。在优选实施例中，外延层形成FET通道的一部分。由于凸向外弯曲的表面，即使在每批容纳多达100个或更多个基底的高体积反应器中形成时，其上生长的外延层也具有更均匀的厚度。获得具有更均匀性能的FET，从而大大提高制造成品率并降低成本。

9. 发明授权

US09390906B1 Method for creating asymmetrical wafer 有权
标题翻译：创建不对称晶片的方法
公开(公告)号：US09390906B1
公开(公告)日：2016-07-12
申请号：US14073602
申请日：2013-11-06
申请人： Rubicon Technology, Inc.
发明人： Michael W. Matthews , Sunil B. Phatak
IPC分类号： H01L29/04 , H01L21/02
CPC分类号： H01L21/02035 , H01L21/02013 , H01L21/02021 , H01L21/02024 , H01L23/544 , H01L29/0657 , H01L2223/54426 , H01L2223/54493 , H01L2924/0002 , Y10T428/21 , Y10T428/219 , H01L2924/00
摘要： The present invention consists of a method for imparting asymmetry to a truncated annular wafer by either rounding one corner of the orientation flat, or rounding one corner of a notch. This novel method of rounding corners impart a visual and/or tactile asymmetry which can be utilized by a person in order to differentiate between the two different sides of the wafer. This inventive wafer design and method for making an asymmetric wafer is especially useful in the field of semiconductor technology and may be used on sapphire crystal wafers or any other class of wafer.
摘要翻译：本发明包括一种用于通过使取向平面的一个角的圆角或切口的一个角的四舍五入来赋予截头圆环的不对称性的方法。舍入角的这种新颖的方法赋予人可以利用的视觉和/或触觉不对称性，以便区分晶片的两个不同侧面。用于制造不对称晶片的本发明的晶片设计和方法在半导体技术领域中特别有用，并且可以用于蓝宝石晶体晶片或任何其他类别的晶片。

10. 发明申请

US20150132926A1 PROCESS FOR LARGE-SCALE AMMONOTHERMAL MANUFACTURING OF GALLIUM NITRIDE BOULES 审中-公开
标题翻译：大型氮化镓玻璃制品的大规模制造工艺
公开(公告)号：US20150132926A1
公开(公告)日：2015-05-14
申请号：US14599335
申请日：2015-01-16
申请人： SORAA, INC.
发明人： MARK P. D'EVELYN , DIRK EHRENTRAUT , DERRICK S. KAMBER , BRADLEY C. DOWNEY
IPC分类号： C30B7/10 , H01L21/02 , C30B29/40
CPC分类号： C30B7/105 , B01J3/008 , B01J3/042 , B01J3/065 , B01J2203/0665 , B01J2203/068 , B30B11/002 , C30B29/406 , H01L21/02035 , H01L21/02389
摘要： Large-scale manufacturing of gallium nitride boules using m-plane or wedge-shaped seed crystals can be accomplished using ammonothermal growth methods. Large-area single crystal seed plates are suspended in a rack, placed in a large diameter autoclave or internally-heated high pressure apparatus along with ammonia and a mineralizer, and crystals are grown ammonothermally. The orientation of the m-plane or wedge-shaped seed crystals are chosen to provide efficient utilization of the seed plates and of the volume inside the autoclave or high pressure apparatus.
摘要翻译：使用m-平面或楔形晶种进行大规模制造氮化镓颗粒可以使用氨热生长方法进行。将大面积单晶种子板悬挂在机架中，与氨和矿化剂一起放置在大直径的高压釜或内部加热的高压装置中，并将水晶进行氨水生长。选择m平面或楔形晶种的取向以提供有效利用种子板和高压釜或高压装置内的体积。

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