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81. 发明申请

US20080204093A1 Multiphase generator with duty-cycle correction using dual-edge phase detection and method for generating a multiphase signal 有权
标题翻译：使用双边相位检测的占空比校正的多相发生器和用于产生多相信号的方法
公开(公告)号：US20080204093A1
公开(公告)日：2008-08-28
申请号：US11712162
申请日：2007-02-28
申请人： Feng Lin , Roman Andreas Royer
发明人： Feng Lin , Roman Andreas Royer
IPC分类号： H03H11/26 , H03L7/07
CPC分类号： G06F1/10 , H03K5/133 , H03L7/0805 , H03L7/0812 , H03L7/085
摘要： Embodiments of a multiphase generator with duty-cycle correction are generally described herein. In some embodiments, the multiphase generator comprises controllable delay stages arranged in series and dual-edge phase detector circuitry. The dual-edge phase detector circuitry may generate a control signal to adjust the delay provided by the delay stages based on corresponding rising edges and corresponding falling edges of same-state signals operated on by the delay stages. Other circuits, systems, and methods are described.
摘要翻译：这里通常描述具有占空比校正的多相发生器的实施例。在一些实施例中，多相发生器包括串联布置的可控延迟级和双边缘相位检测器电路。双边缘相位检测器电路可以产生控制信号，以基于由延迟级操作的相同状态信号的相应上升沿和相应的下降沿来调整由延迟级提供的延迟。描述其他电路，系统和方法。

82. 发明申请

US20080174350A1 DLL circuit and method of controlling the same 有权
标题翻译： DLL电路及其控制方法
公开(公告)号：US20080174350A1
公开(公告)日：2008-07-24
申请号：US11826401
申请日：2007-07-16
申请人： Dong Suk Shin , Hyun Woo Lee , Won Joo Yun
发明人： Dong Suk Shin , Hyun Woo Lee , Won Joo Yun
IPC分类号： H03L7/08 , H03K5/14 , H03L7/07
CPC分类号： H03K5/133 , H03K5/1565 , H03K2005/00052 , H03K2005/00065 , H03L7/0814 , H03L7/087
摘要： A DLL circuit includes a duty ratio detection unit that detects a duty ratio of a rising clock and a duty ratio of a falling clock, thereby outputting a duty ratio detection signal. A correction control unit generates a correction control signal in response to the duty ratio detection signal. A duty ratio correction unit corrects a duty ratio of an internal. clock in response to the correction control signal, thereby outputting a reference clock.
摘要翻译： DLL电路包括占空比检测单元，其检测上升时钟的占空比和下降时钟的占空比，从而输出占空比检测信号。校正控制单元响应于占空比检测信号产生校正控制信号。占空比校正单元校正内部的占空比。响应于校正控制信号，从而输出参考时钟。

83. 发明授权

US07388437B2 System and method for tuning a frequency synthesizer 有权
标题翻译：用于调谐频率合成器的系统和方法
公开(公告)号：US07388437B2
公开(公告)日：2008-06-17
申请号：US11325781
申请日：2006-01-04
申请人： Buddhika J. Abesingha , Timothy M. Magnusen , Jan-Michael Stevenson , Robert A. Greene
发明人： Buddhika J. Abesingha , Timothy M. Magnusen , Jan-Michael Stevenson , Robert A. Greene
IPC分类号： H03L7/07 , H03L7/097
CPC分类号： H03L7/18 , H03L7/0891 , H03L7/099 , H03L7/113
摘要： An apparatus for generating an output signal having a particular frequency includes an oscillator, a first tuning module, and a second tuning module. The oscillator generates an output signal associated with an output frequency. When coupled to the oscillator, the first tuning module is capable of inducing, within a first amount of time, a change in the output frequency of a particular magnitude. When coupled to the oscillator, the second tuning module is capable of inducing, within a second amount of time, a change in the output frequency of the same magnitude. The second amount of time is greater than the first amount of time. The selector couples a selected one of the first tuning module and the second tuning module to the oscillator based on a difference between a frequency-divided version of the output signal and a reference signal.
摘要翻译：用于产生具有特定频率的输出信号的装置包括振荡器，第一调谐模块和第二调谐模块。振荡器产生与输出频率相关联的输出信号。当耦合到振荡器时，第一调谐模块能够在第一时间内引起特定幅度的输出频率的变化。当耦合到振荡器时，第二调谐模块能够在第二时间内引起相同幅度的输出频率的变化。第二个时间量大于第一个时间量。选择器基于输出信号的分频版本与参考信号之间的差异将第一调谐模块和第二调谐模块中的选定的一个耦合到振荡器。

84. 发明申请

US20050286505A1 Method and apparatus for generating a phase dependent control signal 失效
公开(公告)号：US20050286505A1
公开(公告)日：2005-12-29
申请号：US11203511
申请日：2005-08-12
申请人： Ronnie Harrison
发明人： Ronnie Harrison
IPC分类号： G11C7/10 , H03D13/00 , H03K5/13 , H03K5/135 , H03L7/07 , H03L7/081 , H03L7/085 , H03L7/087 , H03L7/089 , H04L12/50
CPC分类号： G11C7/1072 , G11C7/222 , H03D13/004 , H03K5/131 , H03K5/133 , H03K5/135 , H03L7/07 , H03L7/0812 , H03L7/085 , H03L7/087 , H03L7/0896
摘要： A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select signals having duty cycles corresponding to the phase relationship between the clock edges of the first and second clock signals. The phase detector also includes a charge pump that receives select signals from the phase detector circuits and produces an increasing or decreasing control signal when the first and second clock signals do not have the predetermined phase relationship, and a non-varying control signal when the first and second clock signals do have the predetermined phase relationship. The control signal may be used to adjust the delay value of a voltage-controlled delay circuit in order to adjust the phase relationship between the first and second clock signals to have a predetermined phase relationship.

85. 发明申请

US20050280407A1 Delay-locked loop and a method of testing a delay-locked loop 有权
标题翻译：延迟锁定环路和测试延迟锁定环路的方法
公开(公告)号：US20050280407A1
公开(公告)日：2005-12-22
申请号：US10869582
申请日：2004-06-16
申请人： Alvin Loke , Michael Joseph Gilsdorf , Peter Meier , Jeffrey R. Rearick
发明人： Alvin Loke , Michael Joseph Gilsdorf , Peter Meier , Jeffrey R. Rearick
IPC分类号： G01R23/175 , H03L7/06 , H03L7/07 , H03L7/081
CPC分类号： H03L7/07 , H03L7/0812
摘要： A delay-locked loop (DLL) of an integrated circuit (IC) with testing circuitry and a method for testing a DLL. During test mode, a phase comparator of the DLL receives a test clock in place of the reference clock and determines the phase difference between the test clock and the clock fed back to the DLL from a clock buffer tree. A variable delay element of the DLL then shifts the reference clock in time by an amount that depends on that phase difference. The variable delay element can be exercised by varying the phase of the test clock with respect to the reference clock by a known phase offset to cause the variable delay element to produce a range of delays. Whether the variable delay element is functioning properly can be determined by checking whether the phase of the test clock is aligned with the phase of the feedback clock.
摘要翻译：具有测试电路的集成电路（IC）的延迟锁定环（DLL）和用于测试DLL的方法。在测试模式期间，DLL的相位比较器代替参考时钟接收测试时钟，并从时钟缓冲器树中确定测试时钟与反馈到DLL的时钟之间的相位差。然后，DLL的可变延迟元件将参考时钟在时间上移动取决于该相位差的量。可以通过将测试时钟相对于参考时钟的相位改变已知的相位偏移来使可变延迟元件产生延迟范围来实现可变延迟元件。可以通过检查测试时钟的相位是否与反馈时钟的相位对准来确定可变延迟元件是否正常工作。

86. 发明申请

US20050249028A1 Method and apparatus for generating a sequence of clock signals 失效
公开(公告)号：US20050249028A1
公开(公告)日：2005-11-10
申请号：US11182965
申请日：2005-07-15
申请人： Ronnie Harrison
发明人： Ronnie Harrison
IPC分类号： G11C7/22 , G11C8/00 , G11C11/4076 , H03L7/07 , H03L7/081 , H03L7/089
CPC分类号： G11C7/22 , G11C7/1078 , G11C7/109 , G11C7/222 , G11C8/08 , G11C8/10 , G11C11/4076 , G11C11/4093 , H03L7/07 , H03L7/0812 , H03L7/0891
摘要： A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that delays a reference clock applied to its input by a plurality of respective delays. Two of the clock signals in the sequence are applied to a phase detector so that the signals at the outputs of the delay line have predetermined phases relative to each other. The outer delay-locked loop is formed by a voltage controlled delay circuit that delays the command clock by a voltage controlled delay to provide the reference clock to the delay line of the inner delay-locked loop. The outer delay-locked loop also includes a phase detector that compares the command clock to one of the clock signals in the sequence generated by the delay line. The outer delay-locked loop thus locks one of the clock signals in the sequence to the command clock. As a result, all of the clock signals in the sequence generated by the delay line have respective predetermined phases relative to the phase of the command clock. One of the clock signals in the sequence is selected by a multiplexer to clock a command data latch at a time corresponding to the delay in coupling a command data bit to the latch.

87. 发明申请

US20050242855A1 Delay locked loop circuit 审中-公开
标题翻译：延时锁定回路电路
公开(公告)号：US20050242855A1
公开(公告)日：2005-11-03
申请号：US11086054
申请日：2005-03-22
申请人： Joong Ho Lee
发明人： Joong Ho Lee
IPC分类号： G11C8/00 , H03L7/06 , H03L7/07 , H03L7/081
CPC分类号： H03L7/07 , H03L7/0814 , H03L7/0818
摘要： Disclosed is a delay locked loop circuit (DLL) used for DDR SDRAM. The DLL provides a fast locking function. In particular, the DLL detects the level of a frequency and performs the fast locking function, thereby realizing a high integrated memory device having a reduced area of a delay part used in order to synchronize a phase of an external clock signal with a phase of an internal clock.
摘要翻译：公开了用于DDR SDRAM的延迟锁定环电路（DLL）。 DLL提供快速锁定功能。特别地，DLL检测频率的电平并执行快速锁定功能，从而实现具有减小的延迟部分的面积的高集成存储器件，以使外部时钟信号的相位与内部时钟

88. 发明授权

US06959016B1 Method and apparatus for adjusting the timing of signals over fine and coarse ranges 失效
标题翻译：用于在精细和粗略范围内调整信号定时的方法和装置
公开(公告)号：US06959016B1
公开(公告)日：2005-10-25
申请号：US09633552
申请日：2000-08-07
申请人： Brent Keeth , Troy A. Manning
发明人： Brent Keeth , Troy A. Manning
IPC分类号： G06F1/10 , G11C7/22 , H03K5/13 , H03L7/07 , H03L7/081 , H04J3/06
CPC分类号： G06F1/10 , G11C7/22 , G11C2207/2281 , G11C2207/229 , H03K5/131 , H03L7/07 , H03L7/0812
摘要： A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments with respect to an input clock signal. The coarse delay circuit adjusts the timing of a digital signal in relatively large phase increments. The delayed clock signal is used to clock a register to which the digital signal is applied to control the timing a the digital signal clocked through the register responsive to adjusting the timing of the fine delay circuit and the coarse delay circuit. The timing relationship is initially adjusted by altering the delay of the fine delay circuit. Whenever the maximum or minimum delay of the fine delay circuit is reached, the coarse delay circuit is adjusted. The variable delay circuit may be used in a memory device to control the timing at which read data is applied to the data bus of the memory device. The fine delay circuit includes a multi—tapped delay line coupled to a multiplexer that selects one of the taps for use in generating the delayed clock. When the first or last tap is selected, the timing of the coarse delay circuit is adjusted. The coarse delay circuit includes a counter that generates the digital signal upon counting from an initial count to the terminal count. The coarse delay circuit is adjusted by adjusting the initial count of the counter.
摘要翻译：可变延迟电路由精细延迟电路和粗略延迟电路构成。精细延迟电路相对于输入时钟信号以相对小的相位增量调整延迟时钟信号的延迟。粗延迟电路以相对大的相位增量来调整数字信号的定时。延迟时钟信号用于对应用数字信号的寄存器进行时钟，以响应于调整精细延迟电路和粗略延迟电路的定时来控制通过寄存器定时的数字信号的定时。最初通过改变精细延迟电路的延迟来调整定时关系。每当达到精细延迟电路的最大或最小延迟时，调整粗略延迟电路。可变延迟电路可以用于存储器件中以控制将读取数据应用于存储器件的数据总线的定时。精细延迟电路包括耦合到多路复用器的多抽头延迟线，其选择一个抽头用于产生延迟的时钟。当选择第一或最后一个抽头时，调整粗延迟电路的定时。粗延迟电路包括从初始计数到终端计数的计数时产生数字信号的计数器。通过调整计数器的初始计数来调整粗略延迟电路。

89. 发明授权

US06956415B2 Modular DLL architecture for generating multiple timings 失效
标题翻译：用于生成多个时序的模块化DLL体系结构
公开(公告)号：US06956415B2
公开(公告)日：2005-10-18
申请号：US10707067
申请日：2003-11-19
申请人： Darren L. Anand , Kevin W. Gorman
发明人： Darren L. Anand , Kevin W. Gorman
IPC分类号： G06F1/04 , G11C7/22 , G11C11/407 , H03L7/00 , H03L7/06 , H03L7/07 , H03L7/08 , H03L7/081 , H03L7/16
CPC分类号： H03L7/07 , G11C7/22 , G11C7/222 , H03L7/0814
摘要： A modular Digital Locked Loop (DLL) architecture capable of generating a plurality of multiple phase clock signals, having particular applicability to synchronization of embedded DRAM systems with on chip timing. The architecture comprises a single core frequency locking circuit that includes a delay element with control logic and locking circuitry capable of locking the DLL system clock frequency to an external reference clock, and a plurality of secondary phase locking circuits capable of synchronizing a plurality of internal clock signals to any phase of the external reference clock.
摘要翻译：一种能够产生多个多相时钟信号的模块化数字锁定环（DLL）架构，其特别适用于具有片上定时的嵌入式DRAM系统的同步。该架构包括单核频率锁定电路，其包括具有控制逻辑的延迟元件和能够将DLL系统时钟频率锁定到外部参考时钟的锁定电路，以及能够使多个内部时钟同步的多个次级锁相电路信号到外部参考时钟的任何相位。

90. 发明授权

US06954110B2 Replica cell for ring oscillator 失效
公开(公告)号：US06954110B2
公开(公告)日：2005-10-11
申请号：US10648919
申请日：2003-08-27
申请人： Shenggao Li
发明人： Shenggao Li
IPC分类号： H03K3/011 , H03K3/03 , H03L7/07 , H03L7/099 , H03L7/00
CPC分类号： H03K3/0322 , H03K3/011 , H03L7/07 , H03L7/0995
摘要： In some embodiments, a ring oscillator includes a plurality of delay cells coupled in series as a ring, and a replica cell coupled to the delay cells to provide at least one bias signal to the delay cells. The replica cell includes a differential transistor pair formed of a first transistor and a second transistor. The first transistor has a drain terminal and a gate terminal coupled to the drain terminal. The second transistor has a drain terminal and a gate terminal coupled to the drain terminal of the second transistor.

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