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1. 发明授权

US08716063B2 Wafer level chip scale package and process of manufacture 有权
标题翻译：晶圆级芯片级封装及制造工艺
公开(公告)号：US08716063B2
公开(公告)日：2014-05-06
申请号：US13007356
申请日：2011-01-14
申请人： Tao Feng , François Hébert , Ming Sun , Yueh-Se Ho
发明人： Tao Feng , François Hébert , Ming Sun , Yueh-Se Ho
IPC分类号： H01L21/00
CPC分类号： H01L29/7827 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/81 , H01L29/0657 , H01L29/41741 , H01L29/4175 , H01L29/45 , H01L29/49 , H01L29/7802 , H01L2224/02371 , H01L2224/03464 , H01L2224/0347 , H01L2224/0401 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06181 , H01L2224/06183 , H01L2224/16225 , H01L2224/16227 , H01L2224/81815 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.
摘要翻译：封装了功率晶圆级芯片级封装（CSP）和制造工艺。功率晶片级芯片级封装包括位于器件一侧的所有源极，栅极和漏极，便于用焊膏安装到印刷电路板（PCB）。

2. 发明授权

US08236653B2 Configuration and method to form MOSFET devices with low resistance silicide gate and mesa contact regions 有权
标题翻译：用于形成具有低电阻硅化物栅极和台面接触区域的MOSFET器件的配置和方法
公开(公告)号：US08236653B2
公开(公告)日：2012-08-07
申请号：US13361950
申请日：2012-01-31
申请人： Yongzhong Hu , Sung-Shan Tai
发明人： Yongzhong Hu , Sung-Shan Tai
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66734
摘要： A novel integration scheme for forming power MOSFET, particularly forming salicided layers for both gate contact regions and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicided layers.
摘要翻译：一种用于形成功率MOSFET的新颖的集成方案，特别是形成用于两个栅极接触区域和台面接触区域的浸渍层，以及使用多个能量接触植入物通过该水浸层形成导电体接触物，该接触体通过浸渍层。

3. 发明授权

US08124453B2 Vertically packaged MOSFET and IC power devices as integrated module using 3D interconnected laminates 有权
标题翻译：垂直封装的MOSFET和IC功率器件作为使用3D互连层压板的集成模块
公开(公告)号：US08124453B2
公开(公告)日：2012-02-28
申请号：US12927172
申请日：2010-11-08
申请人： Ming Sun , Yueh Se Ho
发明人： Ming Sun , Yueh Se Ho
IPC分类号： H01L23/02
CPC分类号： H01L23/5389 , H01L23/3677 , H01L23/49816 , H01L23/49844 , H01L24/48 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An electronic package for containing at least a top packaging module vertically stacked on a bottom packaging module. Each of the packaging modules includes a semiconductor chip packaged and connected by via connectors and connectors disposed on a laminated board fabricated with a standard printed-circuit board process wherein the top and bottom packaging module further configured as a surface mountable modules for conveniently stacking and mounting to prearranged electrical contacts without using a leadframe. At least one of the top and bottom packaging modules is a multi-chip module (MCM) containing at least two semiconductor chips. At least one of the top and bottom packaging modules includes a ball grid array (BGA) for surface mounting onto the prearranged electrical contacts. At least one of the top and bottom packaging modules includes a plurality of solder bumps on one of the semiconductor chips for surface mounting onto the prearranged electrical contacts. The laminated board of the bottom packaging modules further has a thermal expansion coefficient substantially the same as a printed circuit board (PCB) whereby a surface mount onto the PCB is less impacted by a temperature change.
摘要翻译：一种用于至少包含垂直堆叠在底部包装模块上的顶部包装模块的电子包装。每个封装模块包括通过通孔连接器和连接器连接的半导体芯片，该连接器和连接器设置在由标准印刷电路板工艺制造的层压板上，其中顶部和底部封装模块还被配置为便于堆叠和安装的表面可安装模块以预先布置的电触点，而不使用引线框架。顶部和底部封装模块中的至少一个是包含至少两个半导体芯片的多芯片模块（MCM）。顶部和底部封装模块中的至少一个包括用于表面安装到预先布置的电触点上的球栅阵列（BGA）。顶部和底部封装模块中的至少一个包括在半导体芯片之一上的多个焊料凸块，用于表面安装到预先布置的电触点上。底部包装模块的层压板还具有与印刷电路板（PCB）基本相同的热膨胀系数，由此PCB上的表面安装件较少受到温度变化的影响。

4. 发明授权

US08120887B2 MOS transistor triggered transient voltage suppressor to provide circuit protection at a lower voltage 有权
标题翻译： MOS晶体管触发瞬态电压抑制器以在较低电压下提供电路保护
公开(公告)号：US08120887B2
公开(公告)日：2012-02-21
申请号：US11712317
申请日：2007-02-28
申请人： Shekar Mallikararjunaswamy , Madhur Bobde
发明人： Shekar Mallikararjunaswamy , Madhur Bobde
IPC分类号： H02H3/22 , H02H9/00
CPC分类号： H01L27/0262 , Y10T29/49002
摘要： An electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering MOS transistor connected between an emitter and a collector of a first bipolar-junction transistor (BJT) coupled to a second BJT to form a SCR functioning as a main clamp circuit of the TVS circuit. The TVS circuit further includes a triggering circuit for generating a triggering signal for the triggering MOS transistor wherein the triggering circuit includes multiple stacked MOS transistors for turning into a conductive state by a transient voltage while maintaining a low leakage current.
摘要翻译：一种形成为集成电路（IC）的电子设备，其中电子设备还包括瞬态电压抑制（TVS）电路。 TVS电路包括连接在与第二BJT耦合的第一双极结晶体管（BJT）的发射极和集电极之间的触发MOS晶体管，以形成用作TVS电路的主钳位电路的SCR。 TVS电路还包括用于产生用于触发MOS晶体管的触发信号的触发电路，其中触发电路包括多个堆叠的MOS晶体管，用于在保持低泄漏电流的同时通过瞬态电压转为导通状态。

5. 发明授权

US08089139B2 Small outline package in which MOSFET and Schottky diode being co-packaged 有权
标题翻译： MOSFET和肖特基二极管共同封装的小外形封装
公开(公告)号：US08089139B2
公开(公告)日：2012-01-03
申请号：US11792010
申请日：2005-10-09
申请人： Zhengyu Shi , Limin Wang , Lei Shi
发明人： Zhengyu Shi , Limin Wang , Lei Shi
IPC分类号： H01L23/495
CPC分类号： H01L23/49562 , H01L23/49575 , H01L25/165 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A TSOP (Thin Small Outline Package) contains a MOSFET and a Schottky diode. The MOSFET has a source terminal a gate terminal and a drain terminal. The Schottky diode has a cathode terminal, a anode terminal. The TSOP contains the MOSFET and the Schottky diode with a special configuration by placing the drain terminal of the MOSFET and the anode terminal of the Schottky diode on a same side. Specifically, the TSOP implements a leadframe that comprises a plurality of leads. The drain terminal of the MOSFET and the anode terminal extends outside of the TSOP separate on the same side of the package.
摘要翻译： TSOP（Thin Small Outline Package）包含一个MOSFET和一个肖特基二极管。 MOSFET具有源极端子，栅极端子和漏极端子。肖特基二极管具有阴极端子，阳极端子。通过将MOSFET的漏极端子和肖特基二极管的阳极端子放在同一侧，TSOP包含具有特殊配置的MOSFET和肖特基二极管。具体地说，TSOP实现了包括多个引线的引线框架。 MOSFET的漏极端子和阳极端子在封装的同一侧分开延伸到TSOP的外部。

6. 发明授权

US08053298B2 Planar split-gate high-performance MOSFET structure and manufacturing method 有权
标题翻译：平面分闸高性能MOSFET结构及制造方法
公开(公告)号：US08053298B2
公开(公告)日：2011-11-08
申请号：US12381813
申请日：2009-03-16
申请人： Anup Bhalla , Francois Hebert , Daniel S. Ng
发明人： Anup Bhalla , Francois Hebert , Daniel S. Ng
IPC分类号： H01L21/337
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/42372 , H01L29/42376 , H01L29/66712 , H01L29/7828
摘要： This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device. The transistor cell further includes a shallow surface doped regions disposed near a top surface of the drift layer under the gate adjacent to the JFET diffusion region wherein the shallow surface doped region having a dopant concentration lower than the JFET diffusion region and higher than the drift layer.
摘要翻译：本发明公开了一种改进的半导体功率器件，包括多个功率晶体管单元，其中每个单元还包括由设置在构成半导体衬底的上层的漂移层的顶部上的栅极氧化物层填充的平面栅极，其中平面栅极进一步构成分闸门，其包括在栅极层中开口的间隙，由此栅极的总表面积减小。晶体管单元还包括设置在栅极层间隙之下的漂移层中的JFET（结场效应晶体管）扩散区，其中具有比漂移区更高的掺杂浓度的JFET扩散区用于降低半导体功率的沟道电阻设备。晶体管单元还包括在邻近JFET扩散区的栅极附近设置在漂移层的顶表面附近的浅表面掺杂区，其中掺杂浓度低于JFET扩散区并且高于漂移层的浅表面掺杂区。

7. 发明授权

US08035159B2 Device structure and manufacturing method using HDP deposited source-body implant block 有权
标题翻译：使用HDP沉积源体植入块的装置结构和制造方法
公开(公告)号：US08035159B2
公开(公告)日：2011-10-11
申请号：US11796985
申请日：2007-04-30
申请人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K Lui
发明人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K Lui
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/407 , H01L29/42368 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
摘要翻译：本发明公开了一种半导体功率器件。沟槽半导体功率器件包括从半导体衬底的顶表面开口的沟槽栅极，被包围在设置在衬底底表面上的漏区以上的顶表面附近的体区中的源极区围绕。所述半导体功率器件还包括植入离子块，所述植入离子块设置在所述身体区域旁边的台面区域的上表面上，所述植入离子块具有基本上大于0.3微米的厚度，用于阻挡体注入离子和源离子进入台面区域从而可以减少用于制造半导体功率器件的掩模。

8. 发明申请

US20110227155A1 INTEGRATION OF A SENSE FET INTO A DISCRETE POWER MOSFET 有权
标题翻译：将感测FET集成到分立功率MOSFET中
公开(公告)号：US20110227155A1
公开(公告)日：2011-09-22
申请号：US13149051
申请日：2011-05-31
申请人： Yi Su , Anup Bhalla , Daniel Ng
发明人： Yi Su , Anup Bhalla , Daniel Ng
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/8234 , H01L27/088 , H01L29/0646 , H01L29/0653 , H01L29/0696 , H01L29/66734 , H01L29/7815 , H01L2224/0603 , H01L2924/13091 , H01L2924/00
摘要： A main FET and one or more sense FETs are formed in a common substrate. The main FET and sense FET(s) include a source terminal, a gate terminal and a drain terminal. The common gate pad connects the gate terminals of the main FET and sense FET(s). An electrical isolation may be between the gate terminals of the main FET and the sense FET(s). A sense pad in electrical contact with the source of the one or more sense FETs does not overlap an area of the device containing the sense FET(s). It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：主FET和一个或多个感测FET形成在公共衬底中。主FET和感测FET包括源极端子，栅极端子和漏极端子。公共栅极焊盘连接主FET和检测FET的栅极端子。电隔离可以在主FET的栅极端子和感测FET之间。与一个或多个感测FET的源极电接触的感测焊盘不与包含感测FET的器件的区域重叠。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

9. 发明授权

US08021563B2 Etch depth determination for SGT technology 有权
标题翻译：蚀刻深度测定SGT技术
公开(公告)号：US08021563B2
公开(公告)日：2011-09-20
申请号：US11690546
申请日：2007-03-23
申请人： Yingying Lou , Tiesheng Li , Yu Wang , Anup Bhalla
发明人： Yingying Lou , Tiesheng Li , Yu Wang , Anup Bhalla
IPC分类号： H01L21/302
CPC分类号： H01L22/12 , H01L29/407 , H01L29/66734 , H01L2924/0002 , H01L2924/00
摘要： A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the layer of material. The resist mask does not cover the trench. The layer of material is isotropically etched. An etch depth may be determined from a characteristic of etching of the material underneath the mask. Such a method may be used for forming SGT structures. The wafer may comprise a layer of material disposed on at least a portion of a surface of semiconductor wafer; a resist mask comprising an angle-shaped test portion disposed over a portion of the layer of material; and a ruler marking on the surface of the substrate proximate the test portion.
摘要翻译：公开了一种用于确定深度蚀刻的方法，形成屏蔽栅沟槽（SGT）结构的方法和半导体器件晶片。在具有沟槽的衬底的一部分上形成材料层。材料填充沟槽。抗蚀剂掩模放置在材料层的测试部分上。抗蚀剂掩模不覆盖沟槽。材料层被各向同性地蚀刻。可以根据掩模下面的材料的蚀刻特性确定蚀刻深度。这种方法可用于形成SGT结构。晶片可以包括设置在半导体晶片的表面的至少一部分上的材料层; 抗蚀剂掩模，其包括设置在所述材料层的一部分上的角形测试部分; 以及在靠近测试部分的基板的表面上标记的标尺。

10. 发明授权

US08008747B2 High power and high temperature semiconductor power devices protected by non-uniform ballasted sources 有权
标题翻译：由不均匀的压载源保护的大功率和高温半导体功率器件
公开(公告)号：US08008747B2
公开(公告)日：2011-08-30
申请号：US12074087
申请日：2008-02-28
申请人： François Hébert , Anup Bhalla
发明人： François Hébert , Anup Bhalla
IPC分类号： H01L29/66
CPC分类号： H01L29/7802 , H01L24/05 , H01L29/0696 , H01L29/086 , H01L29/41741 , H01L29/41775 , H01L29/456 , H01L29/7803 , H01L2224/0603 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/00
摘要： This invention discloses a semiconductor power device disposed on a semiconductor substrate supporting an epitaxial layer as a drift region composed of an epitaxial layer. The semiconductor power device further includes a super-junction structure includes a plurality of doped sidewall columns disposed in a multiple of epitaxial layers. The epitaxial layer have a plurality of trenches opened and filled with the multiple epitaxial layer therein with the doped columns disposed along sidewalls of the trenches disposed in the multiple of epitaxial layers.
摘要翻译：本发明公开了一种半导体功率器件，其设置在支撑外延层的半导体衬底上，作为由外延层构成的漂移区。半导体功率器件还包括超结结构，其包括设置在多个外延层中的多个掺杂侧壁。外延层具有多个沟槽，其中多个外延层开放并填充，其中掺杂的列沿着设置在多个外延层中的沟槽的侧壁设置。

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