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1. 发明授权

US10468526B2 Self-aligned slotted accumulation-mode field effect transistor (ACCUFET) structure and method 有权
公开(公告)号：US10468526B2
公开(公告)日：2019-11-05
申请号：US15836756
申请日：2017-12-08
申请人： François Hébert , Madhur Bobde , Anup Bhalla
发明人： François Hébert , Madhur Bobde , Anup Bhalla
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L21/265 , H01L29/417 , H01L29/45 , H01L29/47 , H01L29/08
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.

2. 发明申请

US20180102435A1 SELF-ALIGNED SLOTTED ACCUMULATION-MODE FIELD EFFECT TRANSISTOR (ACCUFET) STRUCTURE AND METHOD 审中-公开
公开(公告)号：US20180102435A1
公开(公告)日：2018-04-12
申请号：US15836756
申请日：2017-12-08
申请人： François Hébert , Madjur Bobde , Anup Bhalla
发明人： François Hébert , Madjur Bobde , Anup Bhalla
IPC分类号： H01L29/78 , H01L29/06
CPC分类号： H01L29/7828 , H01L21/26586 , H01L29/0619 , H01L29/0623 , H01L29/0847 , H01L29/41766 , H01L29/456 , H01L29/47 , H01L29/66666 , H01L29/7806
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.

3. 发明申请

US20170288034A1 DEVICE STRUCTURE AND MANUFACTURING METHOD USING HDP DEPOSITED SOURCE-BODY IMPLANT BLOCK 审中-公开
公开(公告)号：US20170288034A1
公开(公告)日：2017-10-05
申请号：US15499487
申请日：2017-04-27
申请人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K. Lui
发明人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K. Lui
IPC分类号： H01L29/423 , H01L29/06 , H01L29/40 , H01L27/088
CPC分类号： H01L29/42368 , H01L27/088 , H01L29/0619 , H01L29/401 , H01L29/4236
摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

4. 发明申请

US20160099351A1 SELF-ALIGNED SLOTTED ACCUMULATION-MODE FIELD EFFECT TRANSISTOR (ACCUFET) STRUCTURE AND METHOD 审中-公开
标题翻译：自对准插图累积模式场效应晶体管（ACCUFET）结构与方法
公开(公告)号：US20160099351A1
公开(公告)日：2016-04-07
申请号：US14507311
申请日：2014-10-06
申请人： François Hébert , Madhur Bobde , Anup Bhalla
发明人： François Hébert , Madhur Bobde , Anup Bhalla
IPC分类号： H01L29/78 , H01L29/423 , H01L21/28 , H01L29/66
CPC分类号： H01L29/7828 , H01L21/26586 , H01L29/0619 , H01L29/0623 , H01L29/0847 , H01L29/41766 , H01L29/456 , H01L29/47 , H01L29/66666 , H01L29/7806
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.
摘要翻译：本发明公开了一种设置在半导体衬底中的半导体功率器件。半导体功率器件包括沟槽栅极，每个沟槽栅极具有在由侧壁间隔物围绕的半导体衬底的顶表面之上延伸的伸出栅极段。半导体功率器件还包括与基本上平行于沟槽栅极的侧壁间隔开的开口的槽。粘贴门区段还包括由侧壁间隔物围绕的绝缘材料构成的盖。阻挡金属层覆盖盖的顶表面并且覆盖在侧壁间隔物上并在槽的顶表面上方延伸。这些槽填充有与栅极段相同的栅极材料，用作附加栅电极，用于提供向沟槽栅极延伸的耗尽层，借此栅极与沟槽栅极之间的漂移区域完全耗尽栅极 - 漏极电压Vgs = 0伏。

5. 发明授权

US08264084B2 Solder-top enhanced semiconductor device for low parasitic impedance packaging 有权
标题翻译：焊接增强型半导体器件，用于低寄生阻抗封装
公开(公告)号：US08264084B2
公开(公告)日：2012-09-11
申请号：US11932845
申请日：2007-10-31
申请人： François Hébert , Anup Bhalla , Kai Liu , Ming Sun
发明人： François Hébert , Anup Bhalla , Kai Liu , Ming Sun
IPC分类号： H01L21/60 , H01L23/488
CPC分类号： H01L24/40 , H01L23/4952 , H01L23/49562 , H01L23/64 , H01L24/29 , H01L24/33 , H01L24/37 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/83 , H01L2224/05624 , H01L2224/29101 , H01L2224/29111 , H01L2224/32245 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/40249 , H01L2224/4103 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48472 , H01L2224/48624 , H01L2224/48724 , H01L2224/48824 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/83194 , H01L2224/83801 , H01L2224/84801 , H01L2924/0001 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01067 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/157 , H01L2924/181 , H01L2924/19043 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/29099 , H01L2224/37099
摘要： A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes: a) Lithographically patterning the top metal layer into the contact zones and the contact enhancement zones. b) Forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.
摘要翻译：提出了一种焊顶增强型半导体器件进行封装。焊料顶部器件包括具有图案化为接触区域和接触增强区域的顶部金属层的器件裸片。至少一个接触区域电连接到至少一个接触增强区域。每个接触增强区顶部都是一个焊料层，用于增加复合材料厚度，从而降低寄生阻抗。在顶部金属材料不能与焊料材料形成均匀的良好电接合的情况下，器件裸片还包括夹在中间层之间并与顶部金属层和焊料层形成均匀的电接合的中间层。用于制造焊料顶部器件的方法包括：a）将顶部金属层的光刻图案化成接触区域和接触增强区域。 b）使用用于增加复合材料厚度的模版工艺在每个接触增强区的顶部上形成焊料层。

6. 发明授权

US10896968B2 Device structure and manufacturing method using HDP deposited source-body implant block 有权
公开(公告)号：US10896968B2
公开(公告)日：2021-01-19
申请号：US15499487
申请日：2017-04-27
申请人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K. Lui
发明人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K. Lui
IPC分类号： H01L29/423 , H01L29/06 , H01L29/40
摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

7. 发明授权

US09024378B2 Device structure and manufacturing method using HDP deposited source-body implant block 有权
标题翻译：使用HDP沉积源体植入块的装置结构和制造方法
公开(公告)号：US09024378B2
公开(公告)日：2015-05-05
申请号：US13763644
申请日：2013-02-09
申请人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K Lui
发明人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K Lui
IPC分类号： H01L29/78 , H01L21/265 , H01L29/66
CPC分类号： H01L29/7827 , H01L21/265 , H01L21/2652 , H01L21/26586 , H01L21/266 , H01L29/0619 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813
摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
摘要翻译：本发明公开了一种半导体功率器件。沟槽半导体功率器件包括从半导体衬底的顶表面开口的沟槽栅极，被包围在设置在衬底底表面上的漏区以上的顶表面附近的体区中的源极区围绕。所述半导体功率器件还包括植入离子块，所述植入离子块设置在所述身体区域旁边的台面区域的上表面上，所述植入离子块具有基本上大于0.3微米的厚度，用于阻挡体注入离子和源离子进入台面区域从而可以减少用于制造半导体功率器件的掩模。

8. 发明授权

US08878292B2 Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method 有权
标题翻译：自对准开槽积分型场效应晶体管（AccuFET）结构及方法
公开(公告)号：US08878292B2
公开(公告)日：2014-11-04
申请号：US12074280
申请日：2008-03-02
申请人： François Hébert , Madhur Bobde , Anup Bhalla
发明人： François Hébert , Madhur Bobde , Anup Bhalla
IPC分类号： H01L29/739
CPC分类号： H01L29/7828 , H01L29/0619 , H01L29/0623 , H01L29/0847 , H01L29/41766 , H01L29/456 , H01L29/66666
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.
摘要翻译：本发明公开了一种设置在半导体衬底中的半导体功率器件。半导体功率器件包括沟槽栅极，每个沟槽栅极具有在由侧壁间隔物围绕的半导体衬底的顶表面之上延伸的伸出栅极段。半导体功率器件还包括与基本上平行于沟槽栅极的侧壁间隔开的开口的槽。粘贴门区段还包括由侧壁间隔物围绕的绝缘材料构成的盖。阻挡金属层覆盖盖的顶表面并且覆盖在侧壁间隔物上并在槽的顶表面上方延伸。这些槽填充有与栅极段相同的栅极材料，用作附加栅电极，用于提供向沟槽栅极延伸的耗尽层，借此栅极与沟槽栅极之间的漂移区域完全耗尽栅极 - 漏极电压Vgs = 0伏。

9. 发明申请

US20140225187A1 DEVICE STRUCTURE AND MANUFACTURING METHOD USING HDP DEPOSITED SOURCE-BODY IMPLANT BLOCK 审中-公开
标题翻译：使用HDP沉积源体植入块的装置结构和制造方法
公开(公告)号：US20140225187A1
公开(公告)日：2014-08-14
申请号：US13763644
申请日：2013-02-09
申请人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K. Lui
发明人： Anup Bhalla , François Hébert , Sung-Shan Tai , Sik K. Lui
IPC分类号： H01L29/78 , H01L29/66 , H01L21/265
CPC分类号： H01L29/7827 , H01L21/265 , H01L21/2652 , H01L21/26586 , H01L21/266 , H01L29/0619 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813
摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
摘要翻译：本发明公开了一种半导体功率器件。沟槽半导体功率器件包括从半导体衬底的顶表面开口的沟槽栅极，被包围在设置在衬底底表面上的漏区以上的顶表面附近的体区中的源极区围绕。所述半导体功率器件还包括植入离子块，所述植入离子块设置在所述身体区域旁边的台面区域的上表面上，所述植入离子块具有基本上大于0.3微米的厚度，用于阻挡体注入离子和源离子进入台面区域从而可以减少用于制造半导体功率器件的掩模。

10. 发明授权

US08357973B2 Inverted-trench grounded-source FET structure with trenched source body short electrode 有权
标题翻译：反沟槽接地源FET结构，具有沟槽源体短路电极
公开(公告)号：US08357973B2
公开(公告)日：2013-01-22
申请号：US13199382
申请日：2011-08-25
申请人： Sik K Lui , François Hébert , Anup Bhalla
发明人： Sik K Lui , François Hébert , Anup Bhalla
IPC分类号： H01L29/66
CPC分类号： H01L29/781 , H01L21/823487 , H01L27/088 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region. The combined sinker-channel region extending below the drift region and the combined sinker-channel region that has a dopant-conductivity opposite to and compensating the drift region for reducing the source-drain capacitance.
摘要翻译：本发明公开了底源横向扩散MOS（BS-LDMOS）器件。器件具有在半导体衬底的顶表面附近的漏区附近设置的源极区域，该半导体衬底在源极区域和漏极区域之间支撑栅极。 BS-LDMOS器件还具有一个组合的沉降通道区域，该半导体衬底的深度完全位于靠近顶表面的源极区域附近设置的体区域之下，其中组合沉降通道区域用作掩埋源体用于将主体区域和源区域电连接到用作源电极的衬底的底部。漂移区域设置在栅极下方的顶表面附近并且远离源极区域并且延伸到并包围漏极区域。在漂移区域下方延伸的组合沉降通道区域和具有与掺杂剂 - 导电性相反并补偿漂移区域以减少源极 - 漏极电容的组合沉降沟道区域。

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