专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09990982B2 Memory module and memory system 有权
公开(公告)号：US09990982B2
公开(公告)日：2018-06-05
申请号：US14476023
申请日：2014-09-03
申请人： Longitude Semiconductor S.a.r.l.
发明人： Yoshinori Matsui , Toshio Sugano , Hiroaki Ikeda
IPC分类号： G11C5/06 , G11C11/408 , G11C5/00 , G11C5/04 , G11C7/10 , G11C29/12 , G11C29/26 , G11C29/48 , H01L25/065 , H01L25/18 , G11C8/12 , H01L23/538
CPC分类号： G11C11/408 , G11C5/00 , G11C5/04 , G11C5/06 , G11C7/1051 , G11C7/1063 , G11C8/12 , G11C29/1201 , G11C29/26 , G11C29/48 , H01L23/5384 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2224/0401
摘要： In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

2. 发明授权

US09715921B2 Semiconductor device having PDA function 有权
公开(公告)号：US09715921B2
公开(公告)日：2017-07-25
申请号：US15271872
申请日：2016-09-21
申请人： Longitude Semiconductor S.a.r.l.
发明人： Chikara Kondo
IPC分类号： G11C8/00 , G11C11/4093 , G11C7/10 , G11C7/22 , G11C11/4072 , G11C11/4076 , G11C11/408 , G11C11/4096 , G11C11/4063
CPC分类号： G11C11/4093 , G06F13/161 , G11C7/1045 , G11C7/109 , G11C7/1093 , G11C7/222 , G11C11/4063 , G11C11/4072 , G11C11/4076 , G11C11/4087 , G11C11/4096 , Y02D10/14
摘要： A method for writing a mode register in a semiconductor device, the method includes receiving a mode register command and a mode signal; generating a first mode register setting signal; delaying the first mode register setting signal in a first latency shifter to provide a second mode register setting signal; receiving a data signal in synchronization with the second mode register setting signal; and writing the mode signal to the mode register only if the received data signal has a first logic level.

3. 发明授权

US09595591B2 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09595591B2
公开(公告)日：2017-03-14
申请号：US14646461
申请日：2013-11-22
申请人： PS5 Luxco S.a.r.l.
发明人： Takeshi Nagai
IPC分类号： H01L29/78 , H01L29/423 , H01L21/8238 , H01L21/283 , H01L27/108 , H01L29/06 , H01L29/49 , H01L29/51 , H01L29/66
CPC分类号： H01L29/4238 , H01L21/283 , H01L21/823842 , H01L21/823857 , H01L27/108 , H01L27/10844 , H01L29/0692 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66484 , H01L29/6659 , H01L29/7831 , H01L29/7833
摘要： One device includes a substrate which contains a well region of one conductivity type, an element isolation insulating film which is arranged within the well region, an island-shaped active region which is surrounded by the element isolation insulating film, two first gate structures which are arranged on the island-shaped active region, and each of which is configured by sequentially laminating a lower gate insulating film, a gate insulating film having a high dielectric constant, a first gate electrode film containing a metal material, and a second gate electrode film, and a second gate structure which includes a second gate electrode film that is in contact with and covers a part of the element isolation insulating film. The two first gate structures and the second gate structure are successively arranged in the order of one first gate structure, the second gate structure and the other first gate structure.
摘要翻译：一个器件包括：衬底，其包含一个导电类型的阱区;布置在阱区内的元件隔离绝缘膜;被元件隔离绝缘膜包围的岛状有源区;两个第一栅极结构，布置在岛状有源区上，并且每个通过顺序层叠下栅极绝缘膜，具有高介电常数的栅绝缘膜，含有金属材料的第一栅电极膜和第二栅电极膜以及第二栅极结构，其包括与元件隔离绝缘膜接触并覆盖元件隔离绝缘膜的一部分的第二栅极电极膜。两个第一栅极结构和第二栅极结构以一个第一栅极结构，第二栅极结构和另一个第一栅极结构的顺序连续布置。

4. 发明授权

US09570447B2 Semiconductor device and production method therefor 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09570447B2
公开(公告)日：2017-02-14
申请号：US14762132
申请日：2014-01-22
申请人： PS4 Luxco S.a.r.l.
发明人： Yoshihiro Takaishi
IPC分类号： H01L27/108 , H01L29/78 , H01L29/66 , H01L21/265 , H01L27/02
CPC分类号： H01L27/10814 , H01L21/26513 , H01L27/0207 , H01L27/108 , H01L27/10823 , H01L27/10876 , H01L27/10894 , H01L29/66545 , H01L29/66666 , H01L29/7827
摘要： One semiconductor device includes first to third gate electrodes arranged inside a first active region and embedded in first to third trenches extending in a first direction, a first semiconductor pillar positioned between the first and second trenches, a second semiconductor pillar positioned between the second and third trenches, a first vertical transistor having the first and second gate electrodes as the double gate electrodes therefor, and a second vertical transistor having the second and third gate electrodes as the double gate electrodes therefor. The second gate electrode is shared by the first vertical transistor and the second vertical transistor.
摘要翻译：一个半导体器件包括布置在第一有源区内并嵌入在沿第一方向延伸的第一至第三沟槽中的第一至第三栅极电极，位于第一和第二沟槽之间的第一半导体柱，位于第二和第三沟槽之间的第二半导体柱沟槽，具有第一和第二栅电极作为其双栅电极的第一垂直晶体管，以及具有第二和第三栅电极作为双栅电极的第二垂直晶体管。第二栅电极由第一垂直晶体管和第二垂直晶体管共享。

5. 发明授权

US09564206B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09564206B2
公开(公告)日：2017-02-07
申请号：US14891272
申请日：2014-05-14
申请人： PS4 Luxco S.a.r.l.
发明人： Taihei Shido
IPC分类号： G11C16/04 , G11C11/4093 , G11C7/10 , G11C11/4076 , G11C11/4096 , G11C29/44
CPC分类号： G11C11/4093 , G11C7/1006 , G11C7/1087 , G11C7/1096 , G11C11/4076 , G11C11/4096 , G11C29/44
摘要： Embodiments of the present invention relate to a latch circuit (L20) which latches a data mask signal (DM) in response to a one-shot signal (NS), and changes the data mask signal (DM) to an active level in response to an error signal (ERR), which indicates that an error is present in write data (DQ), being at an active level; a buffer circuit (BF2) which outputs the data mask signal (DM) that has been latched by the latch circuit (L20), said data mask signal (DM) being output in response to a write clock signal (WCLK2); and a main amplifier (80) which outputs the write data (DQ) to an internal circuit on the condition that the data mask signal (DM) which has been output from the buffer circuit (BF2) is at an inactive level. The present invention can prevent the writing of erroneous write data, and is capable of preventing increased chip surface area.
摘要翻译：本发明的实施例涉及一种响应于单触发信号（NS）锁存数据屏蔽信号（DM）的锁存电路（L20），并响应于该触发信号将数据屏蔽信号（DM）改变为有效电平指示在写入数据（DQ）中存在错误的错误信号（ERR）处于活动级; 输出由锁存电路（L20）锁存的数据屏蔽信号（DM）的缓冲电路（BF2），响应写入时钟信号（WCLK2）输出所述数据屏蔽信号（DM）。以及在从缓冲电路（BF2）输出的数据掩码信号（DM）处于非活动状态的条件下，将写入数据（DQ）输出到内部电路的主放大器（80）。本发明可以防止写入错误的写入数据，并且能够防止增加的芯片表面积。

6. 发明授权

US09502354B2 Semiconductor device with layout of wiring layer and dummy patterns 有权
标题翻译：具有布线层和虚拟图案布局的半导体器件
公开(公告)号：US09502354B2
公开(公告)日：2016-11-22
申请号：US14555851
申请日：2014-11-28
申请人： PS4 LUXCO S.A.R.L.
发明人： Michio Inoue , Yorio Takada
IPC分类号： G06F17/50 , H01L23/538 , H01L23/528
CPC分类号： H01L23/5386 , G06F17/5068 , G06F17/5072 , G06F17/5077 , G06F17/5081 , H01L21/76865 , H01L23/528 , H01L23/538 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.
摘要翻译：图案布局方法包括以下过程。提取半导体晶片的第一区域中的第一布线的图形数据。第一个区域是半导体芯片形成区域。第一区域由半导体晶片的划线区域包围。第一个区域包括第二个区域。第二个区域与划刻区域有界。第二区域具有从半导体芯片形成区域和划线区域之间的边界到第一区域和第二区域之间的边界的第二距离。布置了第一个区域中的第一个虚拟模式。第一虚设图形具有与第一布线至少第一距离。布置第二区域中的第二虚拟图案。第二虚设图形具有至少距离第一布线的第一距离。第二虚拟图形具有距离第一虚设图案至少第三距离。

7. 发明授权

US09496267B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09496267B2
公开(公告)日：2016-11-15
申请号：US14890875
申请日：2014-05-09
申请人： PS4 Luxco S.a.r.l.
发明人： Kazuaki Tonari , Yuki Togashi
IPC分类号： H01L27/108 , H01L29/423 , H01L29/66 , H01L21/768
CPC分类号： H01L27/10855 , H01L21/76897 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L29/4236 , H01L29/66795
摘要： In one device, a first space partitioned by first and second line patters is filled with a multilayer film that is composed of a first silicon film having a high impurity concentration relative to a standard plug impurity concentration and a second silicon film having a low impurity concentration relative to the standard plug impurity concentration, and is divided by forming a groove using a mask film on the side wall of the second line pattern. As a result, expansion of a seam, which is formed only on the second silicon film having a low impurity concentration, is suppressed. After that, an isolation insulating film is embedded in the groove and impurity diffusion is carried out by a heat treatment, so that divided plugs as a whole are made to have the standard plug impurity concentration.
摘要翻译：在一个器件中，由第一和第二线图案分隔的第一空间填充有多层膜，该多层膜由相对于标准插塞杂质浓度具有高杂质浓度的第一硅膜和具有低杂质浓度的第二硅膜组成相对于标准塞子杂质浓度，并且通过在第二线图案的侧壁上使用掩模膜形成凹槽来分割。结果，抑制仅在具有低杂质浓度的第二硅膜上形成的接缝的膨胀。之后，将隔离绝缘膜嵌入槽中，通过热处理进行杂质扩散，使得分插塞整体上具有标准的插塞杂质浓度。

8. 发明授权

US09472557B2 Memory transistors with buried gate electrodes 有权
公开(公告)号：US09472557B2
公开(公告)日：2016-10-18
申请号：US14815542
申请日：2015-07-31
申请人： PS4 Luxco S.a.r.l.
发明人： Kazutaka Manabe
IPC分类号： H01L27/108 , H01L29/94 , H01L29/66 , H01L49/02 , H01L29/423 , H01L21/74
CPC分类号： H01L27/10823 , H01L21/743 , H01L27/10805 , H01L27/10808 , H01L27/10814 , H01L27/10847 , H01L27/1085 , H01L27/10876 , H01L27/10888 , H01L28/60 , H01L28/87 , H01L28/91 , H01L29/4236 , H01L29/66181 , H01L29/94 , H01L29/945
摘要： A device includes a semiconductor region surrounded with the isolation region and includes a first active region, a channel region and a second active region arranged in that order in a first direction. A first side portion of the first active region and a second side portion of the second active region faces each other across a top surface of the channel region in the first direction. A gate electrode covers the top surface and the first and second side portions and extends in a second direction that intersects the first direction. A first diffusion layer is formed in the first active region. A second diffusion layer is formed in the second active region. An embedded contact plug is formed in the first active region and extends downwardly from the upper surface of the semiconductor region and contacts with the first diffusion layer.

9. 发明授权

US10147479B2 Memory module and memory system 有权
公开(公告)号：US10147479B2
公开(公告)日：2018-12-04
申请号：US15996974
申请日：2018-06-04
申请人： Longitude Semiconductor S.a.r.l.
发明人： Yoshinori Matsui , Toshio Sugano , Hiroaki Ikeda
IPC分类号： G11C5/06 , G11C11/408 , G11C5/04 , H01L23/538 , G11C8/12 , G11C5/00 , H01L25/18 , H01L25/065 , G11C29/48 , G11C29/26 , G11C29/12 , G11C7/10
摘要： In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

10. 发明授权

US10037971B2 Semiconductor device having plural memory chip 有权
公开(公告)号：US10037971B2
公开(公告)日：2018-07-31
申请号：US15010930
申请日：2016-01-29
申请人： PS4 Luxco S.a.r.l.
发明人： Akira Ide
IPC分类号： G06F17/50 , H01L25/065 , H01L23/48 , G11C5/04 , H01L23/50 , G11C11/408
CPC分类号： H01L25/0657 , G11C5/04 , G11C11/408 , H01L23/481 , H01L23/50 , H01L2224/16145 , H01L2225/06544
摘要： A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip. Penetration electrodes arranged in the same positions as seen in a stacking direction are connected in common between the chips. In response to an access request, the memory chips activate the memory banks that are arranged in respective different positions as seen in the stacking direction, whereby data is simultaneously input/output via the penetration electrodes that lie in different planar positions.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式