专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07724775B2 Data transmission circuit and method for controlling the data transmission circuit 有权
标题翻译：数据传输电路及数据传输电路的控制方法
公开(公告)号：US07724775B2
公开(公告)日：2010-05-25
申请号：US11704245
申请日：2007-02-09
申请人： Yuji Saito
发明人： Yuji Saito
IPC分类号： H04J3/24 , H04J3/04
CPC分类号： H04L49/9094 , H04L47/10 , H04L49/90
摘要： A circuit connected to a data transmission path, said circuit comprising, a merge element which generates merged data by merging a plurality of incoming data; and a controller which transmits said merged data through said data transmission path when said data transmission path comes open.
摘要翻译：连接到数据传输路径的电路，所述电路包括：合并元件，其通过合并多个输入数据产生合并的数据; 以及当所述数据传输路径打开时通过所述数据传输路径发送所述合并的数据的控制器。

2. 发明授权

US08041758B2 Multiplier and arithmetic unit 有权
标题翻译：乘数和运算单位
公开(公告)号：US08041758B2
公开(公告)日：2011-10-18
申请号：US11709784
申请日：2007-02-23
申请人： Takashi Osada
发明人： Takashi Osada
IPC分类号： G06F7/44 , G06F7/52 , G06F1/00
CPC分类号： G06F7/53 , G06F2207/382 , G06F2207/3868 , G06F2207/3872
摘要： A multiplier has a multiplication array in which partial products are generated by performing multiplication between a multiplier and a multiplicand, and a partial product control circuit which generates an enable signal for activating an effective region in the multiplication array corresponding to effective figures of the multiplier and the multiplicand. The effective figures depend on the format of the multiplier and the multiplicand. The partial product control circuit controls the status of the enable signal according to a multiplication command designating the format. The multiplication array is constituted by a dynamic circuit. The dynamic circuit in an initial stage of the multiplication array has a switch which is turned on/off by the enable signal. When the enable signal is ineffective, the switch is turned off and a discharging operation in the dynamic circuit is stopped.
摘要翻译：乘法器具有乘法阵列，其中通过执行乘法器和被乘数之间的乘法来生成部分乘积，以及部分乘积控制电路，其产生用于激活与乘法器的有效数字相对应的乘法阵列中的有效区域的使能信号;以及被乘数。有效数字取决于乘数和被乘数的格式。部分产品控制电路根据指定格式的乘法命令来控制使能信号的状态。乘法阵列由动态电路构成。乘法阵列的初始阶段的动态电路具有由使能信号导通/截止的开关。当使能信号无效时，开关断开，动态电路中的放电动作停止。

3. 发明授权

US07904665B2 Multiprocessor system and its operational method 有权
标题翻译：多处理器系统及其操作方法
公开(公告)号：US07904665B2
公开(公告)日：2011-03-08
申请号：US11657045
申请日：2007-01-24
申请人： Yoshiaki Watanabe
发明人： Yoshiaki Watanabe
IPC分类号： G06F12/00
CPC分类号： G06F12/0828
摘要： The multiprocessor system includes multiple cells having identical functions, and each of the multiple cells has a processor, a cache memory, and a main memory. The multiple cells include the first cell as a request cell, the second cell as a home cell, and the third cell as an owner cell. The latest version of the target data stored in the main memory of the second cell is stored in the cache memory of the third cell. When the first cell issues a read request for the target data to the second cell, the second cell issues a snoop request to the third cell in response to the read request. The third cell directly transmits the target data to the first cell in response to the snoop request. Also, the third cell issues the reply write back to the second cell in response to the snoop request. The first cell issues a request write back to the same address as that of the target data in the second cell. The second cell discards the reply write back when the reply write back from the third cell is received later than the request write back from the first cell.
摘要翻译：多处理器系统包括具有相同功能的多个单元，并且多个单元中的每一个具有处理器，高速缓冲存储器和主存储器。多个小区包括作为请求小区的第一小区，作为家庭小区的第二小区，以及作为所有者小区的第三小区。存储在第二单元的主存储器中的最新版本的目标数据被存储在第三单元的高速缓冲存储器中。当第一小区向第二小区发出对目标数据的读请求时，第二小区响应于读请求向第三小区发出窥探请求。响应于窥探请求，第三小区直接将目标数据发送到第一小区。而且，响应于窥探请求，第三单元将回复发回到第二单元。第一个单元将请求写回与第二个单元格中的目标数据相同的地址。当从第三个单元写入回复的第二个单元接收晚于从第一个单元写入的请求时，第二个单元丢弃该回复。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式