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1. 发明申请

US20190205094A1 MIXED-PRECISION PROCESSING ELEMENTS, SYSTEMS, AND METHODS FOR COMPUTATIONAL MODELS 审中-公开
公开(公告)号：US20190205094A1
公开(公告)日：2019-07-04
申请号：US15857998
申请日：2017-12-29
申请人： Facebook, Inc.
发明人： Abdulkadir Utku Diril , Mikhail Smelyanskiy , Nadav Rotem , Jong Soo Park
IPC分类号： G06F7/523
CPC分类号： G06F7/523 , G06F7/5443 , G06F2207/382 , G06N3/0481 , G06N3/063 , G06N3/08 , G06N5/022
摘要： The disclosed method may include (1) receiving a precision level of each weight associated with each input of a node of a computational model, (2) identifying, for each weight, one of a plurality of multiplier groups, where each multiplier group may include a plurality of hardware multipliers of a corresponding bit width, and where the corresponding bit width of the plurality of hardware multipliers of the one of the plurality of multiplier groups may be sufficient to multiply the weight by the associated input, and (3) multiplying each weight by its associated input using an available hardware multiplier of the one of the plurality of multiplier groups identified for the weight. Various other processing elements, methods, and systems are also disclosed.

2. 发明授权

US10073676B2 Reduced floating-point precision arithmetic circuitry 有权
公开(公告)号：US10073676B2
公开(公告)日：2018-09-11
申请号：US15272231
申请日：2016-09-21
申请人： Altera Corporation
发明人： Martin Langhammer
IPC分类号： G06F7/487 , G06F17/16
CPC分类号： G06F7/485 , G06F7/4876 , G06F7/49957 , G06F7/5443 , G06F9/30014 , G06F17/16 , G06F2207/382 , G06F2207/483
摘要： The present embodiments relate to performing reduced-precision floating-point arithmetic operations using specialized processing blocks with higher-precision floating-point arithmetic circuitry. A specialized processing block may receive four floating-point numbers that represent two single-precision floating-point numbers, each separated into an LSB portion and an MSB portion, or four half-precision floating-point numbers. A first partial product generator may generate a first partial product of first and second input signals, while a second partial product generator may generate a second partial product of third and fourth input signals. A compressor circuit may generate carry and sum vector signals based on the first and second partial products; and circuitry may anticipate rounding and normalization operations by generating in parallel based on the carry and sum vector signals at least two results when performing the single-precision floating-point operation and at least four results when performing the two half-precision floating-point operations.

3. 发明申请

US20170322808A1 LOW-POWER PROCESSOR WITH SUPPORT FOR MULTIPLE PRECISION MODES 审中-公开
公开(公告)号：US20170322808A1
公开(公告)日：2017-11-09
申请号：US15147642
申请日：2016-05-05
申请人： Cirrus Logic International Semiconductor Ltd.
发明人： Anthony James Magrath , Bryant E. Sorensen
IPC分类号： G06F9/30
CPC分类号： G06F9/30112 , G06F7/38 , G06F9/3001 , G06F9/30014 , G06F9/30189 , G06F2207/382
摘要： Multiple data wordlengths may be supported by a processor through a single data path and/or a single set of registers. For example, the processor may support 16-bit wordlengths and 24-bit wordlengths through a single datapath. For supported data wordlengths that are less than the wordlength of the registers and datapath, the data may be left-aligned within the registers and datapath. The left alignment of data may allow saturation detection in the processor to be performed by examining the same saturation point regardless of the wordlength of the data being operated on. A special saturation mode of the processor may set the lower bits to zero when a configuration register or instruction-bit is set and saturation is detected.

4. 发明授权

US09753690B2 Splitable and scalable normalizer for vector data 有权
公开(公告)号：US09753690B2
公开(公告)日：2017-09-05
申请号：US15151062
申请日：2016-05-10
申请人： International Business Machines Corporation
发明人： Maarten J. Boersma , Markus Kaltenbach , Christophe J. Layer , Silvia M. Mueller
IPC分类号： G06F7/00 , G06F7/499 , G06F15/78 , G06F15/80 , G06F9/30 , G06F7/483
CPC分类号： G06F7/49936 , G06F7/00 , G06F7/483 , G06F7/49915 , G06F9/30014 , G06F9/30036 , G06F9/30189 , G06F9/3887 , G06F15/78 , G06F15/8053 , G06F2207/382
摘要： A tool for supporting vector operations in a scalar data path. The tool determines a location for a split in the scalar mode configuration to enable vector mode operations. The tool determines the number of coarse shift multiplexers in conflict at a bit position receiving data from both the left half and the right half of the vector mode configuration. The tool duplicates a coarse shift multiplexer in conflict at the bit position receiving data from both the left half and the right half of the vector mode configuration. The tool duplicates an intermediate data signal in conflict at a signal position receiving data from both the left half and the right half of the vector mode configuration. The tool receives a control signal to split the scalar mode configuration and shift the leading zeros across the left half and the right half of the vector mode configuration.

5. 发明申请

US20160253152A1 SPLITABLE AND SCALABLE NORMALIZER FOR VECTOR DATA 有权
标题翻译：用于矢量数据的可分离和可扩展的标准化
公开(公告)号：US20160253152A1
公开(公告)日：2016-09-01
申请号：US15151062
申请日：2016-05-10
申请人： International Business Machines Corporation
发明人： Maarten J. Boersma , Markus Kaltenbach , Christophe J. Layer , Silvia M. Mueller
IPC分类号： G06F7/499
CPC分类号： G06F7/49936 , G06F7/00 , G06F7/483 , G06F7/49915 , G06F9/30014 , G06F9/30036 , G06F9/30189 , G06F9/3887 , G06F15/78 , G06F15/8053 , G06F2207/382
摘要： A tool for supporting vector operations in a scalar data path. The tool determines a location for a split in the scalar mode configuration to enable vector mode operations. The tool determines the number of coarse shift multiplexers in conflict at a bit position receiving data from both the left half and the right half of the vector mode configuration. The tool duplicates a coarse shift multiplexer in conflict at the bit position receiving data from both the left half and the right half of the vector mode configuration. The tool duplicates an intermediate data signal in conflict at a signal position receiving data from both the left half and the right half of the vector mode configuration. The tool receives a control signal to split the scalar mode configuration and shift the leading zeros across the left half and the right half of the vector mode configuration.
摘要翻译：用于在标量数据路径中支持向量操作的工具。该工具确定标量模式配置中拆分的位置，以启用向量模式操作。该工具确定在向量模式配置的左半部分和右半部分接收数据的位位置处冲突中的粗移位复用器的数量。该工具在从向量模式配置的左半部分和右半部分接收数据的比特位置处复制冲突中的粗略移位复用器。该工具在从矢量模式配置的左半部分和右半部分接收数据的信号位置处复制冲突中的中间数据信号。该工具接收一个控制信号，以分割标量模式配置，并将前导零移动到向量模式配置的左半部分和右半部分。

6. 发明授权

US09223753B2 Dynamic range adjusting floating point execution unit 有权
标题翻译：动态范围调整浮点执行单元
公开(公告)号：US09223753B2
公开(公告)日：2015-12-29
申请号：US13793240
申请日：2013-03-11
申请人： International Business Machines Corporation
发明人： Mark J. Hickey , Adam J. Muff , Matthew R. Tubbs , Charles D. Wait
IPC分类号： G06F17/10 , G06F7/483 , G06F7/544 , G06F9/30 , G06F9/38
CPC分类号： G06F17/10 , G06F7/483 , G06F7/5443 , G06F9/30014 , G06F9/30189 , G06F9/3861 , G06F2207/382 , G06F2207/3828
摘要： A floating point execution unit is capable of selectively repurposing a subset of the significand bits in a floating point value for use as additional exponent bits to dynamically provide an extended range for floating point calculations. A significand field of a floating point operand may be considered to include first and second portions, with the first portion capable of being concatenated with the second portion to represent the significand for a floating point value, or, to provide an extended range, being concatenated with the exponent field of the floating point operand to represent the exponent for a floating point value.
摘要翻译：浮点执行单元能够选择性地重新排列浮点值中的有效位的子集，以用作附加指数位以动态地提供用于浮点计算的扩展范围。浮点操作数的有效位域可以被认为包括第一和第二部分，其中第一部分能够与第二部分连接以表示浮点值的有效位数，或者提供扩展的范围，被连接与浮点运算数的指数字段表示浮点值的指数。

7. 发明申请

US20150067299A1 SPLITABLE AND SCALABLE NORMALIZER FOR VECTOR DATA 有权
公开(公告)号：US20150067299A1
公开(公告)日：2015-03-05
申请号：US14150925
申请日：2014-01-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Maarten J. Boersma , Markus Kaltenbach , Christophe J. Layer , Silvia M. Mueller
IPC分类号： G06F15/78
CPC分类号： G06F7/49936 , G06F7/00 , G06F7/483 , G06F7/49915 , G06F9/30014 , G06F9/30036 , G06F9/30189 , G06F9/3887 , G06F15/78 , G06F15/8053 , G06F2207/382
摘要： A hardware circuit component configured to support vector operations in a scalar data path. The hardware circuit component configured to operate in a vector mode configuration and in a scalar mode configuration. The hardware circuit component configured to split the scalar mode configuration into a left half and a right half of the vector mode configuration. The hardware circuit component configured to perform one or more bit shifts over one or more stages of interconnected multiplexers in the vector mode configuration. The hardware circuit component configured to include duplicated coarse shift multiplexers at bit positions that receive data from both the left half and the right half of the vector mode configuration, resulting in one or more coarse shift multiplexers sharing the bit position.

8. 发明申请

US20140214913A1 ADDER CAPABLE OF SUPPORTING ADDITION AND SUBTRACTION OF UP TO N-BIT DATA AND METHOD OF SUPPORTING ADDITION AND SUBTRACTION OF A PLURALITY OF DATA TYPE USING THE ADDER 有权
标题翻译：可以支持添加和提交到N位数据的添加，以及使用添加剂支持添加和减少数据类型多样性的方法
公开(公告)号：US20140214913A1
公开(公告)日：2014-07-31
申请号：US14166076
申请日：2014-01-28
申请人： Samsung Electronics Co., Ltd.
发明人： Hyeong-Seok YU , Suk-Jin KIM
IPC分类号： G06F17/10
CPC分类号： G06F17/10 , G06F7/503 , G06F7/507 , G06F2207/382 , G06F2207/3828
摘要： An adder for supporting multiple data types by controlling a carry propagation is provided. The adder includes a plurality of first addition areas configured to receive pieces of incoming operand data, wherein each of the plurality of first addition areas includes a predetermined unit number of bits, and a plurality of second addition areas configured to receive pieces of control data based on a type of the operand data and an operation type, wherein the plurality of second addition areas are alternately arranged between the plurality of first addition areas.
摘要翻译：提供了一种用于通过控制进位传播来支持多种数据类型的加法器。所述加法器包括多个第一加法区域，被配置为接收输入操作数数据，其中所述多个第一加法区域中的每一个包括预定单位数位，以及多个第二加法区域，被配置为接收多条控制数据关于操作数数据的类型和操作类型，其中所述多个第二相加区域交替地布置在所述多个第一相加区域之间。

9. 再颁专利

USRE44697E1 Encryption processor with shared memory interconnect 有权
标题翻译：具有共享内存互连的加密处理器
公开(公告)号：USRE44697E1
公开(公告)日：2014-01-07
申请号：US13603137
申请日：2012-09-04
申请人： David E. Jones , Cormac M. O'Connell
发明人： David E. Jones , Cormac M. O'Connell
IPC分类号： G06F21/00
CPC分类号： G06F7/5324 , G06F7/49931 , G06F7/5052 , G06F7/72 , G06F7/722 , G06F2207/382 , G06F2207/3828 , H04L9/14 , H04L2209/125
摘要： An encryption chip is programmable to process a variety of secret key and public key encryption algorithms. The chip includes a pipeline of processing elements, each of which can process a round within a secret key algorithm. Data is transferred between the processing elements through dual port memories. A central processing unit allows for processing of very wide data words from global memory in single cycle operations. An adder circuit is simplified by using plural relatively small adder circuits with sums and carries looped back in plural cycles. Multiplier circuitry can be shared between the processing elements and the central processor by adapting the smaller processing element multipliers for concatenation as a very wide central processor multiplier.
摘要翻译：加密芯片是可编程的，用于处理各种秘密密钥和公钥加密算法。该芯片包括处理元件的流水线，每个处理元件可以在秘密密钥算法内处理一轮。通过双端口存储器在处理元件之间传送数据。中央处理单元允许在单周期操作中处理来自全局存储器的非常宽的数据字。通过使用多个具有和的相对较小的加法器电路来简化加法器电路，并以多个周期进行循环。乘法器电路可以通过将较小的处理单元乘法器适配为级联，作为非常宽的中央处理器乘法器而在处理元件和中央处理器之间共享。

10. 发明申请

US20130332497A1 MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE, DEDICATED CONNECTIONS BETWEEN MODULES OF THE CIRCUITRY 有权
标题翻译：模块化数字信号处理电路，具有可选择的电路模块之间的专用连接
公开(公告)号：US20130332497A1
公开(公告)日：2013-12-12
申请号：US13961534
申请日：2013-08-07
申请人： Altera Corporation
发明人： Keone Streicher , Martin Langhammer , Yi-Wen Lin , Wai-Bor Leung , David Lewis , Volker Mauer , Henry Y. Lui , Suleyman Sirri Demirsoy , Hyun Yi
IPC分类号： G06F17/10
CPC分类号： G06F17/10 , G06F7/5324 , G06F2207/382 , H03H17/06 , H03H2220/06 , H03K19/17732
摘要： Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.
摘要翻译：提供数字信号处理（“DSP”）电路块，如果需要，可以更容易地一起工作来执行更大（例如更复杂和/或更具有算术精度）的DSP操作。尽管不能使用某些块（例如，由于电路缺陷），这些DSP块还可以包括有助于将多个这样的块拼接在一起的冗余电路。收缩寄存器可以包括在DSP块中的各个点处，以便于使用块来实现收缩形式，有限脉冲响应（“FIR”），数字滤波器。

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