专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08990631B1 Packet format for error reporting in a content addressable memory 有权
标题翻译：内容可寻址内存中错误报告的数据包格式
公开(公告)号：US08990631B1
公开(公告)日：2015-03-24
申请号：US13039616
申请日：2011-03-03
申请人： Shankar Channabasappa
发明人： Shankar Channabasappa
IPC分类号： G06F11/07 , H04L12/26
CPC分类号： H04L12/2647 , H04L41/06 , H04L45/7457 , H04L69/12 , H04L69/40
摘要： Approaches for a packet format for error reporting in a content addressable memory (CAM) device are disclosed. The CAM device may comprise a CAM array that includes a plurality of rows, each row including a plurality of CAM cells coupled to a match line, and an error notification circuit capable of forming a packet that indicates whether the CAM device is experiencing an error condition. If an error condition was experienced by the CAM device, the response packet may also indicate the type(s) of error that was encountered. Advantageously, information about any error condition experienced by the CAM device may be quickly ascertained by a host device in which the CAM device is incorporated.
摘要翻译：公开了一种用于内容可寻址存储器（CAM）设备中的错误报告的分组格式的方法。 CAM设备可以包括CAM阵列，其包括多行，每行包括耦合到匹配线的多个CAM单元，以及能够形成指示CAM设备是否正在经历错误状态的分组的错误通知电路。如果CAM设备出现错误状况，响应包也可能指示遇到的错误类型。有利地，可以由其中并入CAM设备的主机设备快速地确定关于CAM设备经历的任何错误状况的信息。

2. 发明授权

US08964905B1 Low power serial link 有权
标题翻译：低功率串行链路
公开(公告)号：US08964905B1
公开(公告)日：2015-02-24
申请号：US13173576
申请日：2011-06-30
申请人： Marc Loinaz
发明人： Marc Loinaz
IPC分类号： H03K5/159
CPC分类号： H04L25/4904 , H04L25/0272
摘要： The present invention relates to a low power serial link employing differential return-to-zero signaling. A receiver circuit consistent with some embodiments includes an input circuit for receiving differential serial data signals that form a differential return-to-zero signaling and a clock recovery circuit. The clock recovery circuit is coupled to the input circuit and includes a logic gate configured to generate a clock signal by using said differential serial data signals.
摘要翻译：本发明涉及采用差分归零信令的低功率串行链路。与一些实施例一致的接收机电路包括用于接收形成差分归零信令的差分串行数据信号的输入电路和时钟恢复电路。时钟恢复电路耦合到输入电路，并且包括被配置为通过使用所述差分串行数据信号产生时钟信号的逻辑门。

3. 发明授权

US08953628B2 Processor with packet ordering device 有权
标题翻译：处理器与数据包订购设备
公开(公告)号：US08953628B2
公开(公告)日：2015-02-10
申请号：US13154413
申请日：2011-06-06
申请人： David T. Hass
发明人： David T. Hass
IPC分类号： H04L12/28 , H04L12/931 , H04J1/16 , G06F12/08
CPC分类号： H04L49/00 , G06F12/0813 , H04L49/30
摘要： A processor includes a plurality of processor cores, a networking output, and a packet ordering device. The packet ordering device determines an ordering for packets that are processed by the processor cores. The packets are released to the networking output in a determined order.
摘要翻译：处理器包括多个处理器核心，联网输出和分组排序设备。分组排序设备确定处理器核心处理的分组的顺序。数据包以确定的顺序被释放到网络输出。

4. 发明授权

US08948331B2 Systems, circuits and methods for filtering signals to compensate for channel effects 有权
标题翻译：用于滤波信号以补偿信道效应的系统，电路和方法
公开(公告)号：US08948331B2
公开(公告)日：2015-02-03
申请号：US13931099
申请日：2013-06-28
申请人： NetLogic Microsystems, Inc.
发明人： Halil Cirit , Stefanos Sidiropoulos
IPC分类号： H04L7/00 , H04L25/03 , H04B10/2507
CPC分类号： H04B10/2507 , H04L25/03063 , H04L25/0307 , H04L25/03076
摘要： Embodiments of circuits and methods are described for decreasing transmitter waveform dispersion penalty (TWDP) in a transmitter. A data stream is received for transmission across a channel and a main data signal is generated from the data stream. At least two cursor signals are generated where each of the at least two cursor signals are shifted at least a portion of a clock period from the main data signal. The at least two cursor signals are subtracted from the main data signal to generate an output data signal with improved TWDP. Other embodiments include generating a main data signal, a pre-cursor signal shifted on previous clock cycle relative to the main data signal, and a post-cursor signal Shifted one subsequent clock cycle relative to the main data signal. The pre and post cursor signals are subtracted from the main data signal to generate an output data signal.
摘要翻译：描述了用于降低发射机中的发射机波形色散惩罚（TWDP）的电路和方法的实施例。接收数据流以通过信道传输，并从数据流生成主数据信号。产生至少两个光标信号，其中至少两个光标信号中的每一个从主数据信号中移位到时钟周期的至少一部分。从主数据信号中减去至少两个光标信号，以产生具有改进的TWDP的输出数据信号。其他实施例包括产生主数据信号，相对于主数据信号在先前时钟周期上移位的前置光标信号，以及相对于主数据信号移位一个后续时钟周期的后光标信号。从主数据信号中减去前后游标信号，生成输出数据信号。

5. 发明授权

US08861241B1 Content search system having embedded power control units 有权
标题翻译：具有嵌入式功率控制单元的内容搜索系统
公开(公告)号：US08861241B1
公开(公告)日：2014-10-14
申请号：US13226220
申请日：2011-09-06
申请人： Cristian Estan
发明人： Cristian Estan
IPC分类号： G11C15/00 , G11C15/04
CPC分类号： G11C15/04 , G11C15/00
摘要： A content addressable memory (CAM) device to dynamically reduces power consumption between a search key and data stored in a plurality of CAM blocks by selectively disabling a number of CAM blocks, requested for the search operation by an external network processor, based upon the contents of the search key.
摘要翻译：一种内容可寻址存储器（CAM）装置，其通过基于所述内容选择性地禁用由外部网络处理器请求搜索操作的多个CAM块来动态地减少搜索关键字与存储在多个CAM块中的数据之间的功耗的搜索关键字。

6. 发明授权

US08837188B1 Content addressable memory row having virtual ground and charge sharing 有权
标题翻译：具有虚拟地面和电荷共享的内容可寻址存储器行
公开(公告)号：US08837188B1
公开(公告)日：2014-09-16
申请号：US13167552
申请日：2011-06-23
申请人： Ganesh Krishnamurthy , Dimitri Argyres
发明人： Ganesh Krishnamurthy , Dimitri Argyres
IPC分类号： G11C15/00 , G11C15/04 , G11C11/56
CPC分类号： G11C15/04 , G11C11/56 , G11C15/00 , G11C15/046
摘要： A content addressable memory (CAM) row is disclosed. The CAM row includes one or more compare circuits coupled between a match line and a virtual-ground line. The compare circuits are configured to compare a search key with CAM cell data words. The CAM row also includes a pre-charge circuit controlled by a pre-charge signal, and includes a tank capacitor. The pre-charge circuit is configured to pre-charge the match line to a supply voltage in response to assertion of the pre-charge signal. A pull-down transistor dynamically discharges the virtual-ground line to ground potential.
摘要翻译：公开了内容可寻址存储器（CAM）行。 CAM行包括耦合在匹配线和虚拟地线之间的一个或多个比较电路。比较电路被配置为将搜索关键字与CAM单元数据字进行比较。 CAM行还包括由预充电信号控制的预充电电路，并且包括储能电容器。预充电电路被配置为响应于预充电信号的断言将匹配线预充电到电源电压。下拉晶体管将虚拟地线动态放电到地电位。

7. 发明申请

US20140244868A1 INTEGRATED CIRCUIT DEVICES, SYSTEMS AND METHODS HAVING AUTOMATIC CONFIGURABLE MAPPING OF INPUT AND/OR OUTPUT DATA CONNECTIONS 有权
标题翻译：具有输入和/或输出数据连接的自动配置映射的集成电路设备，系统和方法
公开(公告)号：US20140244868A1
公开(公告)日：2014-08-28
申请号：US14069590
申请日：2013-11-01
申请人： Netlogic Microsystems, Inc.
发明人： Whay Sing Lee
IPC分类号： G06F13/40
CPC分类号： G06F13/4022 , G06F11/28 , G06F13/4291
摘要： Integrated circuit devices are disclosed with receive ports having mapping circuits automatically configurable to change a logical mapping of data received on receive-data connections. Automatic configuration can be based on a data value included within a received data set. Corresponding systems and methods are also described.
摘要翻译：公开了具有接收端口的集成电路装置，其具有可自动配置的映射电路，以改变在接收数据连接上接收的数据的逻辑映射。自动配置可以基于包含在接收数据集中的数据值。还描述了相应的系统和方法。

8. 发明授权

US08792348B1 Serial link interface power control method and apparatus with selective idle data discard 有权
标题翻译：串行链路接口功率控制方法和设备，具有选择性空闲数据丢弃
公开(公告)号：US08792348B1
公开(公告)日：2014-07-29
申请号：US13034570
申请日：2011-02-24
申请人： Shankar Channabasappa
发明人： Shankar Channabasappa
IPC分类号： H04L1/00 , H04L12/26
CPC分类号： H04L43/0811 , G06F13/4282 , Y02D10/14 , Y02D10/151
摘要： A receiver circuit for coupling to a serial link is disclosed. The receiver circuit comprises a data buffer and serial interface circuitry. The serial interface circuitry receives serialized packet words and processes the serial words for input to the data buffer. The serial interface circuitry includes word detection logic to detect predefined control words and discard logic to selectively inhibit forwarding of one or more of the predefined control words to the data buffer.
摘要翻译：公开了一种用于耦合到串行链路的接收机电路。接收器电路包括数据缓冲器和串行接口电路。串行接口电路接收串行化的分组字，并处理串行字以输入到数据缓冲器。串行接口电路包括用于检测预定义的控制字的字检测逻辑，并且丢弃逻辑以选择性地禁止将一个或多个预定义的控制字转发到数据缓冲器。

9. 发明授权

US08700593B1 Content search system having pipelined engines and a token stitcher 失效
标题翻译：具有流水线引擎和令牌拼接器的内容搜索系统
公开(公告)号：US08700593B1
公开(公告)日：2014-04-15
申请号：US12838323
申请日：2010-07-16
申请人： Cristian Estan , Greg Watson
发明人： Cristian Estan , Greg Watson
IPC分类号： G06F17/30
CPC分类号： G06F17/30985
摘要： A content search system includes multiple pipelined search engines that implement different portions of a regular expression search operations. For some embodiments, the search pipeline includes a DFA engine, an NFA engine, and a token stitcher that combines partial match results generated by the DFA and NFA engines in a manner that prevents either engine from becoming a bottleneck. In addition, the token stitcher can be configured to implement unbounded sub-expressions without utilizing resources of the DFA or NFA engines.
摘要翻译：内容搜索系统包括实现正则表达式搜索操作的不同部分的多个流水线搜索引擎。对于一些实施例，搜索流水线包括DFA引擎，NFA引擎和令牌拼接器，其以防止引擎成为瓶颈的方式组合由DFA和NFA引擎生成的部分匹配结果。此外，令牌拼接器可以被配置为在不使用DFA或NFA引擎的资源的情况下实现无界子表达式。

10. 发明授权

US08667038B1 Methods and apparatus to increase the resolution of a clock synthesis circuit that uses feedback interpolation 失效
标题翻译：提高使用反馈插值的时钟合成电路的分辨率的方法和装置
公开(公告)号：US08667038B1
公开(公告)日：2014-03-04
申请号：US12185750
申请日：2008-08-04
申请人： Stefanos Sidiropoulos
发明人： Stefanos Sidiropoulos
IPC分类号： G06F7/52 , H03K7/08
CPC分类号： H03L7/0893 , H03K5/133 , H03K2005/00052 , H03L7/081 , H03L7/0895 , H03L7/093 , H03L7/0998 , H03L7/18
摘要： A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.
摘要翻译：频率合成电路包括锁相环和内插器电路。锁相环电路接收参考时钟和反馈时钟，并产生基于参考时钟和反馈时钟的频率的输出时钟。内插器电路耦合在锁相环电路的反馈路径中。内插器控制电路产生指定内插器电路的可变时间延迟的内插器控制字。内插器电路接收输出时钟，并根据内插器控制字在输出时钟中引入可变时间延迟来产生反馈时钟。时间可变延迟会改变输出电路的频率。公开了包括扩频频率时钟发生器，频率调制器和固定频率时钟发生器电路的频率合成电路的实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式