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1. 发明授权

US11132942B2 LED display device having decreased display image crosstalk 有权
公开(公告)号：US11132942B2
公开(公告)日：2021-09-28
申请号：US17088057
申请日：2020-11-03
申请人： TLI Inc.
发明人： Jaegan Ko
IPC分类号： G09G3/32
摘要： A light-emitting diode (LED) display device includes a display part having LED elements arranged in a matrix structure including scan lines and data lines. The LED display device also includes a scan driver driving the scan lines and each of the scan lines is controlled using a discharge voltage at a discharge timing. The LED display device also includes a data compensation part which compensates driving data of each of the data lines to generate the compensation data of each of the data lines using a compensation value to compensate for a difference in luminous intensity slope of the LED element due to a difference in the number of luminescence data lines at the unit scan timing. Thus, a crosstalk phenomenon of the display image due to a difference in the number of data lines simultaneously sourced is decreased.

2. 发明申请

US20110273103A1 LED LAMP WITH ADJUSTABLE ILLUMINATION INTENSITY BASED ON AC VOLTAGE AMPLITUDE 审中-公开
标题翻译：基于交流电压放大器的LED灯具可调光照强度
公开(公告)号：US20110273103A1
公开(公告)日：2011-11-10
申请号：US13093393
申请日：2011-04-25
申请人： Soon Won HONG
发明人： Soon Won HONG
IPC分类号： H05B37/00
CPC分类号： H05B33/0821 , H05B33/0809
摘要： An LED lamp with adjustable illumination intensity is disclosed. The LED lamp comprises an illumination block having first, second, and third illumination modules, and first and second switches. The first, second, and third illumination modules are coupled in series between a rectification voltage node and a third connection node. The first switch selectively connects a first connection node shared by the first and second illumination modules to a basis voltage node. The second switch selectively connects a second connection node shared by the second and third illumination modules to the basis voltage node. The third connection node is coupled to the basis voltage node. A control block provides the first and second control signals respectively controlling the first and second switches, wherein the logic states of the first and second control signals are based on the amplitude of a driving voltage measured between the rectification and basis voltage nodes.
摘要翻译：公开了一种具有可调节照明强度的LED灯。 LED灯包括具有第一，第二和第三照明模块以及第一和第二开关的照明块。第一，第二和第三照明模块串联耦合在整流电压节点和第三连接节点之间。第一开关选择性地将由第一和第二照明模块共享的第一连接节点连接到基本电压节点。第二开关选择性地将由第二和第三照明模块共享的第二连接节点连接到基准电压节点。第三连接节点耦合到基本电压节点。控制块提供分别控制第一和第二开关的第一和第二控制信号，其中第一和第二控制信号的逻辑状态基于在整流和基准电压节点之间测量的驱动电压的幅度。

3. 发明授权

US09496051B2 Efficient raid technique for reliable SSD 有权
标题翻译：高效的RAID技术可靠的SSD
公开(公告)号：US09496051B2
公开(公告)日：2016-11-15
申请号：US14377159
申请日：2013-02-08
申请人： TLI INC.
发明人： Jae Ho Kim , Jong Min Lee , Jong Moo Choi , Dong Hee Lee , Sam Hyuk Noh
IPC分类号： G11C29/04 , G06F11/10 , G06F3/06 , G06F12/02
CPC分类号： G11C29/04 , G06F3/06 , G06F3/0613 , G06F3/0659 , G06F3/0688 , G06F11/108 , G06F11/1096 , G06F12/0246 , G06F2212/262 , G06F2212/7208
摘要： Provided is a control device for managing a plurality of memory channels driven through multichannel interleaving. The apparatus includes a stripe configuring unit for configuring a stripe according to a physical number of pages included in the plurality of memory channels, and a parity generating unit for generating parity data on the configured stripe.
摘要翻译：提供了一种用于管理通过多通道交织驱动的多个存储器通道的控制装置。该装置包括：条带配置单元，用于根据多个存储信道中包括的物理页数来配置条带;以及奇偶校验生成单元，用于在所配置的条带上生成奇偶校验数据。

4. 发明授权

US08009784B2 Clock embedded differential data receiving system for ternary lines differential signaling 有权
标题翻译：用于三线差分信号的时钟嵌入式差分数据接收系统
公开(公告)号：US08009784B2
公开(公告)日：2011-08-30
申请号：US12022248
申请日：2008-01-30
申请人： Jae Gan Ko
发明人： Jae Gan Ko
IPC分类号： H04L7/02
CPC分类号： H04L7/0008 , H04L7/0037 , H04L7/0337 , H04L25/0272
摘要： A clock embedded differential data receiving system for ternary lines differential signaling. The clock embedded differential data receiving system includes a monitoring portion which monitors voltage levels of first, second and third transfer signals to generate a clock signal, a first pre-data and a second pre-data, a data generating portion which detects the first pre-data and the second pre-data in response to a sampling control signal, and generates an output data group with decoding of the first pre-data and the second pre-data, and a timing controller to delay the transition time point of the clock signal with a delay phase which generates the sampling control signal.
摘要翻译：用于三线差分信号的时钟嵌入式差分数据接收系统。时钟嵌入式差分数据接收系统包括：监视部分，其监测第一，第二和第三传送信号的电压电平以产生时钟信号;第一预数据和第二预数据;数据产生部分，其检测第一预先数据和第二预数据，并且产生具有第一预数据和第二预数据的解码的输出数据组，以及定时控制器，用于延迟时钟的转变时间点信号具有产生采样控制信号的延迟相位。

5. 发明申请

US20090195266A1 HIGH VOLTAGE STRESS TEST CIRCUIT 有权
标题翻译：高压应力测试电路
公开(公告)号：US20090195266A1
公开(公告)日：2009-08-06
申请号：US12352812
申请日：2009-01-13
申请人： Yong Weon Jeon
发明人： Yong Weon Jeon
IPC分类号： H03K19/00 , H03K19/0175
CPC分类号： H03K3/35613 , G01R31/3004
摘要： A high voltage stress test circuit includes an internal data generation unit for generating internal data and inverted internal data, and a level shifter for receiving the internal data and the inverted internal data and for generating digital data and inverted digital data. In a normal mode, the internal data and the inverted internal data have logic states corresponding to input data, while the digital data and the inverted digital data have logic states corresponding to the internal data and the inverted internal data. In a high voltage stress test mode, the internal data and the inverted internal data have predetermined logic states regardless of a logic state of the input data, while the digital data and the inverted digital data have predetermined logic states regardless of logic states of the internal data and the inverted internal data.
摘要翻译：高电压应力测试电路包括用于产生内部数据和反相内部数据的内部数据产生单元，以及用于接收内部数据和反相内部数据并用于产生数字数据和反相数字数据的电平转换器。在正常模式下，内部数据和反转的内部数据具有与输入数据对应的逻辑状态，而数字数据和反相数字数据具有与内部数据和反转的内部数据相对应的逻辑状态。在高压应力测试模式中，无论输入数据的逻辑状态如何，内部数据和反相内部数据都具有预定的逻辑状态，而数字数据和反相数字数据具有预定的逻辑状态，而不管内部的逻辑状态如何数据和反向内部数据。

6. 发明授权

US07521977B2 Voltage-controlled oscillator generating output signal finely tunable in wide frequency range and variable delay circuits included therein 有权
标题翻译：产生输出信号的压控振荡器可在宽频率范围内精细调节，其中包括可变延迟电路
公开(公告)号：US07521977B2
公开(公告)日：2009-04-21
申请号：US11776684
申请日：2007-07-12
申请人： Jae Gan Ko
发明人： Jae Gan Ko
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00065 , H03K2005/00221 , H03L7/0995
摘要： A voltage-controlled oscillator includes a plurality of variable delay circuits, wherein a first differential output signal of an adjacent previous stage is provided as a first differential input signal and a second differential output signal of a second previous stage is provided as a second differential input signal. Each variable delay circuit includes a loading circuit including first and second loading units, a first input circuit including first and second input transistors gated by the first differential input signal, a second input circuit including third and fourth input transistors gated by the second differential input signal, first and second current sources connected between a first common node and a second power source and in electrical parallel with each other, and third and fourth current sources connected between a second common node and the second power source and in electrical parallel with each other.
摘要翻译：压控振荡器包括多个可变延迟电路，其中相邻前一级的第一差分输出信号被提供为第一差分输入信号，并且第二前级的第二差分输出信号被提供为第二差分输入信号。每个可变延迟电路包括一个包括第一和第二加载单元的加载电路，包括由第一差分输入信号选通的第一和第二输入晶体管的第一输入电路，包括由第二差分输入信号选通的第三和第四输入晶体管的第二输入电路连接在第一公共节点和第二电源之间并且彼此电并联的第一和第二电流源，以及连接在第二公共节点和第二电源之间并彼此电并联的第三和第四电流源。

7. 发明申请

US20080272818A1 VOLTAGE-CONTROLLED OSCILLATOR GENERATING OUTPUT SIGNAL FINELY TUNABLE IN WIDE FREQUENCY RANGE AND VARIABLE DELAY CIRCUITS INCLUDED THEREIN 有权
标题翻译：电压控制振荡器产生输出信号在宽频范围内和可变延迟电路中包含的精确电压
公开(公告)号：US20080272818A1
公开(公告)日：2008-11-06
申请号：US11776684
申请日：2007-07-12
申请人： Jae Gan KO
发明人： Jae Gan KO
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03K2005/00065 , H03K2005/00221 , H03L7/0995
摘要： A voltage-controlled oscillator includes a plurality of variable delay circuits, wherein a first differential output signal of an adjacent previous stage is provided as a first differential input signal and a second differential output signal of a second previous stage is provided as a second differential input signal. Each variable delay circuit includes a loading circuit including first and second loading units, a first input circuit including first and second input transistors gated by the first differential input signal, a second input circuit including third and fourth input transistors gated by the second differential input signal, first and second current sources connected between a first common node and a second power source and in electrical parallel with each other, and third and fourth current sources connected between a second common node and the second power source and in electrical parallel with each other.
摘要翻译：压控振荡器包括多个可变延迟电路，其中相邻前一级的第一差分输出信号被提供为第一差分输入信号，并且第二前级的第二差分输出信号被提供为第二差分输入信号。每个可变延迟电路包括一个包括第一和第二加载单元的加载电路，包括由第一差分输入信号选通的第一和第二输入晶体管的第一输入电路，包括由第二差分输入信号选通的第三和第四输入晶体管的第二输入电路连接在第一公共节点和第二电源之间并且彼此电并联的第一和第二电流源，以及连接在第二公共节点和第二电源之间并彼此电并联的第三和第四电流源。

8. 发明授权

US10950185B2 Organic light-emitting display device having degradation compensation 有权
公开(公告)号：US10950185B2
公开(公告)日：2021-03-16
申请号：US16827023
申请日：2020-03-23
申请人： TLI Inc.
发明人： Jae Gan Ko , Ju Hyun Park
IPC分类号： G09G3/3233 , G09G3/3291 , G09G3/00
摘要： An organic light-emitting display (OLED) device includes an image display member, an aging display member, a degradation compensation control member for compensating for degradation of original image data of display pixels of the image display member. Aging pixels of the aging display member are degraded by reflecting image driving data of the display pixels, and the degradation of the original image data is compensated depending on degradation confirmation values of standard cumulative stress indexes corresponding to cumulative stress of the display pixels. The degree of degradation of the pixels may be accurately reflected while having a high aperture ratio, so that effective degradation compensation may be performed.

9. 发明授权

US08373634B2 Source driver for display devices 有权
标题翻译：显示设备的源驱动程序
公开(公告)号：US08373634B2
公开(公告)日：2013-02-12
申请号：US12464160
申请日：2009-05-12
申请人： Yong Weon Jeon
发明人： Yong Weon Jeon
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/3614 , G09G2310/027 , G09G2310/0297
摘要： A source driver for display devices includes line pair driving blocks. Each of the line pair driving blocks includes a de-multiplexing portion for de-multiplexing first and second digital data to generate first and second de-multiplexing data, a decoding portion for decoding the first and second de-multiplexing data to generate first and second analog data, and a multiplexing portion for multiplexing the first and second analog data to generate first and second gradation voltages. In the source driver, the de-multiplexing portion is controlled by signals having information of loading timing for the digital data and information of polarity for the gradation voltages.
摘要翻译：用于显示设备的源驱动器包括线对驱动块。每个线对驱动块包括用于解复用第一和第二数字数据以产生第一和第二解复用数据的解复用部分，用于解码第一和第二解复用数据以产生第一和第二解复用数据的解码部分模拟数据和多路复用部分，用于多路复用第一和第二模拟数据以产生第一和第二灰度电压。在源极驱动器中，解复用部分由具有数字数据的加载时序信息和灰度电压的极性信息的信号控制。

10. 发明授权

US08305129B2 Internal clock generating circuit and method for generating internal clock signal with data signal 有权
标题翻译：内部时钟发生电路和用于产生具有数据信号的内部时钟信号的方法
公开(公告)号：US08305129B2
公开(公告)日：2012-11-06
申请号：US12947458
申请日：2010-11-16
申请人： Jang Jin Nam , Yong Weon Jeon
发明人： Jang Jin Nam , Yong Weon Jeon
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G11C7/222 , G11C7/22 , H03K5/19 , H04L7/0331
摘要： An internal clock generating circuit and a method for generating an internal clock signal are disclosed. The internal clock generating circuit includes a transition detecting block for detecting transitions in a data signal and generating data transition information, and an internal clock generating block for generating and storing a period digital data while detecting the unit period of the data signal in a period confirming mode. In the internal clock generating circuit, the internal clock signal can be generated without the external clock signal, so that the internal clock generating circuit can be implemented with a simple constitution. Additionally, an extra locking time is not required for locking the extra clock signal, so that the operating speed of the internal clock generating circuit is improved. The internal clock signal is dependent on the data signal, so that it is easy to control the set-up and hold for data.
摘要翻译：公开了内部时钟发生电路和用于产生内部时钟信号的方法。内部时钟发生电路包括用于检测数据信号中的转变并产生数据转换信息的转移检测块，以及内部时钟产生模块，用于在周期数字数据的产生和存储的同时检测数据信号的单位周期模式。在内部时钟发生电路中，可以不经外部时钟信号产生内部时钟信号，从而能够以简单的结构实现内部时钟发生电路。此外，锁定额外的时钟信号不需要额外的锁定时间，从而提高了内部时钟发生电路的工作速度。内部时钟信号取决于数据信号，因此易于控制数据的设置和保持。

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