专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20180151239A1 Word Line Driver 审中-公开
公开(公告)号：US20180151239A1
公开(公告)日：2018-05-31
申请号：US15492156
申请日：2017-04-20
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Yuhsiang Chen , Shao-Yu Chou , Yu-Der Chih
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C8/08 , H03K3/012 , H03K3/356113 , H03K3/35613 , H03K3/356182
摘要： A word line driver comprising a select word line level shifter configured to generate at least one output signal in the first voltage domain or a second voltage domain and a control word line level shifter coupled to the select word line level shifter and configured to generate at least one output signal in the second voltage domain or a third voltage domain based, at least in part, on the at least one output signal generated by the select word line level shifter.

2. 发明授权

US09929722B1 Wire capacitor for transmitting AC signals 有权
公开(公告)号：US09929722B1
公开(公告)日：2018-03-27
申请号：US15419236
申请日：2017-01-30
申请人： International Business Machines Corporation
发明人： David M. Friend , Grant P. Kesselring , Christopher W. Steffen , James D. Strom
IPC分类号： H03L7/06 , H03K3/037 , H01L23/66 , H01L23/522 , H01L23/528 , H03L7/099
CPC分类号： H03K3/037 , H01L23/5223 , H01L23/5226 , H01L23/528 , H01L23/66 , H01L2223/6611 , H01L2223/6616 , H01L2223/6627 , H03K3/35613 , H03L7/099
摘要： Embodiments herein describe a transmission line used to carry an AC signal (e.g., a high-speed clock signal) between two different voltage domains in an IC. Instead of dividing the transmission line into multiple segments each with a buffer, in one embodiment the transmission line is arranged to form a capacitor. That is, the conductive material forming the transmission line is arranged in the IC to result in a desired capacitance. This capacitance can be used to replace a discrete capacitor that would otherwise be used with a buffer (e.g., level shifter) located at the end of the transmission line for converting the AC signal from a first voltage domain to a second voltage domain.

3. 发明授权

US09859893B1 High speed voltage level shifter 有权
公开(公告)号：US09859893B1
公开(公告)日：2018-01-02
申请号：US15367706
申请日：2016-12-02
申请人： QUALCOMM Incorporated
发明人： Venkat Narayanan , Rakesh Vattikonda , De Lu , Ramaprasath Vilangudipitchai , Samrat Sinharoy , Rui Chen
IPC分类号： H03K3/35 , H03K19/00 , G09G3/20 , H03K19/0185 , H03K3/356
CPC分类号： H03K19/018521 , H03K3/012 , H03K3/356113 , H03K3/35613 , H03K3/356182 , H03K19/0013
摘要： In one embodiment, a voltage level shifter includes a first NOR gate having a first input configured to receive a first input signal in a first power domain, a second input configured to receive an enable signal in a second power domain, a third input, and an output. The voltage level shifter also includes a second NOR gate having a first input configured to receive a second input signal in the first power domain, a second input configured to receive the enable signal in the second power domain, a third input coupled to the output of the first NOR gate, and an output coupled to the third input of the first NOR gate. The first and second NOR gates are powered by a supply voltage of the second power domain.

4. 发明授权

US09722585B2 Circuit and method to extend a signal comparison voltage range 有权
公开(公告)号：US09722585B2
公开(公告)日：2017-08-01
申请号：US15144929
申请日：2016-05-03
申请人： QUALCOMM Incorporated
发明人： Jeremy Goldblatt
IPC分类号： H03K5/00 , H03K3/356 , H03K3/012 , H03K19/00 , H03K5/24
CPC分类号： H03K3/35613 , H03K3/012 , H03K3/356139 , H03K5/00 , H03K5/2481 , H03K5/249 , H03K19/0016
摘要： A circuit to a extend signal comparison voltage range includes a latching circuit and a comparator responsive to common-mode input signals. The comparator is coupled to the latching circuit and to a dynamic node. The circuit also includes a clocked boost circuit coupled to the dynamic node. The clocked boost circuit is configured to extend a supply voltage range of the comparator via biasing the dynamic node. A method to extend a signal comparison voltage range includes selectively shifting a voltage level of one of a ground reference of a dynamic circuit or a supply reference of the dynamic circuit in response to a clock signal.

5. 发明授权

US09621136B1 Data sampler circuit with equalization function and method for sampling data 有权
公开(公告)号：US09621136B1
公开(公告)日：2017-04-11
申请号：US14939273
申请日：2015-11-12
申请人： FREESCALE SEMICONDUCTOR, INC.
发明人： Kevin Yi Cheng Chang
IPC分类号： H04L27/08 , H03K3/356 , H04B1/12
CPC分类号： H03K3/35613 , H03K3/356139 , H03L7/091 , H04B1/123
摘要： A data sampler circuit comprises a transconductance amplifier, a latch circuit, a current-to-voltage converter, and a negative resistance circuit. The transconductance amplifier has an input and an output. The latch circuit is coupled to the output of the transconductance amplifier. The current-to-voltage converter has an input coupled to the output of the transconductance amplifier, and an output for providing a feedback signal to the latch circuit. The negative resistance circuit is coupled to the output of the transconductance amplifier and provides equalization during both a sampling mode and a data latching mode. In one embodiment, the negative resistance circuit comprises a pair of cross-coupled transistors. A gain of the negative resistance circuit can be adjusted based on a pulse width of an input signal.

6. 发明授权

US09608604B2 Voltage level shifter with single well voltage 有权
公开(公告)号：US09608604B2
公开(公告)日：2017-03-28
申请号：US11639006
申请日：2006-12-14
申请人： Lee-Chung Lu , Chung-Hsing Wang , Chun-Hui Tai , Li-Chun Tien , Shun-Li Chen
发明人： Lee-Chung Lu , Chung-Hsing Wang , Chun-Hui Tai , Li-Chun Tien , Shun-Li Chen
IPC分类号： H03L5/00 , H03K3/356
CPC分类号： H03K3/35613
摘要： This invention discloses a voltage level shifter, which comprises a first P-type metal-oxide-semiconductor (PMOS) transistor having a gate, a source and a bulk coupled to an input terminal, a first positive voltage power supply and a second positive voltage power supply, respectively, and a second PMOS transistor having a source, a drain and a bulk coupled to a third positive voltage power supply, an output node and the second positive voltage power supply, respectively, wherein the first and second PMOS transistors are formed in a single Nwell.

7. 发明授权

US09490813B2 High-speed level-shifting multiplexer 有权
标题翻译：高速电平转换复用器
公开(公告)号：US09490813B2
公开(公告)日：2016-11-08
申请号：US14534967
申请日：2014-11-06
申请人： QUALCOMM Incorporated
发明人： Kevin Robert Bowles , Jose Gabriel Corona , Venugopal Boynapalli
IPC分类号： H03K7/00 , H03L5/00 , H03K19/0185 , H03K3/356 , H03K17/00
CPC分类号： H03K19/018528 , H03K3/35613 , H03K17/002 , H03K17/005 , H03K19/018507
摘要： Systems and methods for level-shifting multiplexing are described herein. In one embodiment, a method for level-shifting multiplexing comprises selecting one of a plurality of inputs based on one or more select signals, and pulling down one of first and second nodes based on a logic state of the selected one of the plurality of inputs. The method also comprises pulling up the first node if the second node is pulled down, and pulling up the second node if the first node is pulled down.
摘要翻译：本文描述了用于电平转换复用的系统和方法。在一个实施例中，一种用于电平转换复用的方法包括：基于一个或多个选择信号选择多个输入中的一个，并且基于所述多个输入中所选择的一个输入的逻辑状态来下拉第一和第二节点中的一个。该方法还包括如果第二节点被拉下来则拉起第一节点，并且如果第一节点被拉下来则提起第二节点。

8. 发明授权

US09484922B2 Voltage level shifter module 有权
标题翻译：电压电平移位器模块
公开(公告)号：US09484922B2
公开(公告)日：2016-11-01
申请号：US14516656
申请日：2014-10-17
申请人： Andrey Evgenevich Malkov
发明人： Andrey Evgenevich Malkov
IPC分类号： H03K19/018 , H03K19/0185 , H03K3/356 , H03K5/06 , H03K5/15 , H03K5/1534
CPC分类号： H03K19/018507 , H03K3/35613 , H03K5/06 , H03K5/15 , H03K5/15086 , H03K5/1534
摘要： A voltage level shifter module comprising at least one input arranged to receive an input signal, and at least one cascode transistor arranged to receive at a gate thereof at least one reference voltage signal. The voltage level shifter module further comprises at least one reference voltage control component arranged to detect logical state transitions within the input signal from at least a first logical state to a second logical state, and cause the reference voltage signal applied to the gate of the at least one cascode transistor to be pulled down to a reduced voltage upon detection of a logical state transition within the input signal from at least a first logical state to a second logical state.
摘要翻译：电压电平移位器模块，包括布置成接收输入信号的至少一个输入端和至少一个共源共栅晶体管，其布置成在其栅极处接收至少一个参考电压信号。电压电平移位器模块还包括至少一个参考电压控制部件，被配置为检测来自至少第一逻辑状态到第二逻辑状态的输入信号内的逻辑状态转换，并且使施加到at的门的参考电压信号在从至少第一逻辑状态到第二逻辑状态的输入信号中检测到逻辑状态转换时，至少一个共源共栅晶体管被下拉至降低的电压。

9. 发明申请

US20160307621A1 Integrated Circuit With Separate Supply Voltage For Memory That Is Different From Logic Circuit Supply Voltage 审中-公开
公开(公告)号：US20160307621A1
公开(公告)日：2016-10-20
申请号：US15133400
申请日：2016-04-20
申请人： Apple Inc.
发明人： Brian J. Campbell , Vincent R. von Kaenel , Daniel C. Murray , Gregory S. Scott , Sribalan Santhanam
IPC分类号： G11C11/419 , H03K19/0185 , H03K3/356
CPC分类号： G11C11/419 , G11C5/143 , G11C7/00 , G11C7/12 , G11C8/08 , G11C11/417 , H03K3/35613 , H03K19/018528
摘要： In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

10. 发明授权

US09419593B2 Current mode logic circuit for high speed input/output applications 有权
标题翻译：用于高速输入/输出应用的电流模式逻辑电路
公开(公告)号：US09419593B2
公开(公告)日：2016-08-16
申请号：US14507995
申请日：2014-10-07
申请人： Kevin Yi Cheng Chang
发明人： Kevin Yi Cheng Chang
IPC分类号： H03K3/356
CPC分类号： H03K3/35613 , H03K19/0826
摘要： A CML latch includes an input stage including input nodes to receive a differential input signal and output nodes to provide a differential intermediate output signal, and a negative output node to provide a negative side of the differential intermediate output signal, a negative resistance stage including an input node connected to a first voltage source and output nodes connected to the output nodes of the input stage, and a latch stage including input nodes connected to the output nodes of the input stage and output nodes to provide a differential output signal. The negative resistance stage increases a current gain of the input stage.
摘要翻译： CML锁存器包括输入级，包括用于接收差分输入信号的输入节点和输出节点以提供差分中间输出信号，以及负输出节点以提供差分中间输出信号的负侧，负电阻级包括连接到第一电压源的输入节点和连接到输入级的输出节点的输出节点，以及包括连接到输入级的输出节点的输入节点和输出节点以提供差分输出信号的锁存级。负电阻级增加输入级的电流增益。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式