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1. 发明授权

US10250273B2 Band specific interleaving mismatch compensation in RF ADCs 有权
公开(公告)号：US10250273B2
公开(公告)日：2019-04-02
申请号：US15791538
申请日：2017-10-24
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Sthanunathan Ramakrishnan , Sashidharan Venkatraman , Chandrasekhar Sriram , Jawaharlal Tangudu
IPC分类号： H03M1/08 , H03M1/10 , H03M1/12
摘要： An integrated circuit chip includes an interleaved analog-to-digital converter (ADC) and an interleaving calibration circuit. The interleaved ADC includes a plurality of ADCs that are each configured to sample an analog signal. The interleaved ADC is configured to convert the analog signal into an interleaved analog-to-digital signal (IADC signal) that includes a plurality of spurious signals formed from mismatches between the plurality of ADCs. The interleaving calibration circuit is configured to receive the IADC signal from the interleaved ADC, generate a mismatch profile estimate corresponding to the plurality of spurious signals to generate one or more mismatch profile estimates, determine whether a first mismatch profile estimate is in a frequency band of interest, and, in response to a determination that the first mismatch profile estimate is in the frequency band of interest, generate a set of model parameters based on the first mismatch profile estimate.

2. 发明授权

US10014957B2 High speed isolated and optical USB 有权
公开(公告)号：US10014957B2
公开(公告)日：2018-07-03
申请号：US15067410
申请日：2016-03-11
申请人： Texas Instruments Incorporated
发明人： Win N. Maung , Suzanne M. Vining
IPC分类号： H04B10/80 , H04B10/29 , H04L12/40 , G06F13/40 , H04B10/25
CPC分类号： H04B10/802 , G06F13/4068 , H04B10/25 , H04B10/29 , H04L12/40032 , H04L12/40039
摘要： A system and method are disclosed for providing electrically isolated communications between two USB2 devices. Two isolating eUSB2 repeaters are utilized to implement a digital isolation barrier between the two USB2 devices. The isolating eUSB2 repeaters are configured to broker isolated communications between the two USB2 devices using a modified eUSB2 protocol that allows the two isolating eUSB2 repeaters to interoperate across the isolating barrier. The modified eUSB2 protocol allows the two isolating eUSB2 repeaters to broker isolating communications on behalf of the USB2 devices without the use of an accurate clock signal. The modified eUSB2 protocol utilized by the isolating eUSB2 repeaters is configured in particular to support certain end-of-packet translations between USB2 data and the modified eUSB2 protocol, management of certain USB2 bus state transitions and assignment of roles to the two isolating eUSB2 repeaters.

3. 发明授权

US09076891B2 Integrated circuit (“IC”) assembly includes an IC die with a top metallization layer and a conductive epoxy layer applied to the top metallization layer 有权
标题翻译：集成电路（“IC”）组件包括具有顶部金属化层和施加到顶部金属化层的导电环氧树脂层的IC管芯
公开(公告)号：US09076891B2
公开(公告)日：2015-07-07
申请号：US13754513
申请日：2013-01-30
申请人： Texas Instruments Incorporated
发明人： Osvaldo Jorge Lopez , Jonathan Almeria Noquil , Juan Herbsommer
IPC分类号： H01L23/00 , H01L23/495
CPC分类号： H01L24/49 , H01L23/28 , H01L23/4952 , H01L23/49562 , H01L23/49811 , H01L23/49838 , H01L23/49861 , H01L23/49883 , H01L24/06 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/83 , H01L24/85 , H01L2224/04042 , H01L2224/05078 , H01L2224/05573 , H01L2224/0603 , H01L2224/29026 , H01L2224/29139 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48464 , H01L2224/49111 , H01L2224/4912 , H01L2224/49175 , H01L2224/73265 , H01L2224/83851 , H01L2224/85205 , H01L2224/8592 , H01L2924/01047 , H01L2924/0665 , H01L2924/07811 , H01L2924/15747 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/20751 , H01L2924/00015
摘要： An integrated circuit (“IC”) assembly includes an IC die with a metallization layer on a top surface thereof. A plurality of lead wires are bonded at first end portions thereof to the metallization layer. A conductive layer is attached to the metallization layer and covers the first ends of the lead wires.
摘要翻译：集成电路（“IC”）组件包括其顶表面上具有金属化层的IC管芯。多个引线在其第一端部处接合到金属化层。导电层附接到金属化层并覆盖引线的第一端。

4. 发明申请

US20130234795A1 FREE-FLY CLASS D POWER AMPLIFIER 有权
标题翻译：自由飞行类D功率放大器
公开(公告)号：US20130234795A1
公开(公告)日：2013-09-12
申请号：US13416841
申请日：2012-03-09
申请人： Joonhoi Hur , Lei Ding , Rahmi Hezar , Baher S. Haroun
发明人： Joonhoi Hur , Lei Ding , Rahmi Hezar , Baher S. Haroun
IPC分类号： H03F3/217
CPC分类号： H03F3/2173 , H03F1/56 , H03F2200/387
摘要： A method is provided. A first enable signal is asserted so as to enable a first driver, where the first driver has a first output and a first parasitic capacitance. A second enable signal is asserted so as to enable a second driver, where the second driver has a second output and a second parasitic capacitance. The first and second outputs are coupled together by a switching network when the second driver is enabled. Pulses from complementary first and second radio frequency (RF) signals are applied to the first driver, where there is a first set of free-fly intervals between consecutive pulses from the first and second RF signals, and pulses from complementary third and fourth RF signals are applied to the second driver, wherein there is a second set of free-fly interval between consecutive pulses from the third and fourth RF signals.
摘要翻译：提供了一种方法。第一使能信号被确定为使第一驱动器能够使第一驱动器具有第一输出和第一寄生电容。第二使能信号被确定为使第二驱动器能够启动，其中第二驱动器具有第二输出和第二寄生电容。当第二驱动器被使能时，第一和第二输出由交换网络耦合在一起。来自互补第一和第二射频（RF）信号的脉冲被施加到第一驱动器，其中在来自第一和第二RF信号的连续脉冲之间存在第一组自由飞行间隔，以及来自互补的第三和第四RF信号的脉冲被施加到第二驱动器，其中在来自第三和第四RF信号的连续脉冲之间存在第二组自由间隔。

5. 发明授权

US06881100B2 Modular socket 有权
标题翻译：模块化插座
公开(公告)号：US06881100B2
公开(公告)日：2005-04-19
申请号：US10270763
申请日：2002-10-15
申请人： John Brett Barry , Michael G. Amaro , Mark Daniel Fleszewski
发明人： John Brett Barry , Michael G. Amaro , Mark Daniel Fleszewski
IPC分类号： H01R9/24 , H01R13/514 , H01R13/502 , H01R9/22 , H01R13/1514
CPC分类号： H01R13/514 , H01R9/2408 , H01R12/716
摘要： A socket for receiving a line of contact pins is formed of modules connected together. The modules have three, four or five pin receiving openings and are joined to one another by dovetail connectors to form an elongated body having the desired number of pin receiving openings. Contacts are provided in the pin receiving openings to electrically connect with the pins. The modules have a ledge on which rests a work surface.
摘要翻译：用于接收接触针线的插座由连接在一起的模块形成。模块具有三个，四个或五个销接收开口，并且通过燕尾连接器彼此连接以形成具有所需数量的销接收开口的细长主体。触头设置在销接收开口中以与销电连接。模块有一个突出部，其上安置有工作台面。

6. 发明授权

US10396852B2 Long preamble and duty cycle based coexistence mechanism for power line communication (PLC) networks 有权
公开(公告)号：US10396852B2
公开(公告)日：2019-08-27
申请号：US15946041
申请日：2018-04-05
申请人： Texas Instruments Incorporated
发明人： Kumaran Vijayasankar , Ramanuja Vedantham , Tarkesh Pande
IPC分类号： H04B3/54
摘要： Embodiments of methods and systems for supporting coexistence of multiple technologies in a Power Line Communication (PLC) network are disclosed. A long coexistence preamble sequence may be transmitted by a device that has been forced to back off the PLC channel multiple times. The long coexistence sequence provides a way for the device to request channel access from devices on the channel using other technology. The device may transmit a data packet after transmitting the long coexistence preamble sequence. A network duty cycle time may also be defined as a maximum allowed duration for nodes of the same network to access the channel. When the network duty cycle time occurs, all nodes will back off the channel for a duty cycle extended inter frame space before transmitting again. The long coexistence preamble sequence and the network duty cycle time may be used together.

7. 发明授权

US10033341B2 Programmable impedance network in an amplifier 有权
公开(公告)号：US10033341B2
公开(公告)日：2018-07-24
申请号：US15464091
申请日：2017-03-20
申请人： Texas Instruments Incorporated
发明人： Rajendrakumar Joish
IPC分类号： H03G1/00 , H03F3/45 , H04B1/10
摘要： The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input. A second transistor receives a second input. A plurality of impedance networks is coupled between the first transistor and the second transistor. At least one impedance network of the plurality of impedance networks includes a first impedance path and a second impedance path. The first impedance path is activated during single ended operation, and the second impedance path is activated during differential operation.

8. 发明授权

US09373569B1 Flat no-lead packages with electroplated edges 有权
标题翻译：带电镀边缘的扁平无铅封装
公开(公告)号：US09373569B1
公开(公告)日：2016-06-21
申请号：US14842460
申请日：2015-09-01
申请人： Texas Instruments Incorporated
发明人： Reynaldo Corpuz Javier , Alok Kumar Lohia , Andy Quang Tran
IPC分类号： H01L21/44 , H01L23/495 , H01L21/48 , H01L21/56 , H01L21/78 , H01L23/31
CPC分类号： H01L23/49582 , H01L21/4821 , H01L21/561 , H01L23/293 , H01L23/3107 , H01L23/3675 , H01L23/49503 , H01L23/49541 , H01L23/49548 , H01L23/49568 , H01L23/49579 , H01L24/09 , H01L24/29 , H01L24/46 , H01L24/97 , H01L2224/2908 , H01L2224/29144 , H01L2224/29155 , H01L2224/29164 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48464 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/181 , H01L2924/1815 , H01L2924/19107 , H01L2924/00012 , H01L2224/45099
摘要： A method of forming packaged semiconductor devices includes providing a lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad and exposed back sides of the terminals. Partial sawing in saw lanes begins from the back side through the terminals terminating within the plastic encapsulation to provide exposed side walls of the terminals and of the plastic encapsulation. The exposed thermal pad and exposed back side of the terminals are all shorted together to form exposed electrically interconnected metal surfaces (interconnected surfaces). The interconnected surfaces are electroplated with a solder wetable metal or metal alloy plating layer. The interconnected surfaces are decoupled. A second sawing in the saw lanes finishes sawing through the plastic encapsulation to provide singulation, forming a plurality of packaged semiconductor devices.
摘要翻译：一种形成封装半导体器件的方法包括：提供一个平板无引线引线框架的引线框架片，其具有在芯片焊盘上的半导体管芯，端子和塑料封装，除了片材的背面以提供暴露的热管芯焊盘，暴露在终端的背面。锯条中的部分锯切从背面开始，通过终端在塑料封装内终止，以提供端子的暴露侧壁和塑料封装。端子的暴露的热垫和暴露的背面全部短接在一起形成暴露的电互连金属表面（互连表面）。互连的表面用可焊接的可润湿金属或金属合金镀层电镀。互连的表面是去耦的。在锯条中的第二次锯切完成了通过塑料封装的锯切，以提供单一化，形成多个封装的半导体器件。

9. 发明授权

US08792288B1 Nonvolatile logic array with built-in test drivers 有权
标题翻译：具有内置测试驱动器的非易失逻辑阵列
公开(公告)号：US08792288B1
公开(公告)日：2014-07-29
申请号：US13753800
申请日：2013-01-30
申请人： Texas Instruments Incorporated
发明人： Steven Craig Bartling , Sudhanshu Khanna
IPC分类号： G11C7/22 , G11C29/08
CPC分类号： G11C29/36 , G11C7/12 , G11C7/20 , G11C11/419 , G11C2029/1204
摘要： A system on chip (SoC) provides a nonvolatile memory array that is configured as n rows by m columns of bit cells. Each of the bit cells is configured to store a bit of data. There are m bit lines each coupled to a corresponding one of the m columns of bit cells. There are m write drivers each coupled to a corresponding one of the m bit lines, wherein the m drivers each comprise a write one circuit and a write zero circuit. The m drivers are operable to write all ones into a row of bit cells in response to a first control signal coupled to the write one circuits and to write all zeros into a row of bit cells in response to a second control signal coupled to the write zero circuits.
摘要翻译：片上系统（SoC）提供非易失性存储器阵列，其配置为n行x位的位单元。每个位单元被配置为存储一位数据。存在m个位线，每个位线耦合到位单元的m列的相应一个。存在m个写入驱动器，每个m个驱动器都耦合到m个位线中的对应的一个，其中m个驱动器各自包括写入一个电路和写入零电路。响应于耦合到写入一个电路的第一控制信号并且响应于耦合到写入的第二控制信号将全零写入位单元行中，m个驱动器可操作以将所有的一个写入一行位单元零电路。

10. 发明申请

US20120235714A1 FREQUENCY SYNTHESIZER PRESCALER SCRAMBLING 有权
标题翻译：频率合成器预分频器
公开(公告)号：US20120235714A1
公开(公告)日：2012-09-20
申请号：US13051588
申请日：2011-03-18
申请人： Jan-Tore Marienborg , Per Torstein Røine
发明人： Jan-Tore Marienborg , Per Torstein Røine
IPC分类号： H03K21/00
CPC分类号： H03K21/00 , H03K21/023 , H03K23/68
摘要： Various apparatuses, methods and systems for frequency dividing a clock signal are disclosed herein. For example, some embodiments of the present invention provide an apparatus including a plurality of multiplexers connected in series with the clock signal, each having a plurality of inputs of different phase delays. The apparatus also includes a delta sigma modulator connected to control inputs on the plurality of multiplexers. The delta sigma modulator is adapted to repeatedly select different ones of the pluralities of inputs of different phase delays in the plurality of multiplexers to change a divide ratio between the clock signal and an output of the plurality of multiplexers. The apparatus also includes a multiplexer usage accumulator connected to the delta sigma modulator to track usage of the plurality of multiplexers. The apparatus also includes a scrambler circuit connected between the delta sigma modulator and the control inputs on the plurality of multiplexers, adapted to control settings in the plurality of multiplexers based at least in part on the multiplexer usage accumulator.
摘要翻译：这里公开了用于对时钟信号进行分频的各种装置，方法和系统。例如，本发明的一些实施例提供一种装置，包括与时钟信号串联连接的多个多路复用器，每个具有不同相位延迟的多个输入。该装置还包括连接到多个多路复用器上的控制输入端的Δ-Σ调制器。 ΔΣ调制器适于重复地选择多个多路复用器中的不同相位延迟的多个输入的不同的输入，以改变时钟信号和多个多路复用器的输出之间的分频比。该装置还包括连接到Δ-Σ调制器以跟踪多个多路复用器的使用的多路复用器使用累加器。该装置还包括连接在Δ-Σ调制器与多个多路复用器之间的控制输入端的扰频电路，适于至少部分地基于多路复用器使用累加器来控制多个多路复用器中的设置。

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