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1. 发明申请

US20220057996A1 NON-VOLATILE COUNTER SYSTEM, COUNTER CIRCUIT AND POWER MANAGEMENT CIRCUIT WITH ISOLATED DYNAMIC BOOSTED SUPPLY 有权
公开(公告)号：US20220057996A1
公开(公告)日：2022-02-24
申请号：US17521019
申请日：2021-11-08
申请人： Texas Instruments Incorporated
发明人： Sudhanshu Khanna , Hao Meng , Michael Zwerg , Christy Leigh She , Steven Craig Bartling
IPC分类号： G06F7/62 , G06F1/30 , G06F1/26 , G08C13/02 , H03K5/24
摘要： Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

2. 发明授权

US11243903B2 Nonvolatile logic memory for computing module reconfiguration 有权
公开(公告)号：US11243903B2
公开(公告)日：2022-02-08
申请号：US16658928
申请日：2019-10-21
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Andreas Waechter , Mark Jung , Steven Craig Bartling , Sudhanshu Khanna
IPC分类号： G06F13/42 , G06F13/28 , H04L29/08
摘要： Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

3. 发明授权

US10037071B2 Compute through power loss approach for processing device having nonvolatile logic memory 有权
公开(公告)号：US10037071B2
公开(公告)日：2018-07-31
申请号：US14918133
申请日：2015-10-20
申请人： Texas Instruments Incorporated
发明人： Andreas Dannenberg , Brent Peterson , Aik K. Goh , Joerg Schreiner , Michael Zwerg , Steven Craig Bartling
IPC分类号： G06F1/00 , G06F1/32 , G06F12/02 , G06F9/4401
CPC分类号： G06F1/3275 , G06F1/3243 , G06F1/3287 , G06F9/4418 , G06F12/0246 , G06F2212/7203 , Y02D10/14 , Y02D10/152 , Y02D10/171 , Y02D10/44 , Y02D50/20
摘要： A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a software routine configured to be run by the CPU that effects saving to a non-volatile memory a state of the CPU and/or the device's peripherals before entering the deep low-power mode. The software routine can be configured to control this state storage in response to detecting a low power event, i.e., loss of power sufficient to run the CPU, or a software command to enter the deep low power mode to save power as part of an efficiency program. Then, upon wake up from the deep low power mode, the software routine is first run by the CPU to effect restoring from the non-volatile memory the state of the CPU and the peripherals before execution of a primary application for the central processing unit.

4. 发明申请

US20170109054A1 NONVOLATILE LOGIC MEMORY FOR COMPUTING MODULE RECONFIGURATION 审中-公开
公开(公告)号：US20170109054A1
公开(公告)日：2017-04-20
申请号：US14887885
申请日：2015-10-20
申请人： Texas Instruments Incorporated , Texas Instruments Deutschland GmbH
发明人： Andreas Waechter , Mark Jung , Steven Craig Bartling , Sudhanshu Khanna
IPC分类号： G06F3/06 , G06F13/28 , G06F13/42 , H04L29/08
CPC分类号： G06F13/4234 , G06F13/28 , H04L67/303
摘要： Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

5. 发明授权

US09454437B2 Non-volatile logic based processing device 有权
标题翻译：基于非易失性逻辑的处理器件
公开(公告)号：US09454437B2
公开(公告)日：2016-09-27
申请号：US14309362
申请日：2014-06-19
申请人： Texas Instruments Incorporated , Texas Instruments Deutschland GmbH
发明人： Andreas Waechter , Mark Jung , Steven Craig Bartling , Sudhanshu Khanna
IPC分类号： G06F11/00 , G06F11/14 , G06F9/44
CPC分类号： G06F11/1417 , G06F9/4401 , G06F9/4418 , G06F11/1469
摘要： A processing device boots or wakes using non-volatile logic element (NVL) array(s) that store a machine state. A standard boot sequence is used to restore a first portion of data. A second portion of data is restored, in parallel with the standard boot sequence, from the NVL array(s). A data corruption check is performed on the second portion of data. If the second data is valid, a standard boot sequence is used to restore a third portion of data. If the second data is invalid or the boot is an initial boot, a standard boot sequence is executed to determine the second portion of data, which is then stored in the NVL array(s). The processing device restores the second portion of the data during a portion of the boot/wake process that is not reading data from other non-volatile devices to avoid overloading the respective power domain.
摘要翻译：处理设备使用存储机器状态的非易失性逻辑元件（NVL）阵列引导或唤醒。标准引导顺序用于恢复数据的第一部分。数据的第二部分与标准引导序列并行地从NVL阵列恢复。对数据的第二部分执行数据损坏检查。如果第二个数据有效，则使用标准启动顺序恢复第三部分数据。如果第二数据无效或引导是初始引导，则执行标准引导序列以确定数据的第二部分，然后存储在NVL阵列中。处理设备在引导/唤醒处理的一部分期间恢复数据的第二部分，该部分未从其他非易失性设备读取数据，以避免相应的电源域超载。

6. 发明授权

US09335954B2 Customizable backup and restore from nonvolatile logic array 有权
标题翻译：从非易失性逻辑阵列进行可定制的备份和恢复
公开(公告)号：US09335954B2
公开(公告)日：2016-05-10
申请号：US13770448
申请日：2013-02-19
申请人： Texas Instruments Incorporated
发明人： Steven Craig Bartling , Sudhanshu Khanna
IPC分类号： G06F1/00 , G06F3/06 , G06F12/02 , G06F9/44 , G06F1/32 , G06F13/00 , G06F11/14 , G06F11/10
CPC分类号： G11C7/22 , G06F1/3203 , G06F1/3234 , G06F1/3275 , G06F1/3287 , G06F3/0679 , G06F3/0688 , G06F9/4401 , G06F9/4406 , G06F11/1032 , G06F11/1438 , G06F11/1469 , G06F12/0238 , G06F13/00 , G11C14/00 , H03K3/3562 , Y02D10/17 , Y02D10/171 , Y02D50/20
摘要： Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.
摘要翻译：处理设备的设计和操作可配置为在非易失性存储器恢复机器状态期间优化唤醒时间和峰值功耗成本。处理装置包括被配置为存储由处理装置的多个易失性存储元件表示的机器状态的多个非易失性逻辑元件阵列。将存储的机器状态从多个非易失性逻辑元件阵列读出到多个易失性存储元件。在制造期间，非易失性逻辑元件阵列中每行的数行和数位数是基于目标唤醒时间和峰值功率成本的。在另一种方法中，可以并行，顺序地或以任何组合来对数据进行数据写入或读取数据，以优化操作特性。

7. 发明授权

US09013218B2 Dual-port negative level sensitive reset data retention latch 有权
标题翻译：双端口负电平敏感复位数据保持锁存器
公开(公告)号：US09013218B2
公开(公告)日：2015-04-21
申请号：US14311831
申请日：2014-06-23
申请人： Texas Instruments Incorporated
发明人： Steven Craig Bartling , Sudhanshu Khanna
IPC分类号： H03K3/00 , H03K3/037
CPC分类号： H03K3/0375 , H03K3/356008
摘要： In an embodiment of the invention, a dual-port negative level sensitive reset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes low, CLKZ goes high, reset control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signal RET, the reset control signal REN and the control signals SS and SSN. The signals CKT, CLKZ, RET, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.
摘要翻译：在本发明的一个实施例中，双端口负电平敏感复位数据保持锁存器包括时钟反相器和双端口锁存器。当时钟信号CKT变低，CLKZ变为高电平，复位控制信号REN为高电平，保持控制信号RET为低电平时，数据由时钟反相器提供时钟。双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLKZ，保持控制信号RET，复位控制信号REN和控制信号SS和SSN。信号CKT，CLKZ，RET，REN，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。在保持模式期间，控制信号RET确定数据何时存储在双端口锁存器中。

8. 发明申请

US20150089293A1 Non-Volatile Logic Based Processing Device 有权
标题翻译：基于非易失性逻辑的处理器件
公开(公告)号：US20150089293A1
公开(公告)日：2015-03-26
申请号：US14309362
申请日：2014-06-19
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS DEUTSCHLAND GMBH
发明人： Andreas Waechter , Mark Jung , Steven Craig Bartling , Sudhanshu Khanna
IPC分类号： G06F11/14 , G06F9/44 , G06F12/02
CPC分类号： G06F11/1417 , G06F9/4401 , G06F9/4418 , G06F11/1469
摘要： A processing device boots or wakes using non-volatile logic element (NVL) array(s) that store a machine state. A standard boot sequence is used to restore a first portion of data. A second portion of data is restored, in parallel with the standard boot sequence, from the NVL array(s). A data corruption check is performed on the second portion of data. If the second data is valid, a standard boot sequence is used to restore a third portion of data. If the second data is invalid or the boot is an initial boot, a standard boot sequence is executed to determine the second portion of data, which is then stored in the NVL array(s). The processing device restores the second portion of the data during a portion of the boot/wake process that is not reading data from other non-volatile devices to avoid overloading the respective power domain.
摘要翻译：处理设备使用存储机器状态的非易失性逻辑元件（NVL）阵列引导或唤醒。标准引导顺序用于恢复数据的第一部分。数据的第二部分与标准引导序列并行地从NVL阵列恢复。对数据的第二部分执行数据损坏检查。如果第二个数据有效，则使用标准启动顺序恢复第三部分数据。如果第二数据无效或引导是初始引导，则执行标准引导序列以确定数据的第二部分，然后存储在NVL阵列中。处理设备在引导/唤醒处理的一部分期间恢复数据的第二部分，该部分未从其他非易失性设备读取数据，以避免相应的电源域超载。

9. 发明授权

US08854079B2 Error detection in nonvolatile logic arrays using parity 有权
标题翻译：使用奇偶校验的非易失性逻辑阵列中的错误检测
公开(公告)号：US08854079B2
公开(公告)日：2014-10-07
申请号：US13753856
申请日：2013-01-30
申请人： Texas Instruments Incorporated
发明人： Steven Craig Bartling , Sudhanshu Khanna
IPC分类号： H03K19/177 , G06F7/00 , H03K19/173
CPC分类号： H03K19/173
摘要： A system on chip (SoC) has a nonvolatile memory array of n rows by m columns coupled to one or more of the core logic blocks. M is constrained to be an odd number. Each time a row of m data bits is written, parity is calculated using the m data bits. Before storing the parity bit, it is inverted. Each time a row is read, parity is checked to determine if a parity error is present in the recovered data bits. A boot operation is performed on the SoC when a parity error is detected.
摘要翻译：片上系统（SoC）具有耦合到一个或多个核心逻辑块的n行m列的非易失性存储器阵列。 M被限制为奇数。每次写入一行m个数据位时，使用m个数据位来计算奇偶校验。在存储奇偶校验位之前，它被反转。每次读取一行时，检查奇偶校验以确定恢复的数据位中是否存在奇偶校验错误。当检测到奇偶校验错误时，在SoC上执行引导操作。

10. 发明申请

US20140075218A1 Nonvolatile Logic Array And Power Domain Segmentation In Processing Device 有权
标题翻译：非易失逻辑阵列和处理器件中的电源域分割
公开(公告)号：US20140075218A1
公开(公告)日：2014-03-13
申请号：US13770498
申请日：2013-02-19
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Steven Craig Bartling , Sudhanshu Khanna
IPC分类号： G06F1/32
CPC分类号： G11C7/22 , G06F1/3203 , G06F1/3234 , G06F1/3275 , G06F1/3287 , G06F3/0679 , G06F3/0688 , G06F9/4401 , G06F9/4406 , G06F11/1032 , G06F11/1438 , G06F11/1469 , G06F12/0238 , G06F13/00 , G11C14/00 , H03K3/3562 , Y02D10/17 , Y02D10/171 , Y02D50/20
摘要： A computing device includes a first set of non-volatile logic element arrays associated with a first function and a second set of non-volatile logic element arrays associated with a second function. The first and second sets of non-volatile logic element arrays are independently controllable. A first power domain supplies power to switched logic elements of the computing device, a second power domain supplies power to logic elements configured to control signals for storing data to or reading data from non-volatile logic element arrays, and a third power domain supplies power for the non-volatile logic element arrays. The different power domains are independently powered up or down based on a system state to reduce power lost to excess logic switching and the accompanying parasitic power consumption during the recovery of system state and to reduce power leakage to backup storage elements during regular operation of the computing device.
摘要翻译：计算设备包括与第一功能相关联的第一组非易失性逻辑元件阵列和与第二功能相关联的第二组非易失性逻辑元件阵列。第一组和第二组非易失性逻辑元件阵列是独立可控的。第一电源域向计算设备的交换逻辑元件供电，第二电源域为配置成控制用于将数据存储到非易失性逻辑单元阵列或从非易失性逻辑单元阵列读取数据的信号的逻辑元件供电，而第三电源域供电用于非易失性逻辑元件阵列。基于系统状态，不同的电源域被独立上电或下电，以减少在冗余逻辑切换期间的功率损耗以及在恢复系统状态期间伴随的寄生功率消耗，并且在计算的常规操作期间减少备用存储元件的功率泄漏设备。

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