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1. 发明授权

US11145575B2 Conductive bonding layer with spacers between a package substrate and chip 有权
公开(公告)号：US11145575B2
公开(公告)日：2021-10-12
申请号：US16677595
申请日：2019-11-07
申请人： UTAC Headquarters Pte. Ltd.
发明人： Tanawan Chaowasakoo , Hua Hong Tan , Alexander Lucero Laylo , Thanawat Jaengkrajarng
IPC分类号： H01L23/02 , H01L23/34 , H01L23/495 , H01L23/00 , H01L25/00 , H01L25/07 , H01L25/065 , H01L21/56 , H01L23/31
摘要： An embodiment related to a method for forming a device is disclosed. The method includes providing a package substrate having a first die attach pad (DAP) and a first bond pad, forming a first conductive die-substrate bonding layer on the first DAP, and attaching a first major surface of a first die to the first DAP. The first die includes a first die contact pad on a second major surface of the first die. A first conductive clip-die bonding layer with spacers is formed on the first die contact pad of the first die. A first conductive clip-substrate bonding layer is formed on the first bond pad of the package substrate. The method also includes attaching a first clip bond to the first die and the first bond pad. The first clip bond includes a first horizontal planar portion attached to the first die over the first die contact pad and a second vertical portion attached to the first bond pad.

2. 发明授权

US11114315B2 Chip packaging method and package structure 有权
公开(公告)号：US11114315B2
公开(公告)日：2021-09-07
申请号：US16805846
申请日：2020-03-02
申请人： PEP INNOVATION PTE. LTD.
发明人： Jimmy Chew
IPC分类号： H01L23/31 , H01L23/00 , H01L23/29 , H01L21/56
摘要： The present disclosure provides a chip packaging method and a package structure. The chip packaging method comprises: forming a protective layer having material properties on a die active surface of a die; attaching (such as adhering) the die in which the die active surface is formed with the protective layer onto a carrier, the die active surface facing the carrier, and a die back surface of the die facing away from the carrier; forming an encapsulation layer having material properties to encapsulate the die; removing (such as stripping off) the carrier to expose the protective layer; and forming a conductive layer and a dielectric layer. The chip packaging method reduces or eliminates warpage in the panel packaging process, lowers a requirement on an accuracy of aligning the die on the panel, reduces a difficulty in the panel packaging process, and makes the packaged chip structure more durable, and thus the present disclosure is especially suitable for large panel-level package and package of a thin chip with a large electric flux.

3. 发明授权

US11057285B2 Non-intrusive IT device monitoring and performing action based on IT device state 有权
公开(公告)号：US11057285B2
公开(公告)日：2021-07-06
申请号：US14947834
申请日：2015-11-20
申请人： ZPE Systems, Inc.
发明人： Arnaldo Zimmermann , Livio Ceci
IPC分类号： H04L12/26 , H04L12/24 , H04L29/08 , G06F9/455
摘要： Infrastructure management device(s) may monitor IT device(s) communicatively connected over a network. IT device state(s) may be determined for at least one of the IT device(s). Action(s) may be performed on one or more IT device(s), determined at least in part, by the state of the IT device(s).

4. 发明授权

US10923525B2 CMOS cap for MEMS devices 有权
公开(公告)号：US10923525B2
公开(公告)日：2021-02-16
申请号：US16809561
申请日：2020-03-05
申请人： Meridian Innovation Pte Ltd
发明人： Wan Chia Ang , Piotr Kropelnicki , Ilker Ender Ocak , Paul Simon Pontin
IPC分类号： H01L27/146 , H01L31/0224 , G01J5/16 , G01J5/08 , G01J5/12 , G01J5/04 , B81C1/00 , G01J5/02 , H01L31/09
摘要： A complementary metal oxide semiconductor (CMOS) device embedded with micro-electro-mechanical system (MEMS) components in a MEMS region. The MEMS components, for example, are infrared (IR) thermosensors. The device is encapsulated with a CMOS compatible IR transparent cap to hermetically seal the MEMS sensors in the MEMS region. The CMOS cap includes a base cap with release openings and a seal cap which seals the release openings.

5. 发明授权

US10693727B2 Non-intrusive device discovery and configuration cloning 有权
公开(公告)号：US10693727B2
公开(公告)日：2020-06-23
申请号：US14508572
申请日：2014-10-07
申请人： ZPE Systems, Inc.
发明人： Arnaldo Zimmermann , Livio Ceci
IPC分类号： H04L12/24 , H04L29/08 , H04L29/06 , G06F9/451 , G06F9/455
摘要： Infrastructure management device(s) may discover IT device(s) communicatively connected over a network. IT device information may be determined for at least one of the IT device(s). Configuration rule(s) compatible with IT device information may be matched to IT device(s). Action(s) may be performed on one or more device inventories, determined at least in part, by the configuration rule(s). Feature gap(s) for IT device(s) may be determined. IT device neutral user interface command(s) may be created.

6. 发明授权

US10679954B2 Integrated circuit system with carrier construction configuration and method of manufacture thereof 有权
公开(公告)号：US10679954B2
公开(公告)日：2020-06-09
申请号：US16117483
申请日：2018-08-30
申请人： EoPlex Limited
发明人： David G. Love , Philip Eugene Rogren
IPC分类号： H01L23/00 , H01L23/31
摘要： A method of manufacture of an integrated circuit system includes: providing a semiconductor wafer with a bond pad; attaching a detachable carrier to the semiconductor wafer, the detachable carrier including a carrier frame portion and a terminal structure; removing the carrier frame portion with the terminal structure attached to the semiconductor wafer; and forming an encapsulation encapsulating the semiconductor wafer, the bond pad, and the terminal structure.

7. 发明授权

US10665892B2 Lithium batteries with nano-composite positive electrode material 有权
公开(公告)号：US10665892B2
公开(公告)日：2020-05-26
申请号：US12522434
申请日：2008-01-11
申请人： Santhanam Raman , Shoufen Yang , Deepak Srivastava
发明人： Sujeet Kumar , Santhanam Raman , Shoufen Yang , Deepak Srivastava
IPC分类号： H01M10/0525 , H01M4/505 , H01M4/485 , H01M4/36 , B82Y30/00 , H01M4/525 , H01M4/62 , C01G51/00 , C01G45/12 , C01G53/00 , H01M4/02
摘要： Provided is a positive electrode for a lithium ion battery, the electrode comprising a nano-crystalline layered-layered composite structure of a material having the general formula xLi2MO3(1−x)LiM′O2 in which 0

8. 发明授权

US10566369B2 Image sensor with processor package 有权
公开(公告)号：US10566369B2
公开(公告)日：2020-02-18
申请号：US15839884
申请日：2017-12-13
申请人： UTAC Headquarters Pte. Ltd.
发明人： Tim Thian Hwee Tan , Boon Pek Liew , Chee Kay Chow , Teddy Joaquin Carreon
IPC分类号： H01L27/146 , H01L23/498 , H01L23/31 , H01L21/56 , H01L23/00
摘要： A semiconductor package and a method for forming a semiconductor package are disclosed. The semiconductor package includes a multi-layer package substrate having interconnect structures embedded therein. A sensor chip having an image sensing element is disposed on a top surface of the package substrate, and an integrated circuit is mounted to a bottom surface of the package substrate. The integrated circuit is a flip-chip assembly. The sensor chip is electrically connected to the integrated circuit. An adhesive material bonds a transparent covering member to the sensor chip to enclose the image sensing element.

9. 发明授权

US10378278B2 Smart ladder 有权
公开(公告)号：US10378278B2
公开(公告)日：2019-08-13
申请号：US15508931
申请日：2017-01-27
申请人： Sentron Engineering (S) Pte Ltd
发明人： Heng Hung Tang
IPC分类号： E06C1/20 , E06C1/18 , E06C1/393 , E06C7/00 , E06C7/42 , E06C7/50
摘要： Disclosed is a smart ladder. The smart ladder may be A-frame type of ladders, such as A-frame ladders and A-frame platform ladders. The smart ladder includes right and left outrigger leg units which are swiveled coupled to the right and left sides of the ladder to provide side support. The ladder includes brace units facilitate in folding and unfolding of the ladder as well as the outrigger legs. An electronic system, which includes a sensor network, a processor and a warning system, is provided. The sensor network senses side inclination angle of the ladder and side force on the outriggers and predict potential hazards from exceeding load and angle thresholds. This enhances safe operation of the ladder and avoids injuries to the user and others in the vicinity.

10. 发明授权

US10199572B2 Integrated magnetic random access memory with logic device 有权
公开(公告)号：US10199572B2
公开(公告)日：2019-02-05
申请号：US15164914
申请日：2016-05-26
申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.
发明人： Wanbing Yi , Yi Jiang , Daxiang Wang , Wei Shao , Juan Boon Tan
IPC分类号： H01L43/12 , H01L27/22
摘要： Device and methods of forming a device are disclosed. The method includes providing a substrate defined with at least first and second regions. A first dielectric layer is provided over the first and second regions of the substrate. The first dielectric layer corresponds to pre-metal dielectric (PMD) or CA level which comprises a plurality of contact plugs in the first and second regions. A first interlevel dielectric (ILD) layer is provided over the first dielectric layer. The first ILD layer accommodates a plurality of metal lines in M1 metal level in the first and second regions and via contact in V0 via level in the first region. A magnetic random access memory (MRAM) cell is formed in the second region. The MRAM cell includes a magnetic tunnel junction (MTJ) element sandwiched between the M1 metal level and CA level.

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