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1. 发明授权

US08694722B2 Memory systems 有权
标题翻译：内存系统
公开(公告)号：US08694722B2
公开(公告)日：2014-04-08
申请号：US13749046
申请日：2013-01-24
申请人： Micron Technology, Inc.
发明人： Sergey Anathlievich Gorobets , Alan David Bennet , Alan Welsh Sinclair
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/0613 , G06F3/0614 , G06F3/0616 , G06F3/064 , G06F3/0679 , G06F3/0688 , G06F2212/7201 , G06F2212/7203 , G06F2212/7211 , G11C16/102 , G11C16/349
摘要： Memory systems having a volatile memory, a non-volatile memory arranged in blocks, and a controller coupled to the volatile memory and to the non-volatile memory. The controller is configured to maintain, in the volatile memory, a list of addresses of erased blocks of the non-volatile memory. The list of addresses of erased blocks of the non-volatile memory is limited to a maximum number of list entries. The controller is further configured to transfer the list of addresses of erased blocks of the non-volatile memory from the volatile memory to the non-volatile memory in response to the list containing its maximum number of list entries and/or in response to an operation that would increase the number of list entries to a number equal to or greater than the maximum number of list entries.
摘要翻译：具有易失性存储器，布置成块的非易失性存储器的存储器系统和耦合到易失性存储器和非易失性存储器的控制器。控制器被配置为在易失性存储器中保持非易失性存储器的擦除块的地址列表。非易失性存储器的擦除块的地址列表被限制为列表条目的最大数目。控制器还被配置为响应于包含其最大数量的列表条目的列表和/或响应于操作而将非易失性存储器的擦除块的地址列表从易失性存储器传送到非易失性存储器这将使列表条目的数量增加到等于或大于列表条目的最大数目的数字。

2. 发明授权

US08693251B2 Processors for programming multilevel-cell NAND memory devices 有权
标题翻译：用于编程多电平单元NAND存储器件的处理器
公开(公告)号：US08693251B2
公开(公告)日：2014-04-08
申请号：US13413119
申请日：2012-03-06
申请人： Frankie F. Roohparvar
发明人： Frankie F. Roohparvar
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/3454
摘要： In an embodiment, a processor includes a storage device. The processor is configured to request first data from a first location of a memory device. The storage device is configured to receive and to store the first data from the memory device. The processor is configured to attempt to write second data to the first location of the memory device. The processor is configured to write the first data stored in the storage device and the second data to one or more other locations of the memory device if the attempt to write second data to the first location of the memory device fails.
摘要翻译：在一个实施例中，处理器包括存储设备。处理器被配置为从存储器设备的第一位置请求第一数据。存储设备被配置为从存储器设备接收和存储第一数据。处理器被配置为尝试将第二数据写入存储器件的第一位置。如果尝试将第二数据写入存储器件的第一位置，则处理器被配置为将存储在存储设备中的第一数据和第二数据写入存储器件的一个或多个其他位置。

3. 发明授权

US08686489B2 Memory with metal-insulator-metal tunneling program and erase 有权
标题翻译：记忆与金属绝缘体金属隧道程序和擦除
公开(公告)号：US08686489B2
公开(公告)日：2014-04-01
申请号：US11472785
申请日：2006-06-22
申请人： Leonard Forbes
发明人： Leonard Forbes
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273
摘要： The flash memory cell comprises a sense transistor that has a pair of source/drain lines and a control gate. A coupling metal-insulator-metal capacitor is created between the floating gate and a read wordline. A tunneling metal-insulator-metal capacitor is created between the floating gate and a write/erase bit line. In one embodiment, the insulator is a metal oxide.
摘要翻译：闪存单元包括具有一对源极/漏极线和控制栅极的检测晶体管。在浮动栅极和读取字线之间产生耦合金属 - 绝缘体 - 金属电容器。在浮动栅极和写/擦除位线之间产生隧道式金属 - 绝缘体 - 金属电容器。在一个实施例中，绝缘体是金属氧化物。

4. 发明授权

US08651798B2 Kinetic hydropower generation system and intake therefore 失效
标题翻译：因此动力水电发电系统和摄入量
公开(公告)号：US08651798B2
公开(公告)日：2014-02-18
申请号：US12466840
申请日：2009-05-15
申请人： Daryoush Allaei
发明人： Daryoush Allaei
IPC分类号： F03B17/06 , F03B15/20 , F03B13/10 , F03B13/12 , F03B13/26 , F03D7/04 , F03D11/04
CPC分类号： F03D1/04 , F03B11/02 , F03B17/061 , F03D9/257 , F05B2210/16 , F05B2240/13 , F05B2240/131 , F05B2240/97 , Y02E10/28 , Y02E10/38 , Y02E10/72
摘要： A kinetic hydropower generation system has a turbine and a generator coupled to the turbine. An underwater intake nozzle assembly is fluidly coupled to the turbine. For one embodiment, an underwater tower nozzle may be fluidly coupled between the turbine and the underwater intake nozzle assembly. The underwater intake nozzle assembly may include a collector and a converging nozzle.
摘要翻译：动力水力发电系统具有涡轮机和耦合到涡轮机的发电机。水下进气喷嘴组件流体地联接到涡轮机。对于一个实施例，水下塔式喷嘴可以流体地联接在涡轮机和水下进气喷嘴组件之间。水下进气喷嘴组件可以包括收集器和会聚喷嘴。

5. 发明授权

US08638632B2 Access line management in a memory device 有权
标题翻译：存储设备中的接入线管理
公开(公告)号：US08638632B2
公开(公告)日：2014-01-28
申请号：US12888765
申请日：2010-09-23
申请人： Benjamin Louie , Ali Mohammadzadeh , Aaron Yip
发明人： Benjamin Louie , Ali Mohammadzadeh , Aaron Yip
IPC分类号： G11C5/14
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26
摘要： Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.
摘要翻译：公开了存储器件和方法，诸如被配置为存储在对存储器件中的特定行存储器单元执行的存储器件操作期间要施加的多个访问线偏置模式的器件。存储器设备被进一步配置为支持所存储的偏置图案的修改，通过对存储在存储器件中的偏置图案的改变来偏置访问线路提供灵活性。方法和设备进一步便于在多个偏置条件下执行存储器件操作，以通过调整存储的偏压图案来评估和表征存储器件，而不需要对存储器件的相关联的硬件改变。

6. 发明授权

US08638624B2 Architecture and method for memory programming 有权
标题翻译：内存编程的架构和方法
公开(公告)号：US08638624B2
公开(公告)日：2014-01-28
申请号：US13561248
申请日：2012-07-30
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
IPC分类号： G11C7/00
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译：例如，公开了存储器，存储器件和系统的编程方法。在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。

7. 发明授权

US08595421B2 Flash memory architecture with separate storage of overhead and user data 有权
标题翻译：闪存体系结构，分开存储开销和用户数据
公开(公告)号：US08595421B2
公开(公告)日：2013-11-26
申请号：US13432763
申请日：2012-03-28
申请人： Petro Estakhri , Siamack Nemazie
发明人： Petro Estakhri , Siamack Nemazie
IPC分类号： G06F12/02 , G06F11/10 , H03M13/05
CPC分类号： G06F3/0605 , G06F3/0616 , G06F3/0631 , G06F3/064 , G06F3/0647 , G06F3/0679 , G06F12/0246 , G06F12/1009 , G06F2212/1036 , G06F2212/214 , G06F2212/657 , G06F2212/7201 , G06F2212/7204 , G06F2212/7211 , G11C16/102
摘要： A memory device has a plurality of dedicated data blocks for storing only user data and a plurality of dedicated overhead blocks for storing only overhead data that comprises ECC data that is used for error checking with respect to the user data in the dedicated data blocks. The dedicated data blocks can be erased without erasing the ECC data that is used for error checking with respect to the user data in the dedicated data blocks.
摘要翻译：存储器装置具有用于仅存储用户数据的多个专用数据块和用于仅存储用于相对于专用数据块中的用户数据进行错误检查的ECC数据的开销数据的多个专用开销块。可以擦除专用数据块而不擦除用于专用数据块中的用户数据的用于错误检查的ECC数据。

8. 发明授权

US08593876B2 Sensing scheme in a memory device 有权
标题翻译：存储设备中的感应方案
公开(公告)号：US08593876B2
公开(公告)日：2013-11-26
申请号：US13085611
申请日：2011-04-13
申请人： Violante Moschiano , Giovanni Santin , Tommaso Vali
发明人： Violante Moschiano , Giovanni Santin , Tommaso Vali
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C16/0483 , G11C16/26
摘要： Methods of operating memory devices, generating reference currents in memory devices, and sensing data states of memory cells in a memory device are disclosed. One such method includes generating reference currents utilized in sense amplifier circuitry to manage leakage currents while performing a sense operation within a memory device. Another such method activates one of two serially coupled transistors along with activating and deactivating the second transistor serially coupled with the first transistor thereby regulating a current through both serially coupled transistors and establishing a particular reference current.
摘要翻译：公开了在存储器件中操作存储器件，产生存储器件中的参考电流以及感测存储器单元的数据状态的方法。一种这样的方法包括产生在读出放大器电路中使用的参考电流，以在存储器件内进行感测操作的同时管理泄漏电流。另一种这样的方法激活两个串联耦合晶体管中的一个，同时激活和去激活与第一晶体管串联耦合的第二晶体管，从而调节通过两个串联耦合的晶体管的电流并建立特定的参考电流。

9. 发明授权

US08578244B2 Programming error correction code into a solid state memory device with varying bits per cell 有权
标题翻译：将错误纠正码编程成固态存储器件，每个单元具有不同位数
公开(公告)号：US08578244B2
公开(公告)日：2013-11-05
申请号：US13633158
申请日：2012-10-02
申请人： Micron Technology, Inc
发明人： Frankie F. Roohparvar , Vishal Sarin , Jung S. Hoei
IPC分类号： G11C29/00 , G11C5/14 , H03M13/00 , G06F11/00
CPC分类号： G06F11/1076 , G06F11/1072 , G11C29/12005
摘要： Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.
摘要翻译：在特定实施例中，存储设备接收和发送表示两个或多个位的位模式的模拟数据信号，以便于相对于传送指示各个位的数据信号的设备的数据传输速率的增加。编程错误校正码（ECC）和元数据到这种存储器设备中包括基于单元的实际错误率将ECC和元数据存储在每个小区的不同比特级。 ECC和元数据可以与数据块存储在与数据块不同的位级别。如果其中存储数据块的存储器区域不支持在特定位级别的ECC和元数据的期望的可靠性，则ECC和元数据可以以不同的位电平存储在存储器阵列的其他区域中。

10. 发明授权

US08572361B2 Configuration of a multilevel flash memory device 有权
标题翻译：配置多级闪存设备
公开(公告)号：US08572361B2
公开(公告)日：2013-10-29
申请号：US13048760
申请日：2011-03-15
申请人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
发明人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
IPC分类号： G06F9/24
CPC分类号： G11C11/5621 , G11C16/20
摘要： A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory. The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device. This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.
摘要翻译：多级闪存设备允许更快更有效地配置存储器设备的操作参数，以执行存储器的不同功能的算法。在测试期间识别存储器件的操作参数的最佳配置通过允许将配置位一次性处理成算法友好的数据来简化，该数据存储在嵌入式辅助随机存取存储器中，每次上电时存储设备。这通过执行存储在嵌入式微处理器的辅助只读存储器中的特定加电算法代码来完成。

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