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1. 发明申请

US20130039129A1 MEMORY DEVICES AND CONFIGURATION METHODS FOR A MEMORY DEVICE 有权
标题翻译：用于存储器件的存储器件和配置方法
公开(公告)号：US20130039129A1
公开(公告)日：2013-02-14
申请号：US13208802
申请日：2011-08-12
申请人： William H. RADKE , Tommaso Vali , Michele Incarnati
发明人： William H. RADKE , Tommaso Vali , Michele Incarnati
IPC分类号： G11C29/42 , G11C16/04
CPC分类号： G06F11/1048 , G06F3/0604 , G06F3/0608 , G06F3/0629 , G06F3/0631 , G06F3/064 , G06F3/0679 , G06F11/1068 , G06F11/1072 , G06F12/0207 , G06F12/0646 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C29/52
摘要： Memory devices and methods of operating memory devices are disclosed. In one such method, different blocks of memory cells have different configurations of user data space and overhead data space. In at least one method, overhead data is distributed within more than one block of memory cells. In another method, blocks are reconfigurable responsive to particular operating modes and/or desired levels of reliability of user data stored in a memory device.
摘要翻译：公开了存储器件和操作存储器件的方法。在一种这样的方法中，不同的存储器单元块具有用户数据空间和开销数据空间的不同配置。在至少一种方法中，开销数据分布在多于一个存储单元块内。在另一种方法中，可以响应于存储在存储器设备中的特定操作模式和/或用户数据的可靠性的期望级别重新配置块。

2. 发明授权

US08004892B2 Single latch data circuit in a multiple level cell non-volatile memory device 有权
标题翻译：单级锁存数据电路在多级单元非易失性存储器件中
公开(公告)号：US08004892B2
公开(公告)日：2011-08-23
申请号：US12632121
申请日：2009-12-07
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati
IPC分类号： G11C11/34
CPC分类号： G11C7/1051 , G11C7/106 , G11C11/5642 , G11C16/0483 , G11C16/28 , G11C2211/5642 , G11C2211/5647
摘要： A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.
摘要翻译：单个锁存电路耦合到多电平单元存储器件中的每个位线，以处理读取多个数据位。该电路由具有反向节点和非反相节点的锁存器组成。第一控制晶体管选择性地将非反相节点耦合到锁存器输出。第二控制晶体管选择性地将反相节点耦合到锁存器输出。复位晶体管耦合在反相节点和电路接地之间，以在晶体管导通时有选择地接地电路。

3. 发明申请

US20100259992A1 METHODS AND APPARATUS FOR PROGRAMMING A MEMORY CELL USING ONE OR MORE BLOCKING MEMORY CELLS 有权
标题翻译：用于编程使用一个或多个阻塞记忆细胞的记忆细胞的方法和装置
公开(公告)号：US20100259992A1
公开(公告)日：2010-10-14
申请号：US12820430
申请日：2010-06-22
申请人： Giovanni Santin , Michele Incarnati
发明人： Giovanni Santin , Michele Incarnati
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： Methods and apparatus for programming a memory cell using one or more blocking memory cells facilitate mitigation of capacitive voltage coupling. The methods include applying a program voltage to a selected memory cell of a string of memory cells, and applying a cutoff voltage to a set of one or more memory cells of the string between the selected memory cell and a select gate. The methods further include applying a pass voltage to one or more other memory cells of the string between the selected memory cell and the select gate. Other methods further include applying other pass voltages, other cutoff voltages and/or intermediate voltages to still other memory cells of the string.
摘要翻译：使用一个或多个阻塞存储器单元来编程存储器单元的方法和装置有助于缓解电容性电压耦合。所述方法包括将程序电压施加到存储器单元串的所选择的存储单元，以及将所述截止电压施加到所选存储单元和选择栅极之间的所述串的一个或多个存储单元的集合。所述方法还包括将通过电压施加到所选择的存储器单元和选择栅极之间的串的一个或多个其它存储单元。其他方法还包括将其他通过电压，其它截止电压和/或中间电压应用于串的其他存储单元。

4. 发明申请

US20100085807A1 SINGLE LATCH DATA CIRCUIT IN A MULTIPLE LEVEL CELL NON-VOLATILE MEMORY DEVICE 有权
标题翻译：多级单元存储器中的单锁数据电路
公开(公告)号：US20100085807A1
公开(公告)日：2010-04-08
申请号：US12632121
申请日：2009-12-07
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati
IPC分类号： G11C16/04 , G11C7/10 , G11C16/06
CPC分类号： G11C7/1051 , G11C7/106 , G11C11/5642 , G11C16/0483 , G11C16/28 , G11C2211/5642 , G11C2211/5647
摘要： A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.
摘要翻译：单个锁存电路耦合到多电平单元存储器件中的每个位线，以处理读取多个数据位。该电路由具有反向节点和非反相节点的锁存器组成。第一控制晶体管选择性地将非反相节点耦合到锁存器输出。第二控制晶体管选择性地将反相节点耦合到锁存器输出。复位晶体管耦合在反相节点和电路接地之间，以在晶体管导通时有选择地接地电路。

5. 发明申请

US20100054068A1 TEMPERATURE COMPENSATION OF MEMORY SIGNALS USING DIGITAL SIGNALS 有权
标题翻译：使用数字信号的存储信号的温度补偿
公开(公告)号：US20100054068A1
公开(公告)日：2010-03-04
申请号：US12613114
申请日：2009-11-05
申请人： Michele Incarnati , Giovanni Santin
发明人： Michele Incarnati , Giovanni Santin
IPC分类号： G11C7/04
CPC分类号： G11C7/04 , G11C5/143
摘要： A temperature sensor generates a digital representation of the temperature of the integrated circuit. A logic circuit reads the digital temperature and generates a multiple bit digital representation of an operational voltage and a multiple bit digital representation of a timing signal, both being functions of the integrated circuit temperature. A voltage generator converts the digital representation of the operational voltage to an analog voltage that biases portions of the integrated circuit requiring temperature compensated voltages. In one embodiment, the temperature compensated voltages bias memory cells. A timing generator converts the multiple bit digital representation of the timing signal to a logic signal.
摘要翻译：温度传感器产生集成电路的温度的数字表示。逻辑电路读取数字温度并产生作为集成电路温度的函数的定时信号的工作电压和多位数字表示的多位数字表示。电压发生器将操作电压的数字表示转换为模拟电压，该模拟电压偏置需要温度补偿电压的集成电路的部分。在一个实施例中，温度补偿电压偏置存储器单元。定时发生器将定时信号的多位数字表示转换为逻辑信号。

6. 发明授权

US07639534B2 Device, system, and method of bit line selection of a flash memory 有权
标题翻译： Flash存储器的位线选择的设备，系统和方法
公开(公告)号：US07639534B2
公开(公告)日：2009-12-29
申请号：US11860949
申请日：2007-09-25
申请人： Michele Incarnati , Giovanni Santin , Violante Moschiano , Tommaso Vali
发明人： Michele Incarnati , Giovanni Santin , Violante Moschiano , Tommaso Vali
IPC分类号： G11C16/04 , G11C5/06
CPC分类号： G11C16/0483 , G11C16/24 , G11C16/26
摘要： Device, system, and method of bit line selection of a flash memory. In some demonstrative embodiments, the method may include connecting to ground at least one location along at least one bit line of a flash memory when the bit line is at an unselected state, wherein the bit line is connected to a multiplexer, and wherein at least one memory sector is coupled to the bit line between the multiplexer and the location; and connecting the location to a precharge path when the bit line is at a selected state.
摘要翻译： Flash存储器的位线选择的设备，系统和方法。在一些说明性实施例中，当位线处于未选择状态时，该方法可以包括沿闪速存储器的至少一个位线的至少一个位置连接到地，其中位线连接到多路复用器，并且其中至少一个存储器扇区耦合到多路复用器和位置之间的位线; 以及当所述位线处于选定状态时将所述位置连接到预充电路径。

7. 发明申请

US20090219761A1 CHARGE LOSS COMPENSATION DURING PROGRAMMING OF A MEMORY DEVICE 有权
标题翻译：存储设备编程期间的费用损失补偿
公开(公告)号：US20090219761A1
公开(公告)日：2009-09-03
申请号：US12177972
申请日：2008-07-23
申请人： Violante Moschiano , Michele Incarnati , Giovanni Santin , Danilo Orlandi
发明人： Violante Moschiano , Michele Incarnati , Giovanni Santin , Danilo Orlandi
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454
摘要： A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation.
摘要翻译：所选字线上的所选择的存储单元通过增加阶跃电压的多个编程脉冲进行编程。在成功的程序验证操作之后，所选存储单元的编程被禁止，同时所选字线的其它存储单元被编程。对所选存储单元执行另一个程序验证操作。如果程序验证操作失败，则耦合到所选单元的位线被偏置在阶跃电压上，并且向所选择的字线发出最终的编程脉冲。然后，所选择的存储单元被锁定以进一步编程，而不评估最终程序验证操作。

8. 发明授权

US07466602B2 Method and apparatus for filtering output data 有权
标题翻译：用于过滤输出数据的方法和装置
公开(公告)号：US07466602B2
公开(公告)日：2008-12-16
申请号：US11758373
申请日：2007-06-05
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/02 , G11C7/106 , G11C7/1066 , G11C7/1069 , G11C7/22 , G11C2207/2281
摘要： Apparatus and methods for filtering spurious output transitions with an adaptive filtering circuit which tracks the memory architecture and form factors with a reduced speed penalty. The filtering is selectable by a fuse option.
摘要翻译：用自适应滤波电路滤波杂散输出转换的装置和方法，该自适应滤波电路以降低的速度损失跟踪存储器架构和形状因子。滤波可由保险丝选项选择。

9. 发明申请

US20080266953A1 SINGLE LATCH DATA CIRCUIT IN A MULTIPLE LEVEL CELL NON-VOLATILE MEMORY DEVICE 有权
标题翻译：多级单元存储器中的单锁数据电路
公开(公告)号：US20080266953A1
公开(公告)日：2008-10-30
申请号：US12170563
申请日：2008-07-10
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati
IPC分类号： G11C7/10 , G11C16/04
CPC分类号： G11C7/1051 , G11C7/106 , G11C11/5642 , G11C16/0483 , G11C16/28 , G11C2211/5642 , G11C2211/5647
摘要： A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.
摘要翻译：单个锁存电路耦合到多电平单元存储器件中的每个位线，以处理读取多个数据位。该电路由具有反向节点和非反相节点的锁存器组成。第一控制晶体管选择性地将非反相节点耦合到锁存器输出。第二控制晶体管选择性地将反相节点耦合到锁存器输出。复位晶体管耦合在反相节点和电路接地之间，以在晶体管导通时有选择地接地电路。

10. 发明申请

US20070189071A1 Single latch data circuit in a multiple level cell non-volatile memory device 有权
标题翻译：单级锁存数据电路在多级单元非易失性存储器件中
公开(公告)号：US20070189071A1
公开(公告)日：2007-08-16
申请号：US11506428
申请日：2006-08-18
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati
IPC分类号： G11C14/00 , G11C16/04 , G11C7/10 , G11C11/34
CPC分类号： G11C7/1051 , G11C7/106 , G11C11/5642 , G11C16/0483 , G11C16/28 , G11C2211/5642 , G11C2211/5647
摘要： A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.
摘要翻译：单个锁存电路耦合到多电平单元存储器件中的每个位线，以处理读取多个数据位。该电路由具有反向节点和非反相节点的锁存器组成。第一控制晶体管选择性地将非反相节点耦合到锁存器输出。第二控制晶体管选择性地将反相节点耦合到锁存器输出。复位晶体管耦合在反相节点和电路接地之间，以在晶体管导通时有选择地接地电路。

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