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1. 发明申请

US20190042156A1 POWER-DOWN/POWER-LOSS MEMORY CONTROLLER 审中-公开
公开(公告)号：US20190042156A1
公开(公告)日：2019-02-07
申请号：US15986804
申请日：2018-05-22
申请人： Luca De Santis , Tommaso Vali , Luca Nubile , Ricardo Cardinali , Maria L. Gallese , Cristina Lattaro
发明人： Luca De Santis , Tommaso Vali , Luca Nubile , Ricardo Cardinali , Maria L. Gallese , Cristina Lattaro
IPC分类号： G06F3/06
摘要： Embodiments of the present disclosure may relate to a memory controller that may include a main controller to begin a power down of a non-volatile memory storage during a first time period, while operating in a first voltage range, wherein the main controller is to begin the power down of the non-volatile memory in response to an indication of a voltage level being below a predetermined threshold; and a sequencer to continue the power down of the memory storage during a second time period, while operating within a second voltage range lower than the first voltage range. In some embodiments, the sequencer may include a state machine to perform a discharge sequence, where the state machine includes a micro-action output to output a micro-action command to the memory storage based at least in part on a current state of the state machine. Other embodiments may be described and/or claimed.

2. 发明授权

US09436402B1 Methods and apparatus for pattern matching 有权
标题翻译：模式匹配的方法和装置
公开(公告)号：US09436402B1
公开(公告)日：2016-09-06
申请号：US13449082
申请日：2012-04-17
申请人： Luca De Santis , Giulio G. Marotta , Marco-Domenico Tiburzi , Tommaso Vali , Frankie F. Roohparvar , Agostino Macerola
发明人： Luca De Santis , Giulio G. Marotta , Marco-Domenico Tiburzi , Tommaso Vali , Frankie F. Roohparvar , Agostino Macerola
IPC分类号： G06F11/263 , G06F3/06 , G11C16/06
CPC分类号： G06F17/30495 , G06F3/0628 , G06F7/20 , G06F12/0802 , G06F2212/1021 , G06F2212/608 , G11C7/1006 , G11C15/046 , G11C16/0483 , G11C16/06 , G11C29/50004 , G11C29/50016
摘要： Methods and apparatus for pattern matching are disclosed. In at least one embodiment, pattern checking is accomplished by reading a page of memory, and comparing the read page with the pattern to be searched in a logic operation. In at least one other embodiment, a pattern to be searched is stored in registers where each bit of the pattern is stored using two register entries and each bit of the array data is stored using two cells of the array.
摘要翻译：公开了用于模式匹配的方法和装置。在至少一个实施例中，通过读取存储器页面，并将读取的页面与在逻辑操作中要搜索的模式进行比较来实现模式检查。在至少另一个实施例中，要搜索的图案被存储在使用两个寄存器条目存储图案的每个位的寄存器中，并且使用阵列的两个单元存储阵列数据的每一位。

3. 发明授权

US09030870B2 Threshold voltage compensation in a multilevel memory 有权
标题翻译：多电平存储器中的阈值电压补偿
公开(公告)号：US09030870B2
公开(公告)日：2015-05-12
申请号：US13219439
申请日：2011-08-26
申请人： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
发明人： Violante Moschiano , Tommaso Vali , Giovanni Naso , Vishal Sarin , William Henry Radke , Theodore T. Pekny
IPC分类号： G11C11/34 , G11C16/04 , G11C16/26 , G11C11/56 , G11C16/34
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C2211/5641
摘要： Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.
摘要翻译：电荷存储存储器中的阈值电压由阈值电压放置来控制，例如提供更可靠的操作并减少诸如相邻电荷存储元件和寄生耦合的因素的影响。相邻编程的“侵略者”存储器单元的阈值电压的预补偿或后补偿降低了闪存系统中的阈值电压不确定性。使用具有诸如查找表之类的数据结构的缓冲器提供了可编程的阈值电压分布，使得能够定制多级单元闪存中的数据状态的分布，例如提供更可靠的操作。

4. 发明授权

US08553461B2 Method for kink compensation in a memory 有权
公开(公告)号：US08553461B2
公开(公告)日：2013-10-08
申请号：US13585389
申请日：2012-08-14
申请人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
发明人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
摘要： This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.

5. 发明授权

US08243521B2 Method for kink compensation in a memory 有权
标题翻译：存储器中的扭结补偿方法
公开(公告)号：US08243521B2
公开(公告)日：2012-08-14
申请号：US12631606
申请日：2009-12-04
申请人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
发明人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
摘要： This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
摘要翻译：本公开涉及存储器扭结补偿。一个方法实施例包括将多个顺序递增的编程脉冲施加到存储器单元，其中顺序编程脉冲通过第一编程脉冲阶跃电压幅度递增。在施加顺序递增的编程脉冲数之后施加接种电压。在施加播种电压之后施加下一个编程脉冲，其中下一个编程脉冲相对于先前的一个顺序递增的编程脉冲通过第二编程脉冲阶跃电压幅度被调整。第二个编程脉冲阶跃电压幅度可以小于第一个编程脉冲阶跃电压幅度。

6. 发明申请

US20110134701A1 MEMORY KINK COMPENSATION 有权
标题翻译：内存清理补偿
公开(公告)号：US20110134701A1
公开(公告)日：2011-06-09
申请号：US12631606
申请日：2009-12-04
申请人： Violante Moschiano , Frankie F. Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
发明人： Violante Moschiano , Frankie F. Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC分类号： G11C16/12
CPC分类号： G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
摘要： This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
摘要翻译：本公开涉及存储器扭结补偿。一个方法实施例包括将多个顺序递增的编程脉冲施加到存储器单元，其中顺序编程脉冲通过第一编程脉冲阶跃电压幅度递增。在施加顺序递增的编程脉冲数之后施加接种电压。在施加播种电压之后施加下一个编程脉冲，其中下一个编程脉冲相对于先前的一个顺序递增的编程脉冲通过第二编程脉冲步长电压幅度被调整。第二个编程脉冲阶跃电压幅度可以小于第一个编程脉冲阶跃电压幅度。

7. 发明申请

US20100165739A1 NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING 有权
标题翻译：非易失性多重存储器单元编程
公开(公告)号：US20100165739A1
公开(公告)日：2010-07-01
申请号：US12718290
申请日：2010-03-05
申请人： Violante Moschiano , Giovanni Santin , Tommaso Vali , Massimo Rossini
发明人： Violante Moschiano , Giovanni Santin , Tommaso Vali , Massimo Rossini
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3404 , G11C16/3486 , G11C2211/5621 , G11C2211/5625
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method includes increasing a threshold voltage (Vt) for each of a number of memory cells until the Vt reaches a verify voltage (VFY) corresponding to a program state among a number of program states. The method includes determining whether the Vt of each of the cells has reached a pre-verify voltage (PVFY) associated with the program state, selectively biasing bit lines coupled to those cells whose Vt has reached the PVFY, adjusting the PVFY to a different level, and selectively biasing bit lines coupled to cells whose Vt has reached the adjusted PVFY, wherein the PVFY and the adjusted PVFY are less than the VFY.
摘要翻译：本公开的实施例提供用于编程多电平非易失性多电平存储器单元的方法，设备，模块和系统。一种方法包括增加用于多个存储器单元中的每一个的阈值电压（Vt），直到Vt达到与多个程序状态中的程序状态相对应的验证电压（VFY）。该方法包括确定每个单元的Vt是否已经达到与编程状态相关联的预验证电压（PVFY），选择性地偏置与Vt已经达到PVFY的那些单元耦合的位线，将PVFY调整到不同的水平并且选择性地偏置与Vt已经达到调整后的PVFY的单元相连的位线，其中PVFY和调整后的PVFY小于VFY。

8. 发明授权

US07630241B2 Single latch data circuit in a multiple level call non-volatile memory device 有权
标题翻译：单级锁存数据电路在多级单元非易失性存储器件中
公开(公告)号：US07630241B2
公开(公告)日：2009-12-08
申请号：US12170563
申请日：2008-07-10
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati
IPC分类号： G11C11/34
CPC分类号： G11C7/1051 , G11C7/106 , G11C11/5642 , G11C16/0483 , G11C16/28 , G11C2211/5642 , G11C2211/5647
摘要： A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.
摘要翻译：单个锁存电路耦合到多电平单元存储器件中的每个位线，以处理读取多个数据位。该电路由具有反向节点和非反相节点的锁存器组成。第一控制晶体管选择性地将非反相节点耦合到锁存器输出。第二控制晶体管选择性地将反相节点耦合到锁存器输出。复位晶体管耦合在反相节点和电路接地之间，以在晶体管导通时有选择地接地电路。

9. 发明申请

US20090273981A1 Methods and apparatuses for programming flash memory using modulated pulses 有权
标题翻译：使用调制脉冲编程闪存的方法和装置
公开(公告)号：US20090273981A1
公开(公告)日：2009-11-05
申请号：US12151265
申请日：2008-05-05
申请人： Violante Moschiano , Tommaso Vali , Giovanni Santin , Walter Di Francesco
发明人： Violante Moschiano , Tommaso Vali , Giovanni Santin , Walter Di Francesco
IPC分类号： G11C16/12
CPC分类号： G11C16/10 , G11C16/12
摘要： Methods and apparatuses for programming non-volatile semiconductor memory devices by using modulated pulses are disclosed. Embodiments generally comprise a pulse generator, to create a sequence of pulses and set a threshold voltage of a non-volatile memory cell, and a pulse coupler. Alternative embodiments may include a threshold verifier capable of verifying that the threshold voltage is set within an acceptable voltage range of a target threshold voltage. A pulse width modulator in some apparatus embodiments may modulate the pulse durations early in the sequence when programming fast bits and late in the sequence when programming slow bits. Method embodiments generally comprise generating a sequence of pulses, applying the sequence of pulses to a memory cell to set a threshold voltage of the memory cell, and modulating among pulses in the sequence the parameters of pulse duration, pulse separation time, and step voltage magnitude.
摘要翻译：公开了通过使用调制脉冲来编程非易失性半导体存储器件的方法和装置。实施例通常包括脉冲发生器，以产生脉冲序列并设置非易失性存储单元的阈值电压和脉冲耦合器。替代实施例可以包括能够验证阈值电压被设置在目标阈值电压的可接受电压范围内的阈值校验器。某些设备实施例中的脉冲宽度调制器可以在编程快速位时在序列的早期调制脉冲持续时间，而在编程慢位时可以在序列的后期调制脉冲持续时间。方法实施例通常包括产生脉冲序列，将脉冲序列应用于存储器单元以设置存储器单元的阈值电压，以及在该序列中的脉冲之间调制脉冲持续时间，脉冲间隔时间和步进电压幅度的参数。

10. 发明申请

US20090080253A1 DEVICE, SYSTEM, AND METHOD OF BIT LINE SELECTION OF A FLASH MEMORY 有权
标题翻译：闪存存储器的位线选择的设备，系统和方法
公开(公告)号：US20090080253A1
公开(公告)日：2009-03-26
申请号：US11860949
申请日：2007-09-25
申请人： MICHELE INCARNATI , Giovanni Santin , Violante Moschiano , Tommaso Vali
发明人： MICHELE INCARNATI , Giovanni Santin , Violante Moschiano , Tommaso Vali
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/24 , G11C16/26
摘要： Device, system, and method of bit line selection of a flash memory. In some demonstrative embodiments, the method may include connecting to ground at least one location along at least one bit line of a flash memory when the bit line is at an unselected state, wherein the bit line is connected to a multiplexer, and wherein at least one memory sector is coupled to the bit line between the multiplexer and the location; and connecting the location to a precharge path when the bit line is at a selected state. Other embodiments are described and claimed.
摘要翻译： Flash存储器的位线选择的设备，系统和方法。在一些说明性实施例中，当位线处于未选择状态时，该方法可以包括沿闪速存储器的至少一个位线的至少一个位置连接到地，其中位线连接到多路复用器，并且其中至少一个存储器扇区耦合到多路复用器和位置之间的位线; 以及当所述位线处于选定状态时将所述位置连接到预充电路径。描述和要求保护其他实施例。

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