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1. 发明授权

US10064276B2 3D bendable printed circuit board with redundant interconnections 有权
公开(公告)号：US10064276B2
公开(公告)日：2018-08-28
申请号：US14919594
申请日：2015-10-21
申请人： Applied BioPhotonics, Ltd.
发明人： Richard K Williams , Keng Hung Lin
IPC分类号： H05K1/00 , H05K1/14 , H05K3/00 , H05K3/02 , H05K3/06 , H05K3/18 , H05K3/32 , H05K3/36 , H05K3/40 , H05K3/46 , H05K3/24
CPC分类号： H05K1/148 , H05K1/147 , H05K3/0026 , H05K3/0035 , H05K3/027 , H05K3/06 , H05K3/061 , H05K3/188 , H05K3/24 , H05K3/32 , H05K3/361 , H05K3/4038 , H05K3/4691 , H05K2201/052 , H05K2201/056 , H05K2201/058 , H05K2201/09245 , H05K2201/09254 , H05K2201/0979 , H05K2201/10106 , H05K2201/2009 , H05K2203/1327
摘要： A rigid-flex PCB includes an array of rigid PCB “islands” interconnected by a flexible PCB formed into flexible connectors. The conductive and insulating layers of the flexible PCB extend into the rigid PCBs, giving the electrical connections to the rigid PCBs added resistance to breakage as the rigid-flex PCB is repeatedly stressed by bending and twisting forces. In addition, the durability of the rigid-flex PCB is enhanced by making the power and signal lines driving the rigid PCBs redundant so that a breakage of a line will not necessarily affect the operation of the rigid PCB to which it is attached. The rigid-flex PCB is particularly applicable to light pads used in phototherapy, wherein LEDs mounted on the rigid-PCBs are powered and controlled through the redundant lines in the flexible PCB.

2. 发明授权

US10032649B2 Method of fabricating low-profile footed power package 有权
公开(公告)号：US10032649B2
公开(公告)日：2018-07-24
申请号：US15453136
申请日：2017-03-08
申请人： Adventive Technology Ltd.
发明人： Richard K. Williams , Keng Hung Lin
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L23/495 , H01L21/56 , H01L23/00 , H01L23/29 , H01L23/367 , H01L23/31
摘要： A method is disclosed of fabricating a power package which includes a heat tab extending from a die pad exposed on the underside of the package, which facilitates the removal of heat from the die to the PCB or other surface on which the package is mounted. The heat tab has a bottom surface coplanar with the flat bottom surface of the die pad and bottom surface of a lead. The lead includes a horizontal foot segment, a vertical columnar segment, and a horizontal cantilever segment facing the die pad. The heat tab may also have a foot. A die containing a power device is mounted on a top surface of the die pad and may be electrically connected to the lead using a bonding wire or clip. The die may be mounted on the die pad with as electrically conductive material, and the package may also include a lead that extends from the die pad and is thus electrically tied to the bottom of the die. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories.

3. 发明授权

US08277919B2 Reflective coating for an optical disc 失效
标题翻译：光盘反光涂层
公开(公告)号：US08277919B2
公开(公告)日：2012-10-02
申请号：US12507868
申请日：2009-07-23
申请人： Neil Deeman , Jerry E. Hurst, Jr.
发明人： Neil Deeman , Jerry E. Hurst, Jr.
IPC分类号： B32B3/02
CPC分类号： C23C14/205 , G11B7/2585 , G11B7/266 , Y10T428/12736 , Y10T428/12743 , Y10T428/21
摘要： An optical disc includes a substrate layer, a cover layer, and an aluminum alloy layer that is between the substrate layer and cover layer, and is adjacent to the substrate layer. The aluminum alloy layer includes a majority amount of aluminum and an additional metal selected from the group consisting of: chromium, titanium, tantalum, and any combination thereof. A method of making an optical disc includes the steps of: forming a substrate layer; sputtering an aluminum alloy target onto the substrate layer to form an aluminum alloy layer; and forming a cover layer; wherein the aluminum alloy layer comprises a majority amount of aluminum and an additional metal selected from the group consisting of: chromium, titanium, tantalum, and any combination thereof.
摘要翻译：光盘包括衬底层，覆盖层和位于衬底层和覆盖层之间并且与衬底层相邻的铝合金层。铝合金层包括大量的铝和选自铬，钛，钽及其任何组合的另外的金属。制造光盘的方法包括以下步骤：形成衬底层; 将铝合金靶溅射到基底层上以形成铝合金层; 并形成覆盖层; 其中所述铝合金层包含多数量的铝和选自以下的另外的金属：铬，钛，钽及其任何组合。

4. 发明授权

US08148758B2 High voltage semiconductor device with JFET regions containing dielectrically isolated junctions and method of fabricating the same 有权
标题翻译：具有包含介电隔离结的JFET区域的高电压半导体器件及其制造方法
公开(公告)号：US08148758B2
公开(公告)日：2012-04-03
申请号：US12928682
申请日：2010-12-16
申请人： Hamza Yilmaz
发明人： Hamza Yilmaz
IPC分类号： H01L29/72
CPC分类号： H01L29/7393 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/42368 , H01L29/66681 , H01L29/7816 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： A high-voltage field-effect device contains an extended drain or “drift” region including an embedded stack of JFET regions separated by intervening layers of the drift region. Each of the JFET regions is filled with material of an opposite conductivity type to that of the drift region, and the floor and ceiling of each JFET region is lined with an oxide layer. When the device is blocking a voltage in the off condition, the semiconductor material inside the JFET regions and in the drift region that separates the JFET regions is depleted. This improves the voltage-blocking ability of the device while conserving chip area. The oxide layer prevents dopant from the JFET regions from diffusing into the drift region.
摘要翻译：高电压场效应器件包含延伸的漏极或“漂移”区域，包括由漂移区的中间层隔开的JFET区域的嵌入堆叠。每个JFET区域都填充有与漂移区域相反的导电类型的材料，并且每个JFET区域的地板和天花板都衬有氧化物层。当器件在断开状态下阻塞电压时，JFET区域内部和分离JFET区域的漂移区域内的半导体材料耗尽。这提高了器件的压阻能力，同时节省了芯片面积。氧化物层防止来自JFET区域的掺杂剂扩散到漂移区域。

5. 发明授权

US08030731B2 Isolated rectifier diode 有权
标题翻译：隔离整流二极管
公开(公告)号：US08030731B2
公开(公告)日：2011-10-04
申请号：US12002344
申请日：2007-12-17
申请人： Richard K. Williams , Donald Ray Disney , Wai Tien Chan
发明人： Richard K. Williams , Donald Ray Disney , Wai Tien Chan
IPC分类号： H01L21/76
CPC分类号： H01L29/735 , H01L21/761 , H01L21/82285 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/8249 , H01L27/0623 , H01L27/0826 , H01L27/092 , H01L29/7322 , H01L2924/0002 , H01L2924/00
摘要： An isolated diode comprises a floor isolation region, a dielectric-filled trench and a sidewall region extending from a bottom of the trench at least to the floor isolation region. The floor isolation region, dielectric-filled trench and a sidewall region are comprised in one terminal (anode or cathode) of the diode and together form an isolated pocket in which the other terminal of the diode is formed. In one embodiment the terminals of the diode are separated by a second dielectric-filled trench and sidewall region.
摘要翻译：隔离二极管包括底部隔离区域，电介质填充的沟槽和从沟槽的底部至少延伸到地板隔离区域的侧壁区域。底部隔离区域，电介质填充沟槽和侧壁区域包含在二极管的一个端子（阳极或阴极）中，并且一起形成隔离的袋，二极管的另一个端子形成在该隔离腔中。在一个实施例中，二极管的端子被第二电介质填充的沟槽和侧壁区域分开。

6. 发明授权

US07960997B2 Cascode current sensor for discrete power semiconductor devices 有权
标题翻译：用于分立功率半导体器件的串联电流传感器
公开(公告)号：US07960997B2
公开(公告)日：2011-06-14
申请号：US11890948
申请日：2007-08-08
申请人： Richard K. Williams
发明人： Richard K. Williams
IPC分类号： G01R31/26
CPC分类号： G01R19/0092 , G01R1/203 , H01L23/49575 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/17 , H01L24/25 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L27/088 , H01L29/1087 , H01L29/41758 , H01L29/4238 , H01L29/7833 , H01L2224/0401 , H01L2224/04042 , H01L2224/05093 , H01L2224/05558 , H01L2224/05599 , H01L2224/0603 , H01L2224/13099 , H01L2224/16145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/48464 , H01L2224/48599 , H01L2224/49111 , H01L2224/49171 , H01L2224/73207 , H01L2224/73257 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/014 , H01L2924/10253 , H01L2924/12032 , H01L2924/12035 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13062 , H01L2924/13063 , H01L2924/13091 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H02M2001/0009 , H03K17/0822 , H03K17/18 , H03K2217/0027 , H01L2924/00 , H01L2924/00012
摘要： A cascode current sensor includes a main MOSFET and a sense MOSFET. The drain terminal of the main MOSFET is connected to a power device whose current is to be monitored, and the source and gate terminals of the main MOSFET are connected to the source and gate terminals, respectively, of the sense MOSFET. The drain voltages of the main and sense MOSFETs are equalized, in one embodiment by using a variable current source and negative feedback. The gate width of the main MOSFET is typically larger than the gate width of the sense MOSFET. Using the size ratio of the gate widths, the current in the main MOSFET is measured by sensing the magnitude of the current in the sense MOSFET. Inserting the relatively large MOSFET in the power circuit minimizes power loss.
摘要翻译：共源共栅电流传感器包括主MOSFET和感测MOSFET。主MOSFET的漏极端子连接到要监视其电流的功率器件，并且主MOSFET的源极和栅极端子分别连接到感测MOSFET的源极和栅极端子。在一个实施例中，通过使用可变电流源和负反馈来使主感测MOSFET和感测MOSFET的漏极电压相等。主MOSFET的栅极宽度通常大于读出MOSFET的栅极宽度。使用栅极宽度的尺寸比，通过感测MOSFET中电流的大小来测量主MOSFET中的电流。在电源电路中插入相对较大的MOSFET可以最大限度地减少功耗。

7. 发明授权

US07902630B2 Isolated bipolar transistor 有权
标题翻译：隔离双极晶体管
公开(公告)号：US07902630B2
公开(公告)日：2011-03-08
申请号：US12069940
申请日：2008-02-14
申请人： Donald R. Disney , Richard K. Williams
发明人： Donald R. Disney , Richard K. Williams
IPC分类号： H01L29/73
CPC分类号： H01L21/76243 , H01L21/761 , H01L21/76267 , H01L21/763 , H01L21/8222 , H01L21/82285 , H01L21/823878 , H01L21/823892 , H01L27/0825 , H01L27/0826 , H01L29/1004 , H01L29/41708 , H01L29/732
摘要： An isolated bipolar transistor formed in a P-type semiconductor substrate includes an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains the bipolar transistor. The collector of the bipolar transistor may comprise the floor isolation region. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.
摘要翻译：形成在P型半导体衬底中的隔离双极型晶体管包括N型浸没式隔离区和从衬底表面向底部隔离区向下延伸的填充沟槽。底部隔离区域和填充的沟槽一起形成包含双极晶体管的衬底的隔离袋。双极晶体管的集电极可以包括地板隔离区域。衬底不含有外延层，从而克服了与其制造相关的许多问题。

8. 发明授权

US07812647B2 MOSFET gate drive with reduced power loss 有权
标题翻译： MOSFET栅极驱动，功耗降低
公开(公告)号：US07812647B2
公开(公告)日：2010-10-12
申请号：US11890942
申请日：2007-08-08
申请人： Richard K. Williams
发明人： Richard K. Williams
IPC分类号： H03B1/00
CPC分类号： H03K17/6872 , H03K17/08142 , H03K17/145 , H03K17/18 , H03K2217/0036 , H03K2217/94031
摘要： A gate driver for a power MOSFET in, for example, a DC-DC converter switches the MOSFET between a fully-on condition and a low-current condition instead of switching the MOSFET between fully-on and fully-off conditions. The amount of charge that must be transferred to charge and discharge the gate of the MOSFET is thereby reduced, and the efficiency of the MOSFET is improved. A feedback circuit may be used to assure that the magnitude of current in the power MOSFET in its low-current condition is correct. Alternatively, a trimming process may be used to correct the magnitude of the voltage supplied by the gate driver to the gate of the power MOSFET in the low-current condition.
摘要翻译：用于例如DC-DC转换器的功率MOSFET的栅极驱动器在完全导通条件和低电流条件之间切换MOSFET，而不是在完全导通和完全关断条件之间切换MOSFET。因此，必须转移到对MOSFET的栅极进行充电和放电的电荷量减小，并且提高了MOSFET的效率。可以使用反馈电路来确保功率MOSFET在其低电流条件下的电流幅度是正确的。或者，修整过程可以用于在低电流条件下校正由栅极驱动器提供给功率MOSFET的栅极的电压的大小。

9. 发明授权

US07812403B2 Isolation structures for integrated circuit devices 有权
标题翻译：集成电路器件的隔离结构
公开(公告)号：US07812403B2
公开(公告)日：2010-10-12
申请号：US12070035
申请日：2008-02-14
申请人： Donald R. Disney , Richard K. Williams
发明人： Donald R. Disney , Richard K. Williams
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L21/76
CPC分类号： H01L21/76243 , H01L21/76267 , H01L21/763 , H01L21/8222 , H01L21/82285 , H01L21/823878 , H01L21/823892 , H01L27/0825 , H01L27/0826 , H01L29/1004 , H01L29/41708 , H01L29/732
摘要： An isolated CMOS pair of transistors formed in a P-type semiconductor substrate includes an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains a P-channel MOSFET in an N-well and an N-channel MOSFET in a P-well. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.
摘要翻译：形成在P型半导体衬底中的隔离的CMOS对晶体管包括N型浸没层隔离区和从衬底表面向底部隔离区向下延伸的填充沟槽。底部隔离区域和填充沟槽一起形成衬底的隔离袋，其在N阱中包含P沟道MOSFET，在P阱中包含N沟道MOSFET。衬底不含有外延层，从而克服了与其制造相关的许多问题。

10. 发明授权

US07800198B2 Isolation structures for integrated circuits 有权
标题翻译：集成电路的隔离结构
公开(公告)号：US07800198B2
公开(公告)日：2010-09-21
申请号：US12220950
申请日：2008-07-30
申请人： Richard K. Williams , Donald Ray Disney , Wai Tien Chan
发明人： Richard K. Williams , Donald Ray Disney , Wai Tien Chan
IPC分类号： H01L21/76
CPC分类号： H01L29/0646 , H01L21/26513 , H01L21/761 , H01L21/76224 , H01L21/76237 , H01L21/76243 , H01L21/76267 , H01L21/763 , H01L21/823481 , H01L21/823878 , H01L21/823892 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be used in combination with doped sidewall isolation regions. Both the trench and the sidewall isolation regions may be annular and enclose an isolated pocket of the substrate. The isolation structures are formed by modular implant and etch processes that do not include significant thermal processing or diffusion of dopants so that the resulting structures are compact and may be tightly packed in the surface of the substrate.
摘要翻译：用于半导体衬底的各种隔离结构包括形成在衬底中的沟槽，其填充有电介质材料或填充有导电材料并且沿着沟槽的壁衬有介电层。沟槽可以与掺杂的侧壁隔离区域组合使用。沟槽和侧壁隔离区域都可以是环形的并且包围衬底的隔离袋。隔离结构通过不包括显着的热处理或掺杂剂扩散的模块化注入和蚀刻工艺形成，使得所得到的结构是紧凑的并且可以紧密地堆积在衬底的表面中。

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