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1. 发明授权

US09040419B2 Semiconductor package and method for manufacturing the same 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US09040419B2
公开(公告)日：2015-05-26
申请号：US14334406
申请日：2014-07-17
申请人： SK Hynix Inc.
发明人： Ho Young Son
IPC分类号： H01L21/44 , H01L21/768 , H01L23/00
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/11 , H01L2224/0401 , H01L2224/0557 , H01L2224/13 , H01L2224/14181 , H01L2924/00014 , H01L2924/12042 , H01L2224/05552 , H01L2924/00
摘要： A semiconductor package includes a semiconductor chip having a front surface and a back surface facing away from the front surface; a through electrode formed in the semiconductor chip and passing through the front surface and the back surface; and a contamination preventing layer formed in the semiconductor chip, the through electrode passing through the contamination preventing layer.
摘要翻译：半导体封装包括半导体芯片，其具有前表面和背表面背离前表面; 形成在半导体芯片中并穿过前表面和后表面的通孔; 以及形成在半导体芯片中的防污染层，穿通电极穿过防污染层。

2. 发明授权

US09018759B2 Semiconductor package substrate and semiconductor package including the same 有权
标题翻译：半导体封装基板和包括其的半导体封装
公开(公告)号：US09018759B2
公开(公告)日：2015-04-28
申请号：US13656339
申请日：2012-10-19
申请人： SK Hynix Inc.
发明人： Jong Hoon Kim
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/13 , H01L23/00 , H01L23/367 , H01L23/498
CPC分类号： H01L23/13 , H01L23/3677 , H01L23/49816 , H01L23/49827 , H01L24/17 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/00
摘要： A semiconductor package substrate including a substrate body having a front surface configured for mounting a semiconductor chip on the front surface and a rear surface facing the front surface and comprising a window passing through the front and rear surfaces, the window having one or more surfaces inclined from the front surface toward the rear surface; and a conductive pattern arranged along an inclined surface of the window so as to extend from the front surface to the rear surface of the substrate body.
摘要翻译：一种半导体封装基板，包括：基板主体，其具有被构造用于将半导体芯片安装在前表面上的前表面和面向前表面的后表面，并且包括通过前表面和后表面的窗口，所述窗口具有一个或多个倾斜的表面从前表面到后表面; 以及沿着窗的倾斜表面布置以从基板主体的前表面延伸到后表面的导电图案。

3. 发明授权

US09013951B2 Word line drivers and semiconductor memory devices including the same 有权
标题翻译：字线驱动器和包括相同的半导体存储器件
公开(公告)号：US09013951B2
公开(公告)日：2015-04-21
申请号：US14079820
申请日：2013-11-14
申请人： SK Hynix Inc.
发明人： Sang Il Park
IPC分类号： G11C8/00 , G11C8/08 , G11C8/10
CPC分类号： G11C8/08 , G11C8/10
摘要： Word line drivers including a selection signal generator and a word line drive unit are provided. The selection signal generator generates a selection signal which is enabled according to a high-order address signal and a low-order address signal in an active mode. Further, the selection signal generator generates a complementary selection signal which is enabled when an equalization signal is inputted in a pre-charge mode after the active mode. The word line driver receives the main word line signal to drive a word line to have a first level when the selection signal is enabled, to drive the word line to have a second level when the selection signal is disabled, and to drive the word line to have a third level when the complementary selection signal is enabled.
摘要翻译：提供了包括选择信号发生器和字线驱动单元的字线驱动器。选择信号发生器根据高阶地址信号和活动模式中的低位地址信号生成选择信号。此外，选择信号发生器产生互补选择信号，其在激活模式之后以预充电模式输入均衡信号时使能。当选择信号被使能时，字线驱动器接收主字线信号以驱动字线以具有第一电平，以在禁止选择信号时驱动字线具有第二电平，并驱动字线当互补选择信号被使能时具有第三电平。

4. 发明授权

US09013950B2 Column select signal generation circuit 有权
标题翻译：列选择信号发生电路
公开(公告)号：US09013950B2
公开(公告)日：2015-04-21
申请号：US13586155
申请日：2012-08-15
申请人： Jin Youp Cha , Jae Il Kim
发明人： Jin Youp Cha , Jae Il Kim
IPC分类号： G11C8/00 , G11C8/18 , G11C7/10 , G11C7/12 , G11C8/10
CPC分类号： G11C7/12 , G11C8/10
摘要： A column select signal generation circuit includes: a first current controller configured to control the level of a pre-column select signal in response to a bank active signal, a driver configured to generate an amplified column select signal in response to the pre-column select signal, and a second current controller configured to generate an output signal of the driver as a column select signal in response to the bank active signal.
摘要翻译：列选择信号生成电路包括：第一电流控制器，被配置为响应于存储体活动信号来控制预列选择信号的电平，驱动器被配置为响应于预列选择产生放大列选择信号信号和第二电流控制器，其被配置为响应于存储体有效信号而产生驱动器的输出信号作为列选择信号。

5. 发明授权

US09007863B1 Semiconductor devices 有权
标题翻译：半导体器件
公开(公告)号：US09007863B1
公开(公告)日：2015-04-14
申请号：US14176599
申请日：2014-02-10
申请人： SK Hynix Inc.
发明人： Choung Ki Song , Yo Sep Lee , Chan Gi Gil , Chang Hyun Kim
IPC分类号： G11C7/00 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/40626
摘要： A semiconductor device including a control signal generator and an internal refresh signal generator is provided. The control signal generator generates first and second control signals, one of which is selectively enabled in response to temperature code signals and mode set signals after a pulse of an internal refresh signal is outputted by the internal refresh signal generator. The temperature code signals are obtained from temperature signals. The internal refresh signal generator outputs a refresh command signal as the internal refresh signal when the first control signal is enabled. Further, the internal refresh signal generator outputs the refresh command signal as the internal refresh signal at a moment that the refresh command signal is inputted thereto by a predetermined number of times when the second control signal is enabled.
摘要翻译：提供了包括控制信号发生器和内部刷新信号发生器的半导体器件。控制信号发生器产生第一和第二控制信号，其中一个控制信号在内部刷新信号发生器输出内部刷新信号的脉冲之后响应于温度代码信号和模式设置信号选择性地使能。温度信号由温度信号获得。当第一控制信号被使能时，内部刷新信号发生器输出刷新命令信号作为内部刷新信号。此外，当第二控制信号被使能时，内部刷新信号发生器输出刷新命令信号作为内部刷新信号，在刷新命令信号输入时刻预定次数。

6. 发明授权

US09000563B2 Capacitor and register of semiconductor device, memory system including the semiconductor device, and method of manufacturing the semiconductor device 有权
标题翻译：半导体器件的电容器和寄存器，包括半导体器件的存储器系统以及半导体器件的制造方法
公开(公告)号：US09000563B2
公开(公告)日：2015-04-07
申请号：US14527170
申请日：2014-10-29
申请人： SK Hynix Inc.
发明人： Sun Mi Park , Sang Hyun Oh , Sang Bum Lee
IPC分类号： H01L21/02 , H01L29/40 , H01L21/20 , H01L21/44 , H01L49/02 , H01L27/108
CPC分类号： H01L28/60 , H01L27/0805 , H01L27/10844 , H01L27/11573 , H01L27/11582 , H01L28/91
摘要： A capacitor of a semiconductor device includes a capacitor structure configured to include electrode layers and dielectric layers alternately stacked, edge regions each stepwise patterned, and a central region disposed between the edge regions, sacrificial layers disposed within the respective electrode layers in the edge regions of the capacitor structure, and support plugs formed in the central region of the capacitor structure and configured to penetrate the electrode layers and the dielectric layers.
摘要翻译：半导体器件的电容器包括电容器结构，其被配置为包括交替堆叠的电极层和电介质层，每个逐步图案化的边缘区域和设置在边缘区域之间的中心区域，设置在边缘区域中的各个电极层内的牺牲层电容器结构和形成在电容器结构的中心区域并被配置为穿透电极层和电介质层的支撑塞。

7. 发明授权

US08999787B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08999787B2
公开(公告)日：2015-04-07
申请号：US14471850
申请日：2014-08-28
申请人： SK Hynix Inc.
发明人： Ki Hong Lee , Seung Ho Pyi , Seok Min Jeon
IPC分类号： H01L21/02 , H01L27/115
CPC分类号： H01L27/11578 , H01L21/0223 , H01L27/11582 , H01L29/792
摘要： A semiconductor device includes a plurality of conductive layers and a plurality of insulating layers formed alternately with each other, at least one channel layer passing through the plurality of conductive layers and the plurality of insulating layers, and at least one first charge blocking layer surrounding the at least one channel layer, wherein a plurality of first regions, interposed between the at least one channel layer and the plurality of conductive layers, and a plurality of second regions, interposed between the at least one channel layer and the plurality of insulating layers, are alternately defined on the at least one first charge blocking layer, and each of the plurality of first regions has a greater thickness than each of the plurality of second regions.
摘要翻译：半导体器件包括彼此交替地形成的多个导电层和多个绝缘层，穿过多个导电层和多个绝缘层的至少一个沟道层，以及包围该多个导电层的至少一个第一电荷阻挡层至少一个沟道层，其中介于所述至少一个沟道层和所述多个导电层之间的多个第一区域以及介于所述至少一个沟道层和所述多个绝缘层之间的多个第二区域，交替地限定在至少一个第一电荷阻挡层上，并且多个第一区域中的每一个具有比多个第二区域中的每一个更大的厚度。

8. 发明授权

US08995213B2 Nonvolatile memory device and operating method thereof 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US08995213B2
公开(公告)日：2015-03-31
申请号：US13711869
申请日：2012-12-12
申请人： SK Hynix Inc.
发明人： In Hwan Song
IPC分类号： G11C29/00 , G11C29/50 , G11C16/34
CPC分类号： G11C29/50016 , G11C16/349
摘要： A nonvolatile memory device includes a memory cell array including a main cell area and a retention flag cell area, a retention check unit configured to compare a read result for retention flag cells included in the retention flag cell area to a reference value, and determine a retention state of the retention flag cells according to a comparison result, and a control logic configured to provide a retention check result based on the retention state to the external device in response to a retention check request provided from an external device.
摘要翻译：非易失性存储器件包括：存储单元阵列，包括主单元区域和保持标志单元区域;保留检查单元，被配置为将保持标记单元区域中包括的保持标志单元的读取结果与参考值进行比较，根据比较结果保持标志单元的保持状态，以及控制逻辑，被配置为响应于从外部设备提供的保持检查请求，将基于保持状态的保留检查结果提供给外部设备。

9. 发明授权

US08995209B2 Semiconductor integrated circuit and method for monitoring reference voltage thereof 有权
标题翻译：半导体集成电路及其参考电压监视方法
公开(公告)号：US08995209B2
公开(公告)日：2015-03-31
申请号：US13845909
申请日：2013-03-18
申请人： SK Hynix Inc.
发明人： Se Jin Yoo
IPC分类号： G11C7/00 , G11C7/18 , G11C7/10 , G11C7/14 , G11C29/02 , G11C29/12 , G11C29/48 , G11C29/04
CPC分类号： G11C7/1096 , G11C7/1048 , G11C7/1066 , G11C7/1069 , G11C7/1084 , G11C7/14 , G11C29/021 , G11C29/1201 , G11C29/48 , G11C2029/0409 , G11C2207/105
摘要： A semiconductor integrated circuit includes a write path coupled to a pad, a read path coupled to the pad, and a reference voltage output control block configured to apply a reference voltage to the pad through the write path in response to a reference voltage monitoring signal. The read path is electrically isolated from the pad in response to the reference voltage monitoring signal.
摘要翻译：半导体集成电路包括耦合到焊盘的写入路径，耦合到焊盘的读取路径以及被配置为响应于参考电压监视信号通过写入路径向焊盘施加参考电压的参考电压输出控制块。读取路径响应于参考电压监视信号与焊盘电隔离。

10. 发明授权

US08988111B2 Cascoded comparator with dynamic biasing for column parallel single slope ADCs 有权
标题翻译：具有串并联单斜率ADC的动态偏置的Cascoded比较器
公开(公告)号：US08988111B2
公开(公告)日：2015-03-24
申请号：US13017839
申请日：2011-01-31
申请人： Jeff Rysinski , Yibing Michelle Wang , Sang-Soo Lee
发明人： Jeff Rysinski , Yibing Michelle Wang , Sang-Soo Lee
IPC分类号： H03K19/00 , H03K19/02 , H03F3/45 , H03K5/24 , H03M1/12 , H03M1/56
CPC分类号： H03K5/2472 , H03F3/45188 , H03F2203/45292 , H03F2203/45302 , H03F2203/45674 , H03K5/2481 , H03M1/12 , H03M1/123 , H03M1/36 , H03M1/56
摘要： Aspects of the invention may include receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively.
摘要翻译：本发明的方面可以包括经由相应的第一和第二输入晶体管接收第一输入信号和第二输入信号。由共源共栅偏压发生器产生的偏置信号跟踪第一输入信号，其中偏置信号相对于第一输入信号具有固定的偏移。偏置信号可以分别施加到可以级联到第一和第二输入晶体管的第一和第二共源共栅晶体管。

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