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1. 发明授权

US11303264B1 Active filter for electromagnetic interference (EMI) reduction using a single connection point and a negative impedance converter 有权
公开(公告)号：US11303264B1
公开(公告)日：2022-04-12
申请号：US17091089
申请日：2020-11-06
申请人： Hong Kong Applied Science and Technology Research Institute Company, Limited
发明人： Danting Xu , Ziyang Gao , Kun Wu
IPC分类号： H03H11/04 , H03F3/45 , H03F3/21 , H01C7/04
摘要： An active filter reduces Electro-Magnetic Interference (EMI) created by current flowing through a power line. The active filter connects to the power line at a single node through a connection capacitor. A sense current flows through the connection capacitor when the power line current changes. This sense current is applied to a non-inverting input of an op amp to drive a power amplifier circuit through a filter capacitor. The power amplifier circuit increases the current drive of the op amp to charge a transfer capacitor that converts the power amplifier output current to a transfer voltage. The transfer capacitor is connected to the connection capacitor so that the transfer voltage is injected back into the power line through the connection capacitor as an injected voltage that compensates for the sensed current. Op amp gain is adjustable by variable resistors that connect to the inverting input of the op amp.

2. 发明授权

US10510743B2 Step fin field-effect-transistor (FinFET) with slim top of fin and thick bottom of fin for electro-static-discharge (ESD) or electrical over-stress (EOS) protection 有权
公开(公告)号：US10510743B2
公开(公告)日：2019-12-17
申请号：US15652645
申请日：2017-07-18
申请人： Hong Kong Applied Science and Technology Research Institute Company, Limited
发明人： Xiaoyong Han , Xiao Huo , Shuli Pan
IPC分类号： H01L29/78 , H01L27/02 , H01L21/265 , H01L29/417 , H01L29/423
摘要： An Electro-Static-Discharge (ESD) protection device has a Fin Field-Effect Transistor (FinFET) with a silicon fin with a step separating a top fin and a bottom fin. The gate wraps around the top fin but not the bottom fin. Normal gate-controlled channel conduction occurs in the top fin between a source and a drain in the top fin. Underneath the conducting channel is a buried conducting region in the bottom fin that conducts after a breakdown voltage is reached during ESD. A ledge, abrupt slope change in the sidewalls of the fin, or a doping increase occurs at the step between the top fin and bottom fin. The bottom fin is 2-3 times wider than the top fin, causing the resistance of the buried conducting region to be 2-3 times less than the resistance of the conducting channel, steering breakdown current away from the channel, reducing failures during breakdown.

3. 发明授权

US09661695B1 Low-headroom constant current source for high-current applications 有权
公开(公告)号：US09661695B1
公开(公告)日：2017-05-23
申请号：US14939081
申请日：2015-11-12
申请人： Hong Kong Applied Science & Technology Research Institute Company Limited
发明人： Guangjie Cai , Ho Ming (Karen) Wan , Chun Fai Wong , Tai Yin Wong
IPC分类号： H03F3/04 , H03F3/30 , H05B33/08 , H03K17/687 , H03F3/45
CPC分类号： H05B33/0806 , H03F3/345 , H03F3/45179 , H03F2200/462 , H03F2200/471 , H03F2200/474 , H03F2200/91 , H03K17/6872 , H05B33/0827 , H05B33/0842
摘要： A low-headroom current driver does not use an op amp or resistor. A sensing transistor having its source connected to a drain of an output transistor senses variations in an output current. The gate, source, and drain voltages of the sensing transistor are mirrored to a sense mirror transistor to control a sense current. The sense current is mirrored to a reference source transistor to generate a mirrored sense current. An error between the mirrored sense current and a fixed reference current is stored as charge on an error-storing capacitor. The stored error charge creates a negative-feedback compensation current that adjusts a gate voltage generated by a feedback-driving transistor. The adjusted gate voltage controls the gate of the output transistor to compensate for the sensed variation in output current. The sensing current is also compensated using a sense-mirror tail transistor connected to the sense mirror transistor.

4. 发明授权

US09191303B2 Systems and methods for creating, managing and communicating users and applications on spontaneous area networks 有权
标题翻译：用于在自发区域网络上创建，管理和传达用户和应用程序的系统和方法
公开(公告)号：US09191303B2
公开(公告)日：2015-11-17
申请号：US13930806
申请日：2013-06-28
申请人： Miraveo, Inc.
发明人： David Fuste Vilella , Jorge Garcia Vidal , Daniel Nemirovsky , Mario Nemirovsky
IPC分类号： H04W4/00 , H04L12/751 , H04W40/00 , H04W84/18 , H04W84/12
CPC分类号： H04L45/02 , H04W40/00 , H04W84/12 , H04W84/18
摘要： A Spontaneous Area Network (SPAN) is formed by mobile and fixed nodes using wireless transmission links between nodes, usually in a nearby geographical area. Applications allow users to create, join, leave, and manage SPANs and groups in a SPAN. Automatic procedures allow nodes to join other SPANs. Transmission power of the wireless network interface is dynamic, varying depending on battery level, type of information to transmit, state and topology of the network. A delay tolerant object layer abstraction creates, modifies, deletes, publishes, and handles Delay Tolerant Distributed Objects (DTDOs). A Patient Transport Protocol (PTP) ensures a reliable transport of information through the network while avoiding congestion conditions. An aggressive and explosive network protocol (AGENET) has routing and forwarding capacities and uses datagrams to establish communication between different nodes of the SPAN. Cooperation and diversity are exploited to react to node mobility that causes frequent changes in network topology and disconnections.
摘要翻译：自动区域网（SPAN）由移动和固定节点使用节点之间的无线传输链路形成，通常在附近的地理区域。应用程序允许用户在SPAN中创建，加入，离开和管理SPAN和组。自动过程允许节点加入其他SPAN。无线网络接口的传输功率是动态的，这取决于电池电量，要发送的信息类型，网络的状态和拓扑。延迟容忍对象层抽象创建，修改，删除，发布和处理延迟容忍分布式对象（DTDO）。患者传输协议（PTP）确保通过网络可靠地传输信息，同时避免拥塞状况。攻击性和爆炸性的网络协议（AGENET）具有路由和转发能力，并使用数据报建立SPAN的不同节点之间的通信。利用合作和多样性对节点移动性做出反应，导致网络拓扑和断开连接的频繁变化。

5. 发明授权

US08321597B2 Flash-memory device with RAID-type controller 有权
标题翻译：具有RAID型控制器的闪存设备
公开(公告)号：US08321597B2
公开(公告)日：2012-11-27
申请号：US13197721
申请日：2011-08-03
申请人： Frank Yu , Abraham C. Ma , Shimon Chen
发明人： Frank Yu , Abraham C. Ma , Shimon Chen
IPC分类号： G06F13/28 , G06F9/00
CPC分类号： G06F13/28 , G06F3/0658 , G06F3/0679 , G06F11/108 , G06F12/0246 , G06F13/385 , G06F21/79 , G06F2212/7208 , G06F2212/7211
摘要： A smart flash drive has one or more levels of smart storage switches and a lower level of single-chip flash devices (SCFD's). A SCFD contains flash memory and controllers that perform low-level bad-block mapping and wear-leveling and logical-to-physical block mapping. The SCFD report their capacity, arrangement, and maximum wear-level count (WLC) and bad block number (BBN) to the upstream smart storage switch, which stores this information in a structure register. The smart storage switch selects the SCFD with the maximum BBN as the target and the SCFD with the lowest maximum WLC as the source of a swap for wear leveling when a WLC exceeds a threshold that rises over time. A top-level smart storage switch receives consolidated capacity, arrangement, WLC, and BBN information from lower-level smart storage switch. Data is striped and optionally scrambled by Redundant Array of Individual Disks (RAID) controllers in all levels of smart storage switches.
摘要翻译：智能闪存驱动器具有一个或多个级别的智能存储交换机和较低级别的单芯片闪存设备（SCFD）。 SCFD包含执行低级坏块映射和磨损均衡以及逻辑到物理块映射的闪存和控制器。 SCFD向上游智能存储交换机报告其容量，布置和最大磨损级数（WLC）和坏块号（BBN），将该信息存储在结构寄存器中。智能存储交换机选择具有最大BBN作为目标的SCFD，并且具有最低最大WLC的SCFD作为WLC超过随时间上升的阈值时的损耗平衡的交换源。顶级智能存储交换机从低级智能存储交换机接收统一的容量，安排，WLC和BBN信息。数据是条带化的，并且可选地由所有级别的智能存储交换机中的冗余冗余阵列（RAID）控制器加扰。

6. 发明授权

US08193854B2 Bi-directional trimming methods and circuits for a precise band-gap reference 有权
标题翻译：用于精确带隙参考的双向修整方法和电路
公开(公告)号：US08193854B2
公开(公告)日：2012-06-05
申请号：US12651993
申请日：2010-01-04
申请人： Xiao Fei Kuang , Kam Chuen Wan , Kwai Chi Chan , Yat To (William) Wong , Kwok Kuen (David) Kwong
发明人： Xiao Fei Kuang , Kam Chuen Wan , Kwai Chi Chan , Yat To (William) Wong , Kwok Kuen (David) Kwong
IPC分类号： G05F3/02
CPC分类号： G05F3/30 , H01C17/22
摘要： A bandgap reference circuit has trimming-up resistors and trimming-down resistors for bi-directional trimming. PNP transistors have base and collectors grounded and emitters connected to parallel resistors. A difference resistor drives an inverting input of an op amp that drives a transistor that generates the bandgap reference voltage Vbg. A sensing resistor connects Vbg to a splitting node that connects to the non-inverting input through a first parallel resistor. The splitting node also connects through a second parallel resistor to the inverting input. Fuses or switches enable the trimming-up and trimming-down resistors. The trimming-up resistors are in series with the sensing resistor and the trimming-down resistors are in series with an output resistor that connects Vbg to reference voltage Vref. The circuit can be designed for a more typical process since bi-directional trimming allows Vref to be raised or lowered. Many circuits need no trimming when targeted for the typical process.
摘要翻译：带隙参考电路具有用于双向修剪的微调电阻和微调电阻。 PNP晶体管的基极和集电极接地，发射极连接到并联电阻。差分电阻驱动驱动产生带隙参考电压Vbg的晶体管的运算放大器的反相输入。感测电阻器将Vbg连接到通过第一并联电阻器连接到非反相输入的分离节点。分离节点还通过第二并联电阻器连接到反相输入端。保险丝或开关使能微调和微调电阻。修整电阻与感测电阻串联，并且减法电阻与将Vbg连接到参考电压Vref的输出电阻串联。该电路可以设计用于更典型的工艺，因为双向修整允许Vref被升高或降低。许多电路在针对典型过程时不需要修剪。

7. 发明授权

US07904655B2 Branching memory-bus module with multiple downlink ports to standard fully-buffered memory modules 有权
标题翻译：将具有多个下行链路端口的内存总线模块分支到标准的全缓冲内存模块
公开(公告)号：US07904655B2
公开(公告)日：2011-03-08
申请号：US12115200
申请日：2008-05-05
申请人： Ramon S. Co
发明人： Ramon S. Co
IPC分类号： G06F13/28
CPC分类号： G06F13/1684 , G06F13/1673 , G11C5/04 , Y02D10/14
摘要： A branching memory-bus module has one uplink port and two or more downlink ports. Frames sent downstream by a host processor are received on the uplink port and repeated to the multiple downlink ports to two or more branches of memory modules. Frames sent upstream to the processor by a memory module on a downlink port are repeated to the uplink port. A branching Advanced Memory Buffer (AMB) on the branching memory-bus module has re-timing and re-synchronizing buffers that repeat frames to the multiple downlink ports. Elastic buffers can merge and synchronize frames from different downlink branches. Separate northbound and southbound lanes may be replaced by bidirectional lanes to reduce pin counts. Latency from the host processor to the farthest memory module is reduced by branching compared with a serial daisy-chain of fully-buffered memory modules. Point-to-point bus segments have only two endpoints despite branching by the branching AMB.
摘要翻译：分支存储器总线模块具有一个上行链路端口和两个或更多个下行链路端口。在主机处理器发送的下游的帧在上行链路端口上被接收并且被重复到多个下行链路端口到存储器模块的两个或更多个分支。通过下行链路端口上的存储器模块向处理器上行发送的帧被重复到上行链路端口。分支存储器总线模块上的分支高级存储器缓冲器（AMB）具有对多个下行链路端口重复帧的重新定时和重新同步缓冲器。弹性缓冲区可以合并和同步来自不同下行链路分支的帧。分开的北行和南行车道可以由双向车道代替，以减少销数。与串行菊花链完全缓冲的内存模块相比，从主处理器到最远的内存模块的延迟减少了。点对点总线段只有两个端点，尽管分支AMB分支。

8. 发明授权

US07797578B2 Fault diagnosis of serially-addressed memory chips on a test adaptor board to a middle memory-module slot on a PC motherboard 有权
标题翻译：将测试适配器板上的串行存储芯片故障诊断到PC主板上的中间存储模块插槽
公开(公告)号：US07797578B2
公开(公告)日：2010-09-14
申请号：US12101138
申请日：2008-04-10
申请人： Ramon S. Co
发明人： Ramon S. Co
IPC分类号： G06F11/00
CPC分类号： G11C29/56 , G11C5/04 , G11C29/56008 , G11C29/56016
摘要： A standard memory module socket is removed from a target DRAM module slot on the component side and the test adaptor board connects to the target DRAM module slot on the reverse (solder) side of a personal computer motherboard, or an extender card may be used. The target DRAM module slot is a middle slot, such as the second or third of four DRAM module slots. The first and fourth DRAM module slots are populated with known good memory modules storing the BIOS at a high address and an operating system image and a test program at a low address. The test program accesses a memory chip in a test socket on a test adaptor board that is connected to the target DRAM module slot to locate defects. The motherboard does not crash since the BIOS, OS image, and test program are not stored in the memory chip under test.
摘要翻译：标准内存模块插座从组件侧的目标DRAM模块插槽中移除，测试适配器板连接到个人计算机主板背面（焊接）侧的目标DRAM模块插槽，或者可以使用扩展卡。目标DRAM模块插槽是中间插槽，例如四个DRAM模块插槽的第二或第三。第一和第四DRAM模块插槽用已知的良好存储器模块填充存储在高地址处的BIOS，操作系统映像和低地址处的测试程序。测试程序访问连接到目标DRAM模块插槽的测试适配器板上的测试插座中的存储芯片，以定位缺陷。主板不会崩溃，因为BIOS，OS映像和测试程序未被存储在被测芯片内。

9. 发明授权

US07741981B1 Dual-use comparator/op amp for use as both a successive-approximation ADC and DAC 有权
标题翻译：双用比较器/运算放大器用作逐次逼近ADC和DAC
公开(公告)号：US07741981B1
公开(公告)日：2010-06-22
申请号：US12345844
申请日：2008-12-30
申请人： Ho Ming Karen Wan , Yat To William Wong , Kwai Chi Chan , Hok Mo Yau , Tin Ho Andy Wu , Kwok Kuen David Kwong
发明人： Ho Ming Karen Wan , Yat To William Wong , Kwai Chi Chan , Hok Mo Yau , Tin Ho Andy Wu , Kwok Kuen David Kwong
IPC分类号： H03M1/00
CPC分类号： H03M1/02 , H03M1/468 , H03M1/804
摘要： A re-configurable circuit acts as an Analog-to-Digital Converter (ADC) and as a digital-to-analog converter (DAC). An array of binary-weighted capacitors stores an analog input. Switches connect different capacitors in the array to fixed voltages that cause charge-sharing with a terminal capacitor. The voltage of the terminal capacitor is compared by a re-configurable comparator stage for each different combination of the capacitors. The comparison results are analyzed to determine the closest digital value for the analog input. In DAC mode, the array capacitors are switched based on an input digital value. The switched capacitors connect to a charge-sharing line to generate an analog voltage that is applied to the re-configurable comparator stage. A differential amplifier generates a buffered analog voltage that is fed back to the other input of the re-configurable comparator stage for unity gain. The gain of the re-configurable comparator stage adjusts for ADC and DAC modes.
摘要翻译：一个可重新配置的电路充当模数转换器（ADC）和数模转换器（DAC）。一组二进制加权电容器存储模拟输入。开关将阵列中的不同电容连接到固定电压，从而与端子电容器进行电荷共享。对于电容器的每个不同组合，端子电容器的电压通过可重新配置的比较器级进行比较。分析比较结果以确定模拟输入的最接近的数字值。在DAC模式下，基于输入数字值切换阵列电容器。开关电容器连接到电荷共享线路以产生施加到可重新配置的比较器级的模拟电压。差分放大器产生缓冲的模拟电压，反馈到可重新配置的比较器级的另一个输入以获得单位增益。可重新配置的比较器级的增益适用于ADC和DAC模式。

10. 发明授权

US07657692B2 High-level bridge from PCIE to extended USB 失效
标题翻译：从PCIE到扩展USB的高级桥
公开(公告)号：US07657692B2
公开(公告)日：2010-02-02
申请号：US11926636
申请日：2007-10-29
申请人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen , Horng-Yee Chou
发明人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen , Horng-Yee Chou
IPC分类号： G06F13/00
CPC分类号： G06F13/28 , G06F12/1416 , G06F21/32 , G06F21/78 , G06K9/00087 , G06K19/07 , G06K19/07354 , G07C9/00087
摘要： An extended universal-serial bus (EUSB) bridge to a host computer can have peripheral component interconnect express (PCIE) protocol layers on one side of the bridge, and EUSB layers on the other side of the bridge, with a high-level bridging converter module connecting the upper layers. The PCIE physical, data-link, and transport layers may be eliminated by integrating the bridge with an I/O controller. PCIE requests and data payloads are directly sent to the bridge, rather than low-level PCIE physical signals. The PCIE data payloads are converted to EUSB data payloads by a high-level direct bridging converter module. Then the EUSB data payloads are passed down to an EUSB transaction layer, an EUSB data-link layer, and an EUSB physical layer which drives and senses physical electrical signals on both differential pairs of the EUSB bus.
摘要翻译：到主机的扩展通用串行总线（EUSB）桥可以在桥的一侧具有外围组件互连快速（PCIE）协议层，并且在桥的另一侧可以具有高级桥接转换器模块连接上层。可以通过将桥与I / O控制器集成来消除PCIE物理，数据链路和传输层。 PCIE请求和数据有效载荷直接发送到桥，而不是低级PCIE物理信号。 PCIE数据有效载荷通过高级直接桥接转换器模块转换为EUSB数据有效载荷。然后，EUSB数据有效载荷被传递到EUSB事务层，EUSB数据链路层和EUSB物理层，其在EUSB总线的两个差分对上驱动和感测物理电信号。

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