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1. 发明授权

US08341332B2 Multi-level controller with smart storage transfer manager for interleaving multiple single-chip flash memory devices 有权
标题翻译：具有智能存储传输管理器的多电平控制器，用于交错多个单芯片闪存设备
公开(公告)号：US08341332B2
公开(公告)日：2012-12-25
申请号：US12186471
申请日：2008-08-05
申请人： Abraham C. Ma , David Q. Chow , Charles C. Lee , Frank Yu
发明人： Abraham C. Ma , David Q. Chow , Charles C. Lee , Frank Yu
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0246 , G06F3/0613 , G06F3/0616 , G06F3/064 , G06F3/0658 , G06F3/0664 , G06F3/0688 , G06F2212/7201 , G06F2212/7208 , G06F2212/7211 , G11C13/0004
摘要： A solid-state disk (SSD) has a smart storage switch with a smart storage transaction manager that re-orders host commands for accessing downstream single-chip flash-memory devices. Each single-chip flash-memory device has a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory blocks in the single-chip flash-memory device. Wear-leveling and bad block remapping are preformed by each single-chip flash-memory device, and at a higher level by a virtual storage processor in the smart storage switch. Virtual storage bridges between the smart storage transaction manager and the single-chip flash-memory devices bridge LBA transactions over LBA buses to the single-chip flash-memory devices. Data striping and interleaving among multiple channels of the single-chip flash-memory device is controlled at a high level by the smart storage transaction manager, while further interleaving and remapping may be performed within each single-chip flash-memory device.
摘要翻译：固态磁盘（SSD）具有智能存储交换机，智能存储交易管理器重新命令用于访问下游单芯片闪存设备的主机命令。每个单芯片闪存设备具有将逻辑块地址（LBA）转换为访问单芯片闪存设备中的闪存块的物理块地址（PBA）的较低级别的控制器。磨损均衡和坏块重映射由每个单芯片闪存设备执行，并且在智能存储交换机中的虚拟存储处理器处于更高级别。智能存储事务管理器和单芯片闪存设备之间的虚拟存储网桥将LBA总线上的LBA交易桥接到单芯片闪存设备。单芯片闪速存储器件的多个通道之间的数据条带化和交错由智能存储事务管理器控制在高电平，而可以在每个单芯片闪速存储器件内执行进一步的交错和重新映射。

2. 发明授权

US08296467B2 Single-chip flash device with boot code transfer capability 有权
标题翻译：具有启动代码传输功能的单芯片闪存设备
公开(公告)号：US08296467B2
公开(公告)日：2012-10-23
申请号：US12947211
申请日：2010-11-16
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma , Shimon Chen
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma , Shimon Chen
IPC分类号： G06F3/00 , G06F12/00
CPC分类号： G06F9/4401 , G06F13/387 , G06F2213/3854
摘要： A Multi-Media Card (MMC) Single-Chip Flash Device (SCFD) contains a MMC flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. An initial boot loader is read from the first page of flash by a state machine and written to a small RAM. A central processing unit (CPU) in the microcontroller reads instructions from the small RAM, executing the initial boot loader, which reads more pages from flash. These pages are buffered by the small RAM and written to a larger DRAM. Once an extended boot sequence is written to DRAM, the CPU toggles a RAM_BASE bit to cause instruction fetching from DRAM. Then the extended boot sequence is executed from DRAM, copying an OS image from flash to DRAM. Boot code and control code are selectively overwritten during a code updating operation to eliminate stocking issues.
摘要翻译：多媒体卡（MMC）单片闪存器件（SCFD）包含一个MMC闪存单片机和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是随机寻址。初始引导加载程序由状态机从闪存的第一页读取并写入小RAM。微控制器中的中央处理单元（CPU）从小型RAM读取指令，执行初始启动加载程序，从Flash读取更多的页面。这些页面被小RAM缓冲并写入较大的DRAM。一旦将扩展引导顺序写入DRAM，CPU将切换一个RAM_BASE位，以使DRAM从DRAM获取指令。然后从DRAM执行扩展启动顺序，将OS映像从闪存复制到DRAM。引导代码和控制代码在代码更新操作期间被有选择地覆盖以消除存货问题。

3. 发明授权

US08166221B2 Low-power USB superspeed device with 8-bit payload and 9-bit frame NRZI encoding for replacing 8/10-bit encoding 失效
标题翻译：低功耗USB超速设备，具有8位有效负载和9位帧NRZI编码，用于替换8/10位编码
公开(公告)号：US08166221B2
公开(公告)日：2012-04-24
申请号：US12831160
申请日：2010-07-06
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma , Jim Chin-Nan Ni , Shimon Chen
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma , Jim Chin-Nan Ni , Shimon Chen
IPC分类号： G06F13/12 , G06F13/00
CPC分类号： G06F13/385 , G11C16/102 , G11C2216/30 , Y02D10/14 , Y02D10/151
摘要： A Low-power flash-memory device uses a modified Universal-Serial-Bus (USB) 3.0 Protocol to reduce power consumption. The bit clock is slowed to reduce power and the need for pre-emphasis when USB cable lengths are short in applications. Data efficiency is improved by eliminating the 8/10-bit encoder and instead encoding sync and framing bytes as 9-bit symbols. Data bytes are expanded by bit stuffing only when a series of six ones occurs in the data. Header and payload data is transmitted as nearly 8-bits per data byte while framing is 9-bits per symbol, much less than the standard 10 bits per byte. Low-power link layers, physical layers, and scaled-down protocol layers are used. A card reader converter hub allows USB hosts to access low-power USB devices. Only one flash device is accessed, reducing power compared with standard USB broadcasting to multiple devices.
摘要翻译：低功耗闪存设备使用修改后的通用串行总线（USB）3.0协议来降低功耗。当应用程序中的USB电缆长度短时，位时钟减慢了功率，并且需要预加重。通过消除8/10位编码器并将同步和成帧字节编码为9位符号来提高数据效率。数据字节只有在数据中出现一系列6个数据字节时才能通过位填充进行扩展。标头和有效载荷数据以每个数据字节近8位的形式传输，而成帧是每个符号9位，远远小于每个字节的标准10位。使用低功率链路层，物理层和缩小协议层。读卡器转换器集线器允许USB主机访问低功耗USB设备。只有一个闪存设备被访问，与标准的USB广播相比，将功耗降低到多个设备。

4. 发明授权

US08061905B2 Multi-level cell (MLC) dual personality extended fiber optic flash memory device 失效
标题翻译：多级单元（MLC）双重人格扩展光纤闪存设备
公开(公告)号：US08061905B2
公开(公告)日：2011-11-22
申请号：US12111872
申请日：2008-04-29
申请人： Abraham Ma , I-Kang Yu , David Nguyen , Charles C. Lee , Ming-Shiang Shen
发明人： Abraham Ma , I-Kang Yu , David Nguyen , Charles C. Lee , Ming-Shiang Shen
IPC分类号： G02B6/38
CPC分类号： G06K19/07732
摘要： A multi-level cell (MLC) dual-personality extended fiber optic flash drive includes a MLC dual-personality extended fiber optic Universal Serial Bus (USB) plug connector connected to a dual-personality extended fiber optic flash drive and being removably connectable to a host. The connector is adaptable to receive electrical data and optical data. A transceiver, located on the flash drive, is operative to convert received electrical data to optical data or to convert received optical data to electrical data.
摘要翻译：多级单元（MLC）双人格扩展光纤闪存驱动器包括连接到双人格扩展光纤闪存驱动器的MLC双人格扩展光纤通用串行总线（USB）插头连接器，并且可移除地连接到主办。该连接器适用于接收电气数据和光学数据。位于闪存驱动器上的收发器用于将接收的电数据转换为光学数据或将接收到的光学数据转换为电气数据。

5. 发明授权

US07934074B2 Flash module with plane-interleaved sequential writes to restricted-write flash chips 有权
标题翻译：闪存模块，具有平面交错顺序写入限制写入闪存芯片
公开(公告)号：US07934074B2
公开(公告)日：2011-04-26
申请号：US11871011
申请日：2007-10-11
申请人： Charles C. Lee , Frank Yu , Ming-Shiang Shen , Abraham C. Ma , David Q. Chow
发明人： Charles C. Lee , Frank Yu , Ming-Shiang Shen , Abraham C. Ma , David Q. Chow
IPC分类号： G06F12/06
CPC分类号： G06F12/0246 , G06F12/0607 , G06F2212/7201 , G06F2212/7208 , G11C11/5621 , G11C16/0408
摘要： A flash memory controller on a PCIE bus controls flash-memory modules on a flash bus. The flash-memory modules are plane-interleaved using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. A physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. A RAM physical page valid table tracks valid pages in the four planes, while a RAM mapping table stores the plane, block, and page addresses for logical sectors generated by the physical sequential address counter.
摘要翻译： PCIE总线上的闪存控制器控制闪存总线上的闪存模块。闪存模块使用从逻辑块索引的最低位提取的交错比特进行平面交织。这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。物理顺序地址计数器通过在中间物理块比特之前递增平面交织比特，然后将MSB重新定位到中间物理块比特之上来生成物理块号。这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。 RAM物理页有效表跟踪四个平面中的有效页面，而RAM映射表存储由物理顺序地址计数器生成的逻辑扇区的平面，块和页面地址。

6. 发明申请

US20110066920A1 Single-Chip Multi-Media Card/Secure Digital (MMC/SD) Controller Reading Power-On Boot Code from Integrated Flash Memory for User Storage 审中-公开
标题翻译：单芯片多媒体卡/安全数字（MMC / SD）控制器从用于存储用户的集成闪存中读取上电引导代码
公开(公告)号：US20110066920A1
公开(公告)日：2011-03-17
申请号：US12950533
申请日：2010-11-19
申请人： I-Kang Yu , Abraham C. Ma , Charles C. Lee
发明人： I-Kang Yu , Abraham C. Ma , Charles C. Lee
IPC分类号： G06F11/08 , G06F12/02 , G06F13/20
CPC分类号： G06F13/28 , G06F3/0679 , G06F11/1064 , G06F13/385 , Y02D10/14 , Y02D10/151
摘要： A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.
摘要翻译：多媒体卡/安全数字（MMC / SD）单芯片闪存设备包含一个MMC / SD闪存微控制器和闪存大容量存储块，其中包含易于寻址的闪存阵列，而不是随机寻址。来自主机MMC / SD总线的MMC / SD事务由MMC / SD闪存微控制器上的总线收发器读取。响应于MMC / SD事务中的命令，激活在MMC / SD闪存单片机中的CPU上执行的各种例程。 MMC / SD闪存单片机中的闪存控制器将数据从总线收发器传输到闪存大容量存储块以进行存储。不是从耦合到CPU的内部ROM引导，引导加载程序由DMA从闪存大容量存储块的第一页传输到内部RAM。在上电时，闪存将从第一页自动读取。 CPU然后从内部RAM执行引导加载程序来加载控制程序。

7. 发明授权

US07889544B2 High-speed controller for phase-change memory peripheral device 失效
标题翻译：用于相变存储器外围设备的高速控制器
公开(公告)号：US07889544B2
公开(公告)日：2011-02-15
申请号：US11770642
申请日：2007-06-28
申请人： David Q. Chow , Charles C. Lee , Frank I-Kang Yu
发明人： David Q. Chow , Charles C. Lee , Frank I-Kang Yu
IPC分类号： G11C11/00
CPC分类号： G06F12/0804 , G06F12/0238 , G06F13/16 , G06F13/161 , G06F2212/1016 , G06F2212/2022 , G11C7/10 , G11C7/1015 , G11C8/08 , G11C8/12 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C13/0061 , G11C13/0069 , G11C2013/0071 , G11C2211/5641 , G11C2213/79
摘要： Peripheral devices store data in non-volatile phase-change memory (PCM). PCM cells have alloy resistors with high-resistance amorphous states and low-resistance crystalline states. The peripheral device can be a Multi-Media Card/Secure Digital (MMC/SD) card. A PCM controller accesses PCM memory devices. Various routines that execute on a CPU in the PCM controller are activated in response to commands in the host-bus transactions. The PCM system increases the throughput of one or more phase-change memory devices by performing one or more of a read-ahead memory operation, a write-ahead memory write operation, a larger page memory write operation, a wider data bus memory write operation, a multi-channel concurrent multi-bank interleaving memory read or write operation, a write-cache memory write operation, and any combination thereof.
摘要翻译：外围设备将数据存储在非易失性相变存储器（PCM）中。 PCM单元具有具有高电阻非晶态和低电阻晶体态的合金电阻。外围设备可以是多媒体卡/安全数字（MMC / SD）卡。 PCM控制器访问PCM存储器设备。响应于主机总线事务中的命令，激活在PCM控制器中的CPU上执行的各种例程。 PCM系统通过执行预读存储器操作，预写存储器写操作，较大页存储器写操作，更宽数据总线存储器写操作中的一个或多个来增加一个或多个相变存储器件的吞吐量多通道同时多存储体交错存储器读或写操作，写高速缓存存储器写操作及其任意组合。

8. 发明授权

US07886108B2 Methods and systems of managing memory addresses in a large capacity multi-level cell (MLC) based flash memory device 失效
标题翻译：在基于大容量多级单元（MLC）的闪存设备中管理存储器地址的方法和系统
公开(公告)号：US07886108B2
公开(公告)日：2011-02-08
申请号：US12025706
申请日：2008-02-04
申请人： Charles C. Lee , I-Kang Yu , David Nguyen , Abraham Chih-Kang Ma , Ming-Shiang Shen
发明人： Charles C. Lee , I-Kang Yu , David Nguyen , Abraham Chih-Kang Ma , Ming-Shiang Shen
IPC分类号： G06F13/16
CPC分类号： G06F12/0246 , G06F12/0607 , G11C11/5621 , G11C16/0408 , G11C16/349 , G11C16/3495
摘要： Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.
摘要翻译：描述了在大容量多级基于单元的闪存设备中管理存储器地址的方法和系统。根据一个方面，一种闪存设备包括一个使用索引方案来管理逻辑到物理地址相关的处理单元。闪存被分为N组。每个集合包括多个条目（即，块）。对于物理块号和相关联的页面使用信息（以下称为“PLTPPUI”）的N组部分逻辑条目号被存储在基于MLC的闪速存储器的保留区域中。只有一个N集被加载以寻址相关和页面使用存储器（ACPUM），这是一个有限大小的随机存取存储器（RAM）。在一个实施例中，静态RAM（SRAM）被实现用于地址相关的快速访问时间。与数据传输请求一起接收的LSA指示将N组PLTPPUI中的哪一个加载到ACPUM中。

9. 发明授权

US07865630B2 Single-chip multi-media card/secure digital (MMC/SD) controller reading power-on boot code from integrated flash memory for user storage 有权
标题翻译：单芯片多媒体卡/安全数字（MMC / SD）控制器从集成闪存读取上电启动代码，用于用户存储
公开(公告)号：US07865630B2
公开(公告)日：2011-01-04
申请号：US12426378
申请日：2009-04-20
申请人： I-Kang Frank Yu , Abraham C. Ma , Charles C. Lee
发明人： I-Kang Frank Yu , Abraham C. Ma , Charles C. Lee
IPC分类号： G06F3/00 , G06F13/28 , G06F13/12 , G06F9/00
CPC分类号： G06F13/28 , Y02D10/14
摘要： A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.
摘要翻译：多媒体卡/安全数字（MMC / SD）单芯片闪存设备包含一个MMC / SD闪存微控制器和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是随机寻址。来自主机MMC / SD总线的MMC / SD事务由MMC / SD闪存微控制器上的总线收发器读取。响应于MMC / SD事务中的命令，激活在MMC / SD闪存单片机中的CPU上执行的各种例程。 MMC / SD闪存单片机中的闪存控制器将数据从总线收发器传输到闪存大容量存储块以进行存储。不是从耦合到CPU的内部ROM引导，引导加载程序由DMA从闪存大容量存储块的第一页传输到内部RAM。在上电时，闪存将从第一页自动读取。 CPU然后从内部RAM执行引导加载程序来加载控制程序。

10. 发明授权

US07844763B2 Differential data transfer for flash memory card 有权
标题翻译：闪存卡差分数据传输
公开(公告)号：US07844763B2
公开(公告)日：2010-11-30
申请号：US12608842
申请日：2009-10-29
申请人： I-Kang Yu , Horng-Yee Chou , Szu-Kuang Chou , Charles C. Lee
发明人： I-Kang Yu , Horng-Yee Chou , Szu-Kuang Chou , Charles C. Lee
IPC分类号： G06F13/12 , G06F13/00
CPC分类号： G06F13/387 , G06F13/385 , G06K19/07732 , G06K19/07733 , Y02D10/14 , Y02D10/151
摘要： A flash memory card includes a differential datapath that enables communications between the flash memory card and a host device to be performed using differential signals. The differential datapath can translate between the differential signals and card-specific signals that control read/write operations to the memory array of the flash memory card. The card-specific signals can be standard MultimediaCard, Secure-Digital card, Memory Stick, or CompactFlash card signals, among others. A host device that provides differential data transfer capability can include a similar differential datapath. By using differential data transfer rather than conventional clocked data transfer, overall data bandwidth between a flash memory card and a host device can be significantly increased, while simultaneously decreasing power consumption and pin requirements.
摘要翻译：闪存卡包括差分数据路径，其使得能够使用差分信号执行闪存卡与主机设备之间的通信。差分数据路径可以在差分信号和控制对闪存卡的存储器阵列的读/写操作的卡特定信号之间进行转换。卡特定信号可以是标准的多媒体卡，安全数字卡，记忆棒或CompactFlash卡信号。提供差分数据传输能力的主机设备可以包括类似的差分数据路径。通过使用差分数据传输而不是传统的时钟数据传输，闪存卡和主机设备之间的总体数据带宽可以显着增加，同时降低功耗和引脚要求。

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