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1. 发明申请

US20130141264A1 REDUCED RESIDUAL OFFSET SIGMA DELTA ANALOG-TO-DIGITAL CONVERTER (ADC) WITH CHOPPER TIMING AT END OF INTEGRATING PHASE BEFORE TRAILING EDGE 有权
标题翻译：减少残留偏移SIGMA DELTA模拟数字转换器（ADC）在跟踪边缘之前的整合阶段结束时的切换时序
公开(公告)号：US20130141264A1
公开(公告)日：2013-06-06
申请号：US13308737
申请日：2011-12-01
申请人： Ho Ming (Karen) WAN , Yat To (William) WONG , Kwai Chi CHAN
发明人： Ho Ming (Karen) WAN , Yat To (William) WONG , Kwai Chi CHAN
IPC分类号： H03M3/02 , H03M1/12
CPC分类号： H03M3/34 , H03M3/43 , H03M3/454
摘要： An analog-to-digital converter (ADC) has a chopper-stabilized sigma-delta modulator (SDM). The SDM uses switched-capacitor integrators to sample, hold, and integrate an analog input in response to non-overlapping multi-phase clocks. Chopper multipliers are inserted on the inputs and outputs of an op amp in a first stage integrator. The chopper multipliers swap or pass through differential inputs in response to non-overlapping chopper clocks. A master clock operating at a frequency of the multi-phase clocks is divided down to trigger generation of the chopper clocks. Delay lines ensure that the edges of the chopper clocks occur before the edges of the multi-phase clocks. The chopper multipliers have already switched and are thus stable when multi-phase clocks change so charge injection at switches controlled by the multi-phase clocks is not immediately modulated by chopper multipliers. This clock timing increases the time available to respond to charge injection at switches improving linearity.
摘要翻译：模数转换器（ADC）具有斩波稳定的Σ-Δ调制器（SDM）。 SDM使用开关电容积分器来采样，保持和集成模拟输入以响应不重叠的多相时钟。斩波倍增器插入在第一级积分器中的运算放大器的输入和输出端。斩波器乘法器响应于不重叠的斩波时钟交换或通过差分输入。以多相时钟频率工作的主时钟被分频以触发斩波时钟的产生。延迟线确保斩波时钟的边沿在多相时钟的边沿之前发生。当多相时钟变化时，斩波倍增器已经切换并稳定，因此在由多相时钟控制的开关处的电荷注入不会被斩波乘法器立即调制。该时钟定时增加了可以在改善线性度的开关处对电荷注入进行响应的时间。

2. 发明授权

US08421658B1 Parallel pipelined calculation of two calibration values during the prior conversion cycle in a successive-approximation-register analog-to-digital converter (SAR-ADC) 有权
标题翻译：在逐次逼近寄存器模数转换器（SAR-ADC）中，在先前的转换周期内对两个校准值进行并行流水线计算，
公开(公告)号：US08421658B1
公开(公告)日：2013-04-16
申请号：US13304346
申请日：2011-11-24
申请人： Hok Mo Yau , Tin Ho (Andy) Wu , Kam Chuen Wan , Yat To (William) Wong
发明人： Hok Mo Yau , Tin Ho (Andy) Wu , Kam Chuen Wan , Yat To (William) Wong
IPC分类号： H03M1/10
CPC分类号： H03M1/1004 , H03M1/1047 , H03M1/468
摘要： A Successive-Approximation Register Analog-to-Digital Converter (SAR-ADC) predicts compensation values for use in a future cycle. A compensation value is applied to capacitors in a calibration Y-side capacitor array to compensate for capacitance errors in a binary-weighted X-side capacitor array. Two compute engines pre-calculate predicted-0 and predicted-1 compensation values for a next bit to be converted. At the end of the current cycle when the comparator determines the current bit, the comparator also controls a mux to select one of the two predicted compensation values. Thus the compensation value is available at the beginning of the next bit's cycle, eliminating a long calculation delay. The compensation value for the first bit to be converted, such as the MSB, is calculated during calibration. Compensation values for other bits are data-dependent. Calibration values are accumulated during calibration to generate the first conversion compensation value for the first bit to be converted.
摘要翻译：逐次近似寄存器模数转换器（SAR-ADC）预测在未来周期中使用的补偿值。补偿值用于校准Y侧电容器阵列中的电容器，以补偿二进制加权的X侧电容器阵列中的电容误差。两个计算引擎预先计算下一个要转换的位的预测0和预测-1补偿值。在比较器确定当前位的当前周期结束时，比较器还控制多路复用器来选择两个预测补偿值之一。因此，补偿值在下一位循环开始时可用，消除了长时间的计算延迟。在校准期间计算要转换的第一位的补偿值，例如MSB。其他位的补偿值依赖于数据。在校准期间累积校准值，以生成要转换的第一个位的第一个转换补偿值。

3. 发明申请

US20100164770A1 MULTI-STAGE COMPARATOR WITH OFFSET CANCELING CAPACITOR ACROSS SECONDARY DIFFERENTIAL INPUTS FOR HIGH-SPEED LOW-GAIN COMPARE AND HIGH-GAIN AUTO-ZEROING 有权
标题翻译：具有偏移取消电容器的多级比较器，用于高速低增益比较和高增益自动调零的二次差分输入
公开(公告)号：US20100164770A1
公开(公告)日：2010-07-01
申请号：US12347113
申请日：2008-12-31
申请人： Ho Ming (Karen) Wan , Yat To (William) Wong , Kwai Chi Chan , Kwok Kuen Kwong
发明人： Ho Ming (Karen) Wan , Yat To (William) Wong , Kwai Chi Chan , Kwok Kuen Kwong
IPC分类号： H03M1/12 , H03M1/00 , H03F3/217
CPC分类号： H03F3/005 , H03F3/45183 , H03F2200/375 , H03F2200/555 , H03F2203/45536 , H03F2203/45544 , H03F2203/45586 , H03F2203/45616 , H03F2203/45631 , H03F2203/45678 , H03F2203/45702 , H03F2203/45726 , H03F2203/45732 , H03M1/0607 , H03M1/0682 , H03M1/46
摘要： An Analog-to-Digital Converter (ADC) has a Successive-Approximation-Register (SAR) driving a digital-to-analog converter (DAC) that generates an analog voltage compared to an input voltage by a series of stages. The last stage feeds a compare signal to the SAR. Each stage has a dual-input differential amplifier that operates as a unity gain op amp during an auto-zeroing phase and as a high-speed low-gain amplifier during an amplifying phase. The dual-input differential amplifier has two pairs of differential inputs. A secondary pair has an offset-storing capacitor across it, and connects to the output pair through feedback switches during auto-zeroing. A primary pair connects to stage inputs through input switches during the amplifying phase. Since two pairs of differential inputs are provided to the dual-input differential amplifier, the offset capacitor is completely isolated from the input pair. The current sink in the dual-input differential amplifier is adjusted higher during the amplifying period.
摘要翻译：模数转换器（ADC）具有驱动数模转换器（DAC）的逐次逼近寄存器（SAR），其通过一系列级与输入电压相比产生模拟电压。最后一个阶段向SAR提供比较信号。每个阶段都有一个双输入差分放大器，在自动归零阶段作为单位增益运算放大器工作，在放大阶段则作为高速低增益放大器工作。双输入差分放大器有两对差分输入。辅助对在其之间具有一个补偿存储电容器，并在自动归零期间通过反馈开关连接到输出对。在放大阶段，初级对通过输入开关连接到级输入。由于两对差分输入提供给双输入差分放大器，所以偏移电容与输入对完全隔离。在放大期间，双输入差分放大器中的电流吸收器被调高。

4. 发明授权

US07710094B1 Current-mode-controlled current sensor circuit for power switching converter 有权
标题翻译：用于电源开关变换器的电流模式控制电流传感器电路
公开(公告)号：US07710094B1
公开(公告)日：2010-05-04
申请号：US12333979
申请日：2008-12-12
申请人： Yat To William Wong , Xiao Fei Kuang , Kam Chuen Wan , Kwok Kuen David Kwong
发明人： Yat To William Wong , Xiao Fei Kuang , Kam Chuen Wan , Kwok Kuen David Kwong
IPC分类号： G05F1/00 , G05F3/02 , G05F3/16
CPC分类号： H02M3/156 , G01R19/0092 , H02M2001/0009
摘要： A power converter has a power transistor driving a power current through an inductor to provide a controlled power-supply voltage. The power transistor is on during a first state but off during a second state when a sink transistor reduces the power current through the inductor. Both voltage sensing of the power-supply voltage and current sensing at the power transistor provide feedback to control the amount of time that the first state is active, and thus control the power current. Current sensing is provided by a smaller minor transistor in parallel with the power transistor. The minor transistor turns on after the power transistor to reduce disturbance spikes. Switches connect sources of the power and mirror transistors to an amplifier that drives a sensing transistor. The sensing transistor generates a sensing voltage from the mirror transistor source. During the second state the amplifier's inputs are equalized to provide fast response.
摘要翻译：功率转换器具有驱动通过电感器的功率电流以提供受控的电源电压的功率晶体管。功率晶体管在第一状态期间导通，而在第二状态期间，当晶体管晶体管降低通过电感器的功率电流时，功率晶体管截止。在功率晶体管处的电源电压和电流感测的两个电压检测提供反馈以控制第一状态是有效的时间量，从而控制功率电流。电流感测由与功率晶体管并联的较小次级晶体管提供。次晶体管在功率晶体管之后导通，以减少干扰尖峰。将电源和镜像晶体管的源极连接到驱动感测晶体管的放大器。感测晶体管产生来自反射镜晶体管源的感测电压。在第二状态期间，放大器的输入被均衡以提供快速响应。

5. 发明授权

US08643337B2 Single-power-transistor battery-charging circuit using voltage-boosted clock 有权
标题翻译：使用升压时钟的单功率晶体管电池充电电路
公开(公告)号：US08643337B2
公开(公告)日：2014-02-04
申请号：US13179107
申请日：2011-07-08
申请人： Kwok Kuen David Kwong , Yat To William Wong , Ho Ming Karen Wan , Chik Wai David Ng
发明人： Kwok Kuen David Kwong , Yat To William Wong , Ho Ming Karen Wan , Chik Wai David Ng
IPC分类号： H02J7/00
CPC分类号： H02J7/0031
摘要： A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.
摘要翻译：充电/放电保护电路可保护电池免受可连接到充电器或便携式电子设备的电源的充电器节点上的意外短路。单个n沟道功率晶体管具有控制电池和充电器节点之间的通道的栅极。门通过栅极耦合晶体管连接到充电器节点，以关闭功率晶体管，从而提供电池隔离。门通过由使能信号激活的开关由升压时钟驱动。使能信号还激活接地晶体管以对栅极耦合晶体管的栅极接地。比较器比较充电器和电池节点的电压，并且比较输出被锁存以产生使能信号。反向使能信号激活第二开关，其将升压电压的时钟驱动到栅极耦合晶体管的栅极，以关断功率晶体管。

6. 发明申请

US20110163799A1 Bi-directional Trimming Methods and Circuits for a Precise Band-Gap Reference 有权
标题翻译：用于精确带隙参考的双向修整方法和电路
公开(公告)号：US20110163799A1
公开(公告)日：2011-07-07
申请号：US12651993
申请日：2010-01-04
申请人： Xiao Fei KUANG , Kam Chuen WAN , Kwai Chi CHAN , Yat To (William) WONG , Kwok Kuen (David) KWONG
发明人： Xiao Fei KUANG , Kam Chuen WAN , Kwai Chi CHAN , Yat To (William) WONG , Kwok Kuen (David) KWONG
IPC分类号： G05F3/02
CPC分类号： G05F3/30 , H01C17/22
摘要： A bandgap reference circuit has trimming-up resistors and trimming-down resistors for bi-directional trimming. PNP transistors have base and collectors grounded and emitters connected to parallel resistors. A difference resistor drives an inverting input of an op amp that drives a transistor that generates the bandgap reference voltage Vbg. A sensing resistor connects Vbg to a splitting node that connects to the non-inverting input through a first parallel resistor. The splitting node also connects through a second parallel resistor to the inverting input. Fuses or switches enable the trimming-up and trimming-down resistors. The trimming-up resistors are in series with the sensing resistor and the trimming-down resistors are in series with an output resistor that connects Vbg to reference voltage Vref. The circuit can be designed for a more typical process since bi-directional trimming allows Vref to be raised or lowered. Many circuits need no trimming when targeted for the typical process.
摘要翻译：带隙参考电路具有用于双向修剪的微调电阻和微调电阻。 PNP晶体管的基极和集电极接地，发射极连接到并联电阻。差分电阻驱动驱动产生带隙参考电压Vbg的晶体管的运算放大器的反相输入。感测电阻器将Vbg连接到通过第一并联电阻器连接到非反相输入的分离节点。分离节点还通过第二并联电阻器连接到反相输入端。保险丝或开关使能微调和微调电阻。修整电阻与感测电阻串联，并且减法电阻与将Vbg连接到参考电压Vref的输出电阻串联。该电路可以设计用于更典型的工艺，因为双向修整允许Vref被升高或降低。许多电路在针对典型过程时不需要修剪。

7. 发明授权

US07812757B1 Hybrid analog-to-digital converter (ADC) with binary-weighted-capacitor sampling array and a sub-sampling charge-redistributing array for sub-voltage generation 有权
标题翻译：具有二进制加权电容采样阵列的混合模数转换器（ADC）和用于子电压发生的子采样电荷重分配阵列
公开(公告)号：US07812757B1
公开(公告)日：2010-10-12
申请号：US12483250
申请日：2009-06-12
申请人： Yat To William Wong , Kam Chuen Wan , Kwok Kuen David Kwong
发明人： Yat To William Wong , Kam Chuen Wan , Kwok Kuen David Kwong
IPC分类号： H03M1/12
CPC分类号： H03M1/468 , H03M1/68 , H03M1/804 , H03M1/806
摘要： A hybrid Analog-to-Digital Converter (ADC) has a binary-weighted capacitor array and a sub-voltage capacitor array that are coupled together by a coupling capacitor. The sub-voltage capacitor array uses a minimum capacitor size that matches the minimum capacitor size of the binary-weighted capacitor array. The coupling capacitor is double the minimum size and reduces a voltage effect on a charge sharing line by half. Second coupling capacitors in the sub-voltage capacitor array each reduce the voltage effect by half, so that first, second, and third sub-voltage capacitors in the sub-voltage capacitor array produce ½, ¼, and ⅛ voltage swings using the minimum size capacitance. Only MSB capacitors in the binary-weighted capacitor array sample the analog input voltage. During conversion, MSB's from a Successive-Approximation-Register (SAR) are applied to binary-weighted capacitors while LSB's are applied to sub-voltage capacitors. The total capacitance is reduced by applying the LSB's only to the sub-voltage capacitor array.
摘要翻译：混合模数转换器（ADC）具有通过耦合电容器耦合在一起的二进制加权电容器阵列和子电压电容器阵列。子电压电容器阵列使用与二进制加权电容器阵列的最小电容器尺寸匹配的最小电容器尺寸。耦合电容是最小尺寸的两倍，并将电荷共享线上的电压降低一半。次级电容器阵列中的第二耦合电容器将电压效应降低一半，使得次级电压电容器阵列中的第一，第二和第三子电压电容器使用最小尺寸产生½，¼和⅛电压摆幅电容。二进制加权电容阵列中只有MSB电容采样模拟输入电压。在转换期间，来自连续近似寄存器（SAR）的MSB被应用于二进制加权电容器，而LSB被应用于子电压电容器。通过将LSB仅施加到子电压电容器阵列来减小总电容。

8. 发明授权

US07795976B2 Slew-rate-enhanced error amp with adaptive transconductance and single dominant pole shared by main and auxiliary amps 有权
标题翻译：具有自适应跨导的转换率增益误差放大器和主和辅助放大器共享的单个主导极
公开(公告)号：US07795976B2
公开(公告)日：2010-09-14
申请号：US12345862
申请日：2008-12-30
申请人： Yat To William Wong , Chik Wai David Ng , Ho Ming Karen Wan , Kam Chuen Wan , Kwok Kuen David Kwong
发明人： Yat To William Wong , Chik Wai David Ng , Ho Ming Karen Wan , Kam Chuen Wan , Kwok Kuen David Kwong
IPC分类号： H03F3/45
CPC分类号： H03F3/45197 , H03F3/3023 , H03F3/45475 , H03F2203/45248 , H03F2203/45646 , H03F2203/45652 , H03F2203/45678
摘要： An error amplifier can be used to control a power regulator transistor. The error amplifier has a main amplifier, a pull-up auxiliary amplifier, and a pull-down auxiliary amplifier that all drive an output. A compensating capacitor on the output sets a single dominant pole for all amplifiers, increasing stability. High slew rates are provided by increased slew current from the auxiliary amplifiers that turn on when the differential input has an absolute voltage difference larger than an intentional offset. The intentional offset is introduced into the auxiliary amplifiers by adjusting a p-channel to n-channel transistor ratio in a leg of the auxiliary amplifiers. A source degenerated resistor in the main amplifier reduces supply headroom and increases linearity by connecting sources of two differential transistors that receive the differential input. Cascode transistors increase gain and output impedance. Reliability is increased as no positive feedback is used in the amplifiers.
摘要翻译：误差放大器可用于控制功率调节晶体管。误差放大器具有主放大器，上拉辅助放大器和全部驱动输出的下拉辅助放大器。输出上的补偿电容为所有放大器设置单个主极，从而提高稳定性。当差分输入具有大于有意偏移的绝对电压差时，来自辅助放大器的增加的转换电流提供高转换速率。通过调整辅助放大器的一个支路中的p沟道至n沟道晶体管比，将有意的偏移引入辅助放大器。主放大器中的源极退化电阻通过连接接收差分输入的两个差分晶体管的源极减小了供电余量并增加了线性度。串联晶体管增加了增益和输出阻抗。在放大器中没有使用正反馈的情况下，可靠性提高。

9. 发明授权

US07764215B2 Multi-stage comparator with offset canceling capacitor across secondary differential inputs for high-speed low-gain compare and high-gain auto-zeroing 有权
标题翻译：用于高速低增益比较和高增益自动归零的多级比较器，具有二次差分输入的偏移消除电容
公开(公告)号：US07764215B2
公开(公告)日：2010-07-27
申请号：US12347113
申请日：2008-12-31
申请人： Ho Ming Karen Wan , Yat To William Wong , Kwai Chi Chan , Kwok Kuen David Kwong
发明人： Ho Ming Karen Wan , Yat To William Wong , Kwai Chi Chan , Kwok Kuen David Kwong
IPC分类号： H03M1/34
CPC分类号： H03F3/005 , H03F3/45183 , H03F2200/375 , H03F2200/555 , H03F2203/45536 , H03F2203/45544 , H03F2203/45586 , H03F2203/45616 , H03F2203/45631 , H03F2203/45678 , H03F2203/45702 , H03F2203/45726 , H03F2203/45732 , H03M1/0607 , H03M1/0682 , H03M1/46
摘要： An Analog-to-Digital Converter (ADC) has a Successive-Approximation-Register (SAR) driving a digital-to-analog converter (DAC) that generates an analog voltage compared to an input voltage by a series of stages. The last stage feeds a compare signal to the SAR. Each stage has a dual-input differential amplifier that operates as a unity gain op amp during an auto-zeroing phase and as a high-speed low-gain amplifier during an amplifying phase. The dual-input differential amplifier has two pairs of differential inputs. A secondary pair has an offset-storing capacitor across it, and connects to the output pair through feedback switches during auto-zeroing. A primary pair connects to stage inputs through input switches during the amplifying phase. Since two pairs of differential inputs are provided to the dual-input differential amplifier, the offset capacitor is completely isolated from the input pair. The current sink in the dual-input differential amplifier is adjusted higher during the amplifying period.
摘要翻译：模数转换器（ADC）具有驱动数模转换器（DAC）的逐次逼近寄存器（SAR），其通过一系列级与输入电压相比产生模拟电压。最后一个阶段向SAR提供比较信号。每个阶段都有一个双输入差分放大器，在自动归零阶段作为单位增益运算放大器工作，在放大阶段则作为高速低增益放大器工作。双输入差分放大器有两对差分输入。辅助对在其之间具有一个补偿存储电容器，并在自动归零期间通过反馈开关连接到输出对。在放大阶段，初级对通过输入开关连接到级输入。由于两对差分输入提供给双输入差分放大器，所以偏移电容与输入对完全隔离。在放大期间，双输入差分放大器中的电流吸收器被调高。

10. 发明申请

US20100164761A1 DUAL-USE COMPARATOR/OP AMP FOR USE AS BOTH A SUCCESSIVE-APPROXIMATION ADC AND DAC 有权
标题翻译：双使用比较器/运算放大器，用作两个ADC，DAC和DAC
公开(公告)号：US20100164761A1
公开(公告)日：2010-07-01
申请号：US12345844
申请日：2008-12-30
申请人： Ho Ming Karen Wan , Yat To William Wong , Kwai Chi Chan , Hok Mo Yau , Tin Ho Andy Wu , Kwok Kuen David Kwong
发明人： Ho Ming Karen Wan , Yat To William Wong , Kwai Chi Chan , Hok Mo Yau , Tin Ho Andy Wu , Kwok Kuen David Kwong
IPC分类号： H03M1/02 , H03M1/12 , H03M3/02
CPC分类号： H03M1/02 , H03M1/468 , H03M1/804
摘要： A re-configurable circuit acts as an Analog-to-Digital Converter (ADC) and as a digital-to-analog converter (DAC). An array of binary-weighted capacitors stores an analog input. Switches connect different capacitors in the array to fixed voltages that cause charge-sharing with a terminal capacitor. The voltage of the terminal capacitor is compared by a re-configurable comparator stage for each different combination of the capacitors. The comparison results are analyzed to determine the closest digital value for the analog input. In DAC mode, the array capacitors are switched based on an input digital value. The switched capacitors connect to a charge-sharing line to generate an analog voltage that is applied to the re-configurable comparator stage. A differential amplifier generates a buffered analog voltage that is fed back to the other input of the re-configurable comparator stage for unity gain. The gain of the re-configurable comparator stage adjusts for ADC and DAC modes.
摘要翻译：一个可重新配置的电路充当模数转换器（ADC）和数模转换器（DAC）。一组二进制加权电容器存储模拟输入。开关将阵列中的不同电容连接到固定电压，从而与端子电容器进行电荷共享。对于电容器的每个不同组合，端子电容器的电压通过可重新配置的比较器级进行比较。分析比较结果以确定模拟输入的最接近的数字值。在DAC模式下，基于输入数字值切换阵列电容器。开关电容器连接到电荷共享线路以产生施加到可重新配置的比较器级的模拟电压。差分放大器产生缓冲的模拟电压，反馈到可重新配置的比较器级的另一个输入以获得单位增益。可重新配置的比较器级的增益适用于ADC和DAC模式。

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