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1. 发明授权

US09130628B1 Digital pre-distorter 有权
标题翻译：数字预失真
公开(公告)号：US09130628B1
公开(公告)日：2015-09-08
申请号：US14582212
申请日：2014-12-24
申请人： Akshat Mittal , Arvind Kaushik , Peter Z. Rashev , Amrit P. Singh
发明人： Akshat Mittal , Arvind Kaushik , Peter Z. Rashev , Amrit P. Singh
IPC分类号： H04B1/62 , H04B1/04 , H04L27/36 , H03F1/32
CPC分类号： H04B1/0475 , H03F1/3241 , H03F1/3247 , H03F3/24 , H03F3/68 , H03F2201/3233 , H04B2001/0425 , H04L27/368
摘要： A digital pre-distorter (DPD) for an RF transceiver system having multiple antennas includes a DPD controller, first and second address generators, stream select and antenna select muxes, first and second lookup tables (LUTs), first and second dynamic routing logic units, multipliers, an adder, and an accumulator. The DPD controller generates antenna select, stream select and stream routing signals indicative of selection of antennas, the first and second LUTs, and input signals. The DPD controller configures the DPD to share the multipliers and the first and second LUTs between multiple antennas by providing the antenna select signal to the antenna select mux, the stream select signal to the stream select mux, and the stream routing signals to the first and second dynamic routing logic units.
摘要翻译：用于具有多个天线的RF收发器系统的数字预失真器（DPD）包括DPD控制器，第一和第二地址发生器，流选择和天线选择多路复用器，第一和第二查找表（LUT），第一和第二动态路由逻辑单元，乘法器，加法器和累加器。 DPD控制器产生指示天线选择，第一和第二LUT以及输入信号的天线选择，流选择和流选路信号。 DPD控制器通过向天线选择多路复用器提供天线选择信号，将流选择信号提供给流选择多路复用器，并将流路由信号配置为在多个天线之间共享乘法器和第一和第二LUT，第二动态路由逻辑单元。

2. 发明授权

US08432960B2 Digital adaptive channel equalizer 有权
标题翻译：数字自适应通道均衡器
公开(公告)号：US08432960B2
公开(公告)日：2013-04-30
申请号：US12727189
申请日：2010-03-18
申请人： Girraj K. Agrawal , Asif Iqbal , Akshat Mittal , Ankit Pal , Amrit P. Singh
发明人： Girraj K. Agrawal , Asif Iqbal , Akshat Mittal , Ankit Pal , Amrit P. Singh
IPC分类号： H03H7/30
CPC分类号： H04L25/03019 , H04L25/03885
摘要： A channel equalizer that compensates for signal distortion of a signal in a communication channel includes an equalization filter, which gain-equalizes a received signal received through the communication channel, and an equalization control circuit, which generates a gain control signal for controlling the gain of the equalization filter. The equalization control circuit specifies a phase switch in data obtained by the equalization filter as an isolated bit and generates the gain control signal based on a width of the isolated bit.
摘要翻译：补偿通信信道中的信号的信号失真的信道均衡器包括均衡滤波器，其对通过通信信道接收的接收信号进行增益均衡，以及均衡控制电路，其产生用于控制增益的增益控制信号均衡滤波器。均衡控制电路指定由均衡滤波器获得的数据中的相位切换作为隔离位，并且基于隔离位的宽度生成增益控制信号。

3. 发明授权

US09665510B2 Synchronous bus architecture for digital pre-distortion system 有权
公开(公告)号：US09665510B2
公开(公告)日：2017-05-30
申请号：US14580158
申请日：2014-12-22
申请人： Arvind Kaushik , Peter Z. Rashev , Amrit P. Singh , Akshat Mittal
发明人： Arvind Kaushik , Peter Z. Rashev , Amrit P. Singh , Akshat Mittal
IPC分类号： G06F13/24 , G06F13/28 , H03F1/32 , H04B1/04
CPC分类号： G06F13/24 , G06F13/28 , H03F1/3247 , Y02D10/14
摘要： A system for storing pre-distorted output samples in a memory includes a sample counter, a programming interface module, and a comparator. The sample counter counts the pre-distorted output samples, generates a dynamic count value, receives a capture counter status signal, and generates a first count value. The programming interface module receives and outputs the first count value, an offset value, and a capture control signal, and generates a first interrupt signal. The comparator receives the first count value, the offset value, the dynamic count value, and the capture control signal, generates a final value, compares the final value with the dynamic count value, and generates a trigger signal when the final value equals the dynamic count value based on the capture control signal. The trigger signal initiates the storing of the pre-distorted output samples in the memory.

4. 发明申请

US20110228839A1 DIGITAL ADAPTIVE CHANNEL EQUALIZER 有权
标题翻译：数字自适应通道均衡器
公开(公告)号：US20110228839A1
公开(公告)日：2011-09-22
申请号：US12727189
申请日：2010-03-18
申请人： Girraj K. Agrawal , Asif Iqbal , Akshat Mittal , Ankit Pal , Amrit P. Singh
发明人： Girraj K. Agrawal , Asif Iqbal , Akshat Mittal , Ankit Pal , Amrit P. Singh
IPC分类号： H04L27/01
CPC分类号： H04L25/03019 , H04L25/03885
摘要： A channel equalizer that compensates for signal distortion of a signal in a communication channel includes an equalization filter, which gain-equalizes a received signal received through the communication channel, and an equalization control circuit, which generates a gain control signal for controlling the gain of the equalization filter. The equalization control circuit specifies a phase switch in data obtained by the equalization filter as an isolated bit and generates the gain control signal based on a width of the isolated bit.
摘要翻译：补偿通信信道中的信号的信号失真的信道均衡器包括均衡滤波器，其对通过通信信道接收的接收信号进行增益均衡，以及均衡控制电路，其产生用于控制增益的增益控制信号均衡滤波器。均衡控制电路指定由均衡滤波器获得的数据中的相位切换作为隔离位，并且基于隔离位的宽度生成增益控制信号。

5. 发明申请

US20160182015A1 FRACTIONAL AND INTEGER RATIO POLYPHASE INTERPOLATION FILTER 审中-公开
标题翻译：分数和整数比多相插值滤波器
公开(公告)号：US20160182015A1
公开(公告)日：2016-06-23
申请号：US14576149
申请日：2014-12-18
申请人： Vinay Gupta , Arvind Kaushik , Akshat Mittal , Amrit P. Singh
发明人： Vinay Gupta , Arvind Kaushik , Akshat Mittal , Amrit P. Singh
IPC分类号： H03H17/02
CPC分类号： H03H17/0685 , H03H17/0275
摘要： A fractional and integer ratio polyphase interpolation filter changes the sample rate of an input digital signal by a ratio defined by an interpolation rate, M, and a decimation rate, N. The clock rate required to evaluate the output signal is M/N.
摘要翻译：分数和整数比多相插值滤波器通过由内插速率M和抽取率N定义的比例来改变输入数字信号的采样率。评估输出信号所需的时钟速率为M / N。

6. 发明申请

US20160179715A1 SYNCHRONOUS BUS ARCHITECTURE FOR DIGITAL PRE-DISTORTION SYSTEM 有权
标题翻译：数字预失真系统同步总线架构
公开(公告)号：US20160179715A1
公开(公告)日：2016-06-23
申请号：US14580158
申请日：2014-12-22
申请人： Arvind Kaushik , Peter Z. Rashev , Amrit P. Singh , Akshat Mittal
发明人： Arvind Kaushik , Peter Z. Rashev , Amrit P. Singh , Akshat Mittal
IPC分类号： G06F13/24 , G06F13/28
CPC分类号： G06F13/24 , G06F13/28 , H03F1/3247 , Y02D10/14
摘要： A system for storing pre-distorted output samples in a memory includes a sample counter, a programming interface module, and a comparator. The sample counter counts the pre-distorted output samples, generates a dynamic count value, receives a capture counter status signal, and generates a first count value. The programming interface module receives and outputs the first count value, an offset value, and a capture control signal, and generates a first interrupt signal. The comparator receives the first count value, the offset value, the dynamic count value, and the capture control signal, generates a final value, compares the final value with the dynamic count value, and generates a trigger signal when the final value equals the dynamic count value based on the capture control signal. The trigger signal initiates the storing of the pre-distorted output samples in the memory.
摘要翻译：用于将预失真输出样本存储在存储器中的系统包括采样计数器，编程接口模块和比较器。样本计数器对预失真的输出样本进行计数，生成动态计数值，接收捕获计数器状态信号，并生成第一个计数值。编程接口模块接收并输出第一计数值，偏移值和捕获控制信号，并产生第一中断信号。比较器接收第一计数值，偏移值，动态计数值和捕获控制信号，生成最终值，将最终值与动态计数值进行比较，并在最终值等于动态计数值时产生触发信号基于捕获控制信号的计数值。触发信号启动将预失真输出样本存储在存储器中。

7. 发明授权

US09231530B1 System for calibrating power amplifier 有权
标题翻译：功率放大器校准系统
公开(公告)号：US09231530B1
公开(公告)日：2016-01-05
申请号：US14591928
申请日：2015-01-08
申请人： Arvind Kaushik , Peter Z. Rashev , Amrit P. Singh , Akshat Mittal
发明人： Arvind Kaushik , Peter Z. Rashev , Amrit P. Singh , Akshat Mittal
IPC分类号： H04K1/02 , H04L25/03 , H04L25/49 , H03F1/32 , H04B1/04
CPC分类号： H04B1/0475 , H03F1/3241 , H03F1/3247 , H03F3/24 , H03F2200/321 , H04B17/13 , H04B2001/0425 , H04W52/362
摘要： A system for calibrating a power amplifier (PA) includes a memory, a processor, a digital pre-distorter (DPD), and a data converter. The DPD includes a programming interface module, a pattern generator, a multiplier, and a pre-distorter module. The multiplier multiplies reference baseband stream data from the memory with pattern coefficient data generated by the pattern generator to generate shaped reference baseband stream data. The pre-distorter module generates pre-distorted shaped reference baseband stream data. The PA receives a low-power reference radio frequency (RF) signal corresponding to the pre-distorted shaped reference baseband stream data and generates a high-power reference RF signal. The processor receives and compares the pre-distorted shaped reference baseband stream data with amplified shaped reference baseband stream data corresponding to the high-power reference RF signal, and adjusts pre-distortion parameters in the pre-distorter module based on the comparison such that the PA generates a linear high-power RF signal.
摘要翻译：用于校准功率放大器（PA）的系统包括存储器，处理器，数字预失真器（DPD）和数据转换器。 DPD包括编程接口模块，模式发生器，乘法器和预失真器模块。乘法器将来自存储器的参考基带流数据与由模式发生器产生的模式系数数据相乘以产生形状参考基带流数据。预失真器模块生成预失真的参考基带流数据。 PA接收与预失真的参考基带流数据相对应的低功率参考射频（RF）信号，并产生高功率参考RF信号。处理器接收并比较预失真的参考基带流数据与对应于大功率参考RF信号的放大的成形参考基带流数据，并且基于比较调整预失真器模块中的预失真参数，使得 PA产生线性高功率RF信号。

8. 发明授权

US08176227B2 Method and system for high-speed detection handshake in universal serial bus based data communication system 有权
标题翻译：基于通用串行总线数据通信系统的高速检测握手方法与系统
公开(公告)号：US08176227B2
公开(公告)日：2012-05-08
申请号：US12628222
申请日：2009-12-01
申请人： Mayank Devam , Vinay Gupta , Akshat Mittal , Parul K Sharma
发明人： Mayank Devam , Vinay Gupta , Akshat Mittal , Parul K Sharma
IPC分类号： G06F13/42
CPC分类号： G06F13/426
摘要： A USB system includes a USB hub, a USB device, and a USB bus interconnecting the USB hub and the USB device. The USB hub asserts a reset signaling on the USB bus to initiate a high-speed detection handshake. The USB hub and the USB device activate corresponding dual-mode squelch detectors in a first (handshake) mode of operation. The USB device transmits a device chirp signal to the USB hub. The USB hub responds with a sequence of hub chirp signals. The USB device detects the hub chirp signals and then the USB hub and the USB device establish a communication link in a high-speed mode of communication in accordance with USB 2.0. The dual-mode squelch detectors in the USB hub and the USB device can also be activated in a second (normal) mode of operation.
摘要翻译： USB系统包括USB集线器，USB设备和互连USB集线器和USB设备的USB总线。 USB集线器在USB总线上断言复位信号，以启动高速检测握手。 USB集线器和USB设备在第一（握手）操作模式下激活相应的双模静噪检测器。 USB设备将设备啁啾信号发送到USB集线器。 USB集线器通过一系列集线器啁啾信号进行响应。 USB设备检测到集线器啁啾信号，然后USB集线器和USB设备根据USB 2.0在高速通信模式下建立通信链路。 USB集线器和USB设备中的双模式静噪探测器也可以在第二（正常）操作模式下激活。

9. 发明申请

US20110131356A1 METHOD AND SYSTEM FOR HIGH-SPEED DETECTION HANDSHAKE IN UNIVERSAL SERIAL BUS BASED DATA COMMUNICATION SYSTEM 有权
标题翻译：通用串行总线数据通信系统中高速检测手段的方法与系统
公开(公告)号：US20110131356A1
公开(公告)日：2011-06-02
申请号：US12628222
申请日：2009-12-01
申请人： Mayank DEVAM , Vinay Gupta , Akshat Mittal , Parul K. Sharma
发明人： Mayank DEVAM , Vinay Gupta , Akshat Mittal , Parul K. Sharma
IPC分类号： G06F13/42
CPC分类号： G06F13/426
摘要： A USB system includes a USB hub, a USB device, and a USB bus interconnecting the USB hub and the USB device. The USB hub asserts a reset signaling on the USB bus to initiate a high-speed detection handshake. The USB hub and the USB device activate corresponding dual-mode squelch detectors in a first (handshake) mode of operation. The USB device transmits a device chirp signal to the USB hub. The USB hub responds with a sequence of hub chirp signals. The USB device detects the hub chirp signals and then the USB hub and the USB device establish a communication link in a high-speed mode of communication in accordance with USB 2.0. The dual-mode squelch detectors in the USB hub and the USB device can also be activated in a second (normal) mode of operation.
摘要翻译： USB系统包括USB集线器，USB设备和互连USB集线器和USB设备的USB总线。 USB集线器在USB总线上断言复位信号，以启动高速检测握手。 USB集线器和USB设备在第一（握手）操作模式下激活相应的双模静噪检测器。 USB设备将设备啁啾信号发送到USB集线器。 USB集线器通过一系列集线器啁啾信号进行响应。 USB设备检测到集线器啁啾信号，然后USB集线器和USB设备根据USB 2.0在高速通信模式下建立通信链路。 USB集线器和USB设备中的双模式静噪探测器也可以在第二（正常）操作模式下激活。

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