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    • 2. 发明授权
    • Digital pre-distorter
    • 数字预失真
    • US09130628B1
    • 2015-09-08
    • US14582212
    • 2014-12-24
    • Akshat MittalArvind KaushikPeter Z. RashevAmrit P. Singh
    • Akshat MittalArvind KaushikPeter Z. RashevAmrit P. Singh
    • H04B1/62H04B1/04H04L27/36H03F1/32
    • H04B1/0475H03F1/3241H03F1/3247H03F3/24H03F3/68H03F2201/3233H04B2001/0425H04L27/368
    • A digital pre-distorter (DPD) for an RF transceiver system having multiple antennas includes a DPD controller, first and second address generators, stream select and antenna select muxes, first and second lookup tables (LUTs), first and second dynamic routing logic units, multipliers, an adder, and an accumulator. The DPD controller generates antenna select, stream select and stream routing signals indicative of selection of antennas, the first and second LUTs, and input signals. The DPD controller configures the DPD to share the multipliers and the first and second LUTs between multiple antennas by providing the antenna select signal to the antenna select mux, the stream select signal to the stream select mux, and the stream routing signals to the first and second dynamic routing logic units.
    • 用于具有多个天线的RF收发器系统的数字预失真器(DPD)包括DPD控制器,第一和第二地址发生器,流选择和天线选择多路复用器,第一和第二查找表(LUT),第一和第二动态路由逻辑单元 ,乘法器,加法器和累加器。 DPD控制器产生指示天线选择,第一和第二LUT以及输入信号的天线选择,流选择和流选路信号。 DPD控制器通过向天线选择多路复用器提供天线选择信号,将流选择信号提供给流选择多路复用器,并将流路由信号配置为在多个天线之间共享乘法器和第一和第二LUT, 第二动态路由逻辑单元。
    • 3. 发明授权
    • System for compensating for I/Q impairments in wireless communication system
    • 用于补偿无线通信系统中I / Q损伤的系统
    • US09088472B1
    • 2015-07-21
    • US14591930
    • 2015-01-08
    • Nikhil JainArvind KaushikPeter Z. RashevAmrit P. Singh
    • Nikhil JainArvind KaushikPeter Z. RashevAmrit P. Singh
    • H04L25/49H04L27/36H03F1/32
    • H04L27/364H03F1/3247H03F3/24H04L27/368H04L27/3863
    • A system for reducing in-phase and quadrature-phase (I/Q) impairments includes first, second, third, and fourth programmable registers for storing respective first, second, third, and fourth values, first and second finite impulse response (FIR) filters having respective first and second sets of filter taps, and first and second adders. The first FIR filter receives an I input signal and generates first and second intermediate output signals based on the first and second values for I and Q channels, respectively. The second FIR filter receives a Q input signal and generates third and fourth intermediate output signals based on the third and fourth values for the I and Q channels, respectively. The first and second adders receive the first and second, and the third and fourth intermediate output signals, respectively, and generate compensated I and Q output signals for the I and Q channels.
    • 用于减小同相和正交相位(I / Q)损伤的系统包括用于存储相应的第一,第二,第三和第四值的第一,第二,第三和第四可编程寄存器,第一和第二有限脉冲响应(FIR) 滤波器具有相应的第一和第二组滤波器抽头,以及第一和第二加法器。 第一FIR滤波器接收I输入信号,并且基于I和Q通道的第一和第二值分别产生第一和第二中间输出信号。 第二FIR滤波器接收Q输入信号,并且分别基于I和Q通道的第三和第四值产生第三和第四中间输出信号。 第一和第二加法器分别接收第一和第二以及第三和第四中间输出信号,并产生用于I和Q通道的补偿的I和Q输出信号。
    • 9. 发明申请
    • SYNCHRONOUS BUS ARCHITECTURE FOR DIGITAL PRE-DISTORTION SYSTEM
    • 数字预失真系统同步总线架构
    • US20160179715A1
    • 2016-06-23
    • US14580158
    • 2014-12-22
    • Arvind KaushikPeter Z. RashevAmrit P. SinghAkshat Mittal
    • Arvind KaushikPeter Z. RashevAmrit P. SinghAkshat Mittal
    • G06F13/24G06F13/28
    • G06F13/24G06F13/28H03F1/3247Y02D10/14
    • A system for storing pre-distorted output samples in a memory includes a sample counter, a programming interface module, and a comparator. The sample counter counts the pre-distorted output samples, generates a dynamic count value, receives a capture counter status signal, and generates a first count value. The programming interface module receives and outputs the first count value, an offset value, and a capture control signal, and generates a first interrupt signal. The comparator receives the first count value, the offset value, the dynamic count value, and the capture control signal, generates a final value, compares the final value with the dynamic count value, and generates a trigger signal when the final value equals the dynamic count value based on the capture control signal. The trigger signal initiates the storing of the pre-distorted output samples in the memory.
    • 用于将预失真输出样本存储在存储器中的系统包括采样计数器,编程接口模块和比较器。 样本计数器对预失真的输出样本进行计数,生成动态计数值,接收捕获计数器状态信号,并生成第一个计数值。 编程接口模块接收并输出第一计数值,偏移值和捕获控制信号,并产生第一中断信号。 比较器接收第一计数值,偏移值,动态计数值和捕获控制信号,生成最终值,将最终值与动态计数值进行比较,并在最终值等于动态计数值时产生触发信号 基于捕获控制信号的计数值。 触发信号启动将预失真输出样本存储在存储器中。
    • 10. 发明授权
    • System for calibrating power amplifier
    • 功率放大器校准系统
    • US09231530B1
    • 2016-01-05
    • US14591928
    • 2015-01-08
    • Arvind KaushikPeter Z. RashevAmrit P. SinghAkshat Mittal
    • Arvind KaushikPeter Z. RashevAmrit P. SinghAkshat Mittal
    • H04K1/02H04L25/03H04L25/49H03F1/32H04B1/04
    • H04B1/0475H03F1/3241H03F1/3247H03F3/24H03F2200/321H04B17/13H04B2001/0425H04W52/362
    • A system for calibrating a power amplifier (PA) includes a memory, a processor, a digital pre-distorter (DPD), and a data converter. The DPD includes a programming interface module, a pattern generator, a multiplier, and a pre-distorter module. The multiplier multiplies reference baseband stream data from the memory with pattern coefficient data generated by the pattern generator to generate shaped reference baseband stream data. The pre-distorter module generates pre-distorted shaped reference baseband stream data. The PA receives a low-power reference radio frequency (RF) signal corresponding to the pre-distorted shaped reference baseband stream data and generates a high-power reference RF signal. The processor receives and compares the pre-distorted shaped reference baseband stream data with amplified shaped reference baseband stream data corresponding to the high-power reference RF signal, and adjusts pre-distortion parameters in the pre-distorter module based on the comparison such that the PA generates a linear high-power RF signal.
    • 用于校准功率放大器(PA)的系统包括存储器,处理器,数字预失真器(DPD)和数据转换器。 DPD包括编程接口模块,模式发生器,乘法器和预失真器模块。 乘法器将来自存储器的参考基带流数据与由模式发生器产生的模式系数数据相乘以产生形状参考基带流数据。 预失真器模块生成预失真的参考基带流数据。 PA接收与预失真的参考基带流数据相对应的低功率参考射频(RF)信号,并产生高功率参考RF信号。 处理器接收并比较预失真的参考基带流数据与对应于大功率参考RF信号的放大的成形参考基带流数据,并且基于比较调整预失真器模块中的预失真参数,使得 PA产生线性高功率RF信号。