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1. 发明授权

US07962909B1 Limiting guest execution 有权
标题翻译：限制客人执行
公开(公告)号：US07962909B1
公开(公告)日：2011-06-14
申请号：US11066027
申请日：2005-02-25
申请人： Alexander C. Klaiber
发明人： Alexander C. Klaiber
IPC分类号： G06F9/455 , G06F9/46
CPC分类号： G06F9/45533
摘要： In one embodiment, a processor comprises an execution core configured to execute instructions including instructions comprising a guest and a circuit coupled to the execution core. The circuit is configured to monitor the execution core, and is programmable to limit an execution of the guest in the execution core to an execution interval. In another embodiment, a method comprises establishing an execution interval for a guest to be executed in a processor; and initiating execution of the guest in the processor. The processor includes a circuit configured to monitor execution of the guest to detect an end of the execution interval. A computer accessible medium storing instructions which, when executed, implement the method is also contemplated.
摘要翻译：在一个实施例中，处理器包括被配置为执行包括指令的指令的执行核心，所述指令包括访客和耦合到执行核心的电路。电路被配置为监视执行核心，并且可编程以将执行核心中的客户机的执行限制到执行间隔。在另一个实施例中，一种方法包括为处理器中要执行的客人建立执行间隔; 并且在处理器中启动客人的执行。处理器包括被配置为监视访客的执行以检测执行间隔的结束的电路。一种存储指令的计算机可访问介质，其在被执行时也实现该方法。

2. 发明授权

US07917740B1 Virtualization assist for legacy x86 floating point exception handling 有权
标题翻译：虚拟化辅助传统的x86浮点异常处理
公开(公告)号：US07917740B1
公开(公告)日：2011-03-29
申请号：US11066920
申请日：2005-02-25
申请人： Alexander C. Klaiber , Michael S. Greske
发明人： Alexander C. Klaiber , Michael S. Greske
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/45533
摘要： In one embodiment, a processor comprises an execution core configured to detect a freeze event responsive to an error indication, an ignore error indication, and an instruction in a guest. The instruction belongs to a predefined subset of instructions associated with the error indication and the ignore error indication. The execution core is configured to exit the guest in response to detecting the freeze event. In some embodiments, the error indication and the ignore indication may be stored in one or more registers in the processor. In some embodiments, the instruction is a floating point instruction, the error indication is a floating pointer error indication, and the ignore error indication is an ignore floating point error indication. In some embodiments, the error indication may correspond to an error signal output by the processor, and the ignore error indication may correspond to an ignore error signal input to the processor.
摘要翻译：在一个实施例中，处理器包括配置成响应于错误指示，忽略错误指示和客户机中的指令来检测冻结事件的执行核心。该指令属于与错误指示和忽略错误指示相关联的指令的预定义子集。响应于检测到冻结事件，执行核心被配置为退出客户机。在一些实施例中，错误指示和忽略指示可以存储在处理器中的一个或多个寄存器中。在一些实施例中，指令是浮点指令，错误指示是浮动指针错误指示，忽略错误指示是忽略浮点错误指示。在一些实施例中，误差指示可对应于由处理器输出的误差信号，并且忽略错误指示可对应于输入到处理器的忽略误差信号。

3. 发明申请

US20100122013A1 DATA STRUCTURE FOR ENFORCING CONSISTENT PER-PHYSICAL PAGE CACHEABILITY ATTRIBUTES 有权
标题翻译：用于执行一致性的物理页面可访问性属性的数据结构
公开(公告)号：US20100122013A1
公开(公告)日：2010-05-13
申请号：US12688722
申请日：2010-01-15
申请人： Alexander C. Klaiber , David Dunn
发明人： Alexander C. Klaiber , David Dunn
IPC分类号： G06F12/08 , G06F12/00 , G06F12/10
CPC分类号： G06F12/1027 , G06F12/0837
摘要： A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.
摘要翻译：公开了一种用于实现一致的每个物理页面缓存性能的数据结构。该数据结构与用于实施一致的每个物理页面高速缓存属性的方法一起使用，该属性维持处理器寻址存储器内部的内存一致性，例如通过将PTE中的物理页面地址的期望可缓存性属性与指示当前的缓存状态。可以在将PTE插入TLB时进行此比较。当比较检测到页面的期望的可缓存性属性和页面的当前可缓存状态之间的不匹配时，可以采取校正动作来将页面转换到期望的可缓存状态。

4. 发明授权

US07620779B1 System and method for handling direct memory accesses 有权
标题翻译：用于处理直接内存访问的系统和方法
公开(公告)号：US07620779B1
公开(公告)日：2009-11-17
申请号：US11439361
申请日：2006-05-22
申请人： Alexander C. Klaiber , Guillermo J. Rozas , David A. Dunn
发明人： Alexander C. Klaiber , Guillermo J. Rozas , David A. Dunn
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop cache determines if the target address is within an address range known to be safe for external access. If the snoop cache determines that the target address is safe, it signals the external agent to proceed with the direct memory access. If the snoop cache does not determine if the target address is safe, then the snoop cache forwards the request on to the processor. After the processor resolves any coherency problems between itself and the memory system, the processor signals the external agent to proceed with the direct memory access. The snoop cache can determine safe address ranges from such processor activity. The snoop cache invalidates its safe address ranges by observing traffic between the processor and the memory system.
摘要翻译：有效处理直接存储器访问请求的方法和系统。外部代理从目标地址的计算机系统的存储系统请求数据。侦听缓存确定目标地址是否在已知对外部访问安全的地址范围内。如果窥探缓存确定目标地址是安全的，则它会通知外部代理继续直接访问内存。如果侦听缓存不能确定目标地址是否安全，则侦听缓存将请求转发到处理器。在处理器解决其本身与存储器系统之间的任何一致性问题之后，处理器发信号通知外部代理进行直接存储器访问。监听缓存可以确定这种处理器活动的安全地址范围。监听缓存通过观察处理器和存储系统之间的流量来使其安全地址范围无效。

5. 发明授权

US07209994B1 Processor that maintains virtual interrupt state and injects virtual interrupts into virtual machine guests 有权
标题翻译：维护虚拟中断状态并将虚拟中断注入虚拟机guest虚拟机的处理器
公开(公告)号：US07209994B1
公开(公告)日：2007-04-24
申请号：US11066019
申请日：2005-02-25
申请人： Alexander C. Klaiber , Hongwen Gao
发明人： Alexander C. Klaiber , Hongwen Gao
IPC分类号： G06F13/24 , G06F9/45
CPC分类号： G06F13/24 , G06F9/45533
摘要： In one embodiment, a processor comprises one or more registers and a control unit. The registers are configured to store interrupt state describing a virtual interrupt. The control unit is configured to initiate the virtual interrupt responsive to the interrupt state. In another embodiment, a method comprises storing an interrupt state describing a virtual interrupt in a storage area allocated to a guest. A processor initiates the virtual interrupt subsequent to initiating execution of the guest, responsive to the interrupt state. In still another embodiment, a computer accessible medium stores a plurality of instructions comprising instructions which, when executed on a processor in response to a physical interrupt: determine a guest into which a virtual interrupt corresponding to the physical interrupt is to be injected; and store an interrupt state describing the virtual interrupt in a storage area allocated to the guest.
摘要翻译：在一个实施例中，处理器包括一个或多个寄存器和控制单元。寄存器被配置为存储描述虚拟中断的中断状态。控制单元被配置为响应于中断状态来启动虚拟中断。在另一个实施例中，一种方法包括将描述虚拟中断的中断状态存储在分配给访客的存储区域中。响应于中断状态，处理器在发起客户端的执行之后发起虚拟中断。在另一个实施例中，计算机可访问介质存储包括指令的多个指令，所述指令在响应于物理中断在处理器上执行时：确定要对其中注入与物理中断相对应的虚拟中断的客户端; 并将描述虚拟中断的中断状态存储在分配给访客的存储区域中。

6. 发明授权

US08117421B2 Data structure for enforcing consistent per-physical page cacheability attributes 有权
标题翻译：用于强制执行一致的每个物理页面缓存属性的数据结构
公开(公告)号：US08117421B2
公开(公告)日：2012-02-14
申请号：US12688722
申请日：2010-01-15
申请人： Alexander C. Klaiber , David Dunn
发明人： Alexander C. Klaiber , David Dunn
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/1027 , G06F12/0837
摘要： A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.
摘要翻译：公开了一种用于实现一致的每个物理页面缓存性能的数据结构。该数据结构与用于实施一致的每个物理页面高速缓存属性的方法一起使用，该属性维持处理器寻址存储器内部的内存一致性，例如通过将PTE中的物理页面地址的期望可缓存性属性与指示当前的缓存状态。可以在将PTE插入TLB时进行此比较。当比较检测到页面的期望的可缓存性属性和页面的当前可缓存状态之间的不匹配时，可以采取校正动作来将页面转换到期望的可缓存状态。

7. 发明授权

US07418584B1 Executing system management mode code as virtual machine guest 有权
标题翻译：执行系统管理模式代码作为虚拟机guest
公开(公告)号：US07418584B1
公开(公告)日：2008-08-26
申请号：US11066752
申请日：2005-02-25
申请人： Alexander C. Klaiber , Geoffrey S. Strongin , Kevin J. McGrath
发明人： Alexander C. Klaiber , Geoffrey S. Strongin , Kevin J. McGrath
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/45533
摘要： In one embodiment, a register in a processor is programmable with an intercept indication indicative of whether or not an event that would cause a transition by the processor to a first mode is to be intercepted during execution of a guest. Responsive to the intercept indication and further responsive to detecting the event, execution circuitry in the processor is configured to exit the guest. In another embodiment, a method comprises: detecting an event that would cause a processor to transition to a first mode, wherein first code is to be executed in the first mode; and causing the first code to be executed in a guest responsive to the detecting. In still another embodiment, a computer accessible medium comprising instructions which when executed in response to detecting the event, cause the first code to be executed in a guest.
摘要翻译：在一个实施例中，处理器中的寄存器是可编程的，其中拦截指示指示在执行客户期间是否将由处理器转换到第一模式的事件被拦截。响应于拦截指示并进一步响应于检测事件，处理器中的执行电路被配置为退出客人。在另一个实施例中，一种方法包括：检测将导致处理器转换到第一模式的事件，其中第一代码将以第一模式执行; 并且响应于检测使得在客人中执行第一代码。在另一个实施例中，一种包括指令的计算机可访问介质，当被响应于检测到事件而被执行时，导致第一代码在客户机中被执行。

8. 发明申请

US20120131307A1 DATA STRUCTURE FOR ENFORCING CONSISTENT PER-PHYSICAL PAGE CACHEABILITY ATTRIBUTES 有权
标题翻译：用于执行一致性的物理页面可访问性属性的数据结构
公开(公告)号：US20120131307A1
公开(公告)日：2012-05-24
申请号：US13363050
申请日：2012-01-31
申请人： Alexander C. Klaiber , David Dunn
发明人： Alexander C. Klaiber , David Dunn
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/0837
摘要： A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.
摘要翻译：公开了一种用于实现一致的每个物理页面缓存性能的数据结构。该数据结构与用于实施一致的每个物理页面高速缓存属性的方法一起使用，该属性维持处理器寻址存储器内部的内存一致性，例如通过将PTE中的物理页面地址的期望可缓存性属性与指示当前的缓存状态。可以在将PTE插入TLB时进行此比较。当比较检测到页面的期望的可缓存性属性和页面的当前可缓存状态之间的不匹配时，可以采取校正动作来将页面转换到期望的可缓存状态。

9. 发明授权

US07937700B1 System, processor, and method for incremental state save/restore on world switch in a virtual machine environment 有权
标题翻译：用于虚拟机环境中世界交换机上的增量状态保存/恢复的系统，处理器和方法
公开(公告)号：US07937700B1
公开(公告)日：2011-05-03
申请号：US11065777
申请日：2005-02-25
申请人： Alexander C. Klaiber , Michael Shawn Greske , Hongwen Gao
发明人： Alexander C. Klaiber , Michael Shawn Greske , Hongwen Gao
IPC分类号： G06F9/455 , G06F9/46 , G06F13/00 , G06F7/38
CPC分类号： G06F9/45533
摘要： In one embodiment, a processor comprises a plurality of registers configured to store processor state and an execution core coupled to the registers. The execution core is configured, during a switch between processor execution of a guest and processor execution of a virtual machine manager (VMM) that controls the guest, to save only a portion of the processor state to a memory. In another embodiment, a method comprises switching from processor execution of a first one of a guest and a virtual machine manager (VMM) to processor execution of a second one of the guest and the VMM, wherein the VMM controls execution of the guest; and during the switching, the processor saving only a portion of a processor state to memory.
摘要翻译：在一个实施例中，处理器包括被配置为存储处理器状态的多个寄存器和耦合到寄存器的执行核心。在执行访客的处理器执行和控制访客的虚拟机管理器（VMM）的处理器执行之间的切换期间，执行核心被配置为仅将一部分处理器状态保存到存储器。在另一实施例中，一种方法包括从访客和虚拟机管理器（VMM）中的第一个处理器执行切换到客户机和VMM中的第二个处理器执行，其中VMM控制客户机的执行; 并且在切换期间，处理器仅将一部分处理器状态保存到存储器。

10. 发明授权

US07937536B2 Handling direct memory accesses 有权
标题翻译：处理直接内存访问
公开(公告)号：US07937536B2
公开(公告)日：2011-05-03
申请号：US12624094
申请日：2009-11-23
申请人： Alexander C. Klaiber , Guillermo J. Rozas , David Dunn
发明人： Alexander C. Klaiber , Guillermo J. Rozas , David Dunn
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop cache determines if the target address is within an address range known to be safe for external access. If the snoop cache determines that the target address is safe, the external agent proceeds with the direct memory access. If the snoop cache does not determine if the target address is safe, then the snoop cache forwards the request on to the processor. After the processor resolves any coherency problems between itself and the memory system, the processor signals the external agent to proceed with the direct memory access. The snoop cache can determine safe address ranges from such processor activity. The snoop cache invalidates its safe address ranges by observing traffic between the processor and the memory system.
摘要翻译：有效处理直接存储器访问请求的方法和系统。外部代理从目标地址的计算机系统的存储系统请求数据。侦听缓存确定目标地址是否在已知对外部访问安全的地址范围内。如果窥探缓存确定目标地址是安全的，则外部代理继续进行直接内存访问。如果侦听缓存不能确定目标地址是否安全，则侦听缓存将请求转发到处理器。在处理器解决其本身与存储器系统之间的任何一致性问题之后，处理器发信号通知外部代理进行直接存储器访问。监听缓存可以确定这种处理器活动的安全地址范围。监听缓存通过观察处理器和存储系统之间的流量来使其安全地址范围无效。

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