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1. 发明授权

US08117421B2 Data structure for enforcing consistent per-physical page cacheability attributes 有权
标题翻译：用于强制执行一致的每个物理页面缓存属性的数据结构
公开(公告)号：US08117421B2
公开(公告)日：2012-02-14
申请号：US12688722
申请日：2010-01-15
申请人： Alexander C. Klaiber , David Dunn
发明人： Alexander C. Klaiber , David Dunn
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/1027 , G06F12/0837
摘要： A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.
摘要翻译：公开了一种用于实现一致的每个物理页面缓存性能的数据结构。该数据结构与用于实施一致的每个物理页面高速缓存属性的方法一起使用，该属性维持处理器寻址存储器内部的内存一致性，例如通过将PTE中的物理页面地址的期望可缓存性属性与指示当前的缓存状态。可以在将PTE插入TLB时进行此比较。当比较检测到页面的期望的可缓存性属性和页面的当前可缓存状态之间的不匹配时，可以采取校正动作来将页面转换到期望的可缓存状态。

2. 发明申请

US20100138615A1 HANDLING DIRECT MEMORY ACCESSES 有权
标题翻译：处理直接内存访问
公开(公告)号：US20100138615A1
公开(公告)日：2010-06-03
申请号：US12624094
申请日：2009-11-23
申请人： Alexander C. Klaiber , Guillermo J. Rozas , David Dunn
发明人： Alexander C. Klaiber , Guillermo J. Rozas , David Dunn
IPC分类号： G06F12/08 , G06F12/00 , G06F13/28
CPC分类号： G06F12/0831
摘要： Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop cache determines if the target address is within an address range known to be safe for external access. If the snoop cache determines that the target address is safe, the external agent proceeds with the direct memory access. If the snoop cache does not determine if the target address is safe, then the snoop cache forwards the request on to the processor. After the processor resolves any coherency problems between itself and the memory system, the processor signals the external agent to proceed with the direct memory access. The snoop cache can determine safe address ranges from such processor activity. The snoop cache invalidates its safe address ranges by observing traffic between the processor and the memory system.
摘要翻译：有效处理直接存储器访问请求的方法和系统。外部代理从目标地址的计算机系统的存储系统请求数据。侦听缓存确定目标地址是否在已知对外部访问安全的地址范围内。如果窥探缓存确定目标地址是安全的，则外部代理继续进行直接内存访问。如果侦听缓存不能确定目标地址是否安全，则侦听缓存将请求转发到处理器。在处理器解决其本身与存储器系统之间的任何一致性问题之后，处理器发信号通知外部代理进行直接存储器访问。监听缓存可以确定这种处理器活动的安全地址范围。监听缓存通过观察处理器和存储系统之间的流量来使其安全地址范围无效。

3. 发明授权

US08607025B2 Data structure for enforcing consistent per-physical page cacheability attributes 有权
标题翻译：用于强制执行一致的每个物理页面缓存属性的数据结构
公开(公告)号：US08607025B2
公开(公告)日：2013-12-10
申请号：US13363050
申请日：2012-01-31
申请人： Alexander C. Klaiber , David Dunn
发明人： Alexander C. Klaiber , David Dunn
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/1027 , G06F12/0837
摘要： A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.
摘要翻译：公开了一种用于实现一致的每个物理页面缓存性能的数据结构。该数据结构与用于实施一致的每个物理页面高速缓存属性的方法一起使用，该属性维持处理器寻址存储器内部的内存一致性，例如通过将PTE中的物理页面地址的期望可缓存性属性与指示当前的缓存状态。可以在将PTE插入TLB时进行此比较。当比较检测到页面的期望的可缓存性属性和页面的当前可缓存状态之间的不匹配时，可以采取校正动作来将页面转换到期望的可缓存状态。

4. 发明授权

US07676629B1 Data structure for enforcing consistent per-physical page cacheability attributes 有权
标题翻译：用于强制执行一致的每个物理页面缓存属性的数据结构
公开(公告)号：US07676629B1
公开(公告)日：2010-03-09
申请号：US11314494
申请日：2005-12-20
申请人： Alexander C. Klaiber , David Dunn
发明人： Alexander C. Klaiber , David Dunn
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/1027 , G06F12/0837
摘要： A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.
摘要翻译：公开了一种用于实现一致的每个物理页面缓存性能的数据结构。该数据结构与用于实施一致的每个物理页面高速缓存属性的方法一起使用，该属性维持处理器寻址存储器内部的内存一致性，例如通过将PTE中的物理页面地址的期望可缓存性属性与指示当前的缓存状态。可以在将PTE插入TLB时进行此比较。当比较检测到页面的期望的可缓存性属性和页面的当前可缓存状态之间的不匹配时，可以采取校正动作来将页面转换到期望的可缓存状态。

5. 发明申请

US20100122013A1 DATA STRUCTURE FOR ENFORCING CONSISTENT PER-PHYSICAL PAGE CACHEABILITY ATTRIBUTES 有权
标题翻译：用于执行一致性的物理页面可访问性属性的数据结构
公开(公告)号：US20100122013A1
公开(公告)日：2010-05-13
申请号：US12688722
申请日：2010-01-15
申请人： Alexander C. Klaiber , David Dunn
发明人： Alexander C. Klaiber , David Dunn
IPC分类号： G06F12/08 , G06F12/00 , G06F12/10
CPC分类号： G06F12/1027 , G06F12/0837
摘要： A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.
摘要翻译：公开了一种用于实现一致的每个物理页面缓存性能的数据结构。该数据结构与用于实施一致的每个物理页面高速缓存属性的方法一起使用，该属性维持处理器寻址存储器内部的内存一致性，例如通过将PTE中的物理页面地址的期望可缓存性属性与指示当前的缓存状态。可以在将PTE插入TLB时进行此比较。当比较检测到页面的期望的可缓存性属性和页面的当前可缓存状态之间的不匹配时，可以采取校正动作来将页面转换到期望的可缓存状态。

6. 发明申请

US20120131307A1 DATA STRUCTURE FOR ENFORCING CONSISTENT PER-PHYSICAL PAGE CACHEABILITY ATTRIBUTES 有权
标题翻译：用于执行一致性的物理页面可访问性属性的数据结构
公开(公告)号：US20120131307A1
公开(公告)日：2012-05-24
申请号：US13363050
申请日：2012-01-31
申请人： Alexander C. Klaiber , David Dunn
发明人： Alexander C. Klaiber , David Dunn
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/0837
摘要： A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.
摘要翻译：公开了一种用于实现一致的每个物理页面缓存性能的数据结构。该数据结构与用于实施一致的每个物理页面高速缓存属性的方法一起使用，该属性维持处理器寻址存储器内部的内存一致性，例如通过将PTE中的物理页面地址的期望可缓存性属性与指示当前的缓存状态。可以在将PTE插入TLB时进行此比较。当比较检测到页面的期望的可缓存性属性和页面的当前可缓存状态之间的不匹配时，可以采取校正动作来将页面转换到期望的可缓存状态。

7. 发明授权

US07937536B2 Handling direct memory accesses 有权
标题翻译：处理直接内存访问
公开(公告)号：US07937536B2
公开(公告)日：2011-05-03
申请号：US12624094
申请日：2009-11-23
申请人： Alexander C. Klaiber , Guillermo J. Rozas , David Dunn
发明人： Alexander C. Klaiber , Guillermo J. Rozas , David Dunn
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop cache determines if the target address is within an address range known to be safe for external access. If the snoop cache determines that the target address is safe, the external agent proceeds with the direct memory access. If the snoop cache does not determine if the target address is safe, then the snoop cache forwards the request on to the processor. After the processor resolves any coherency problems between itself and the memory system, the processor signals the external agent to proceed with the direct memory access. The snoop cache can determine safe address ranges from such processor activity. The snoop cache invalidates its safe address ranges by observing traffic between the processor and the memory system.
摘要翻译：有效处理直接存储器访问请求的方法和系统。外部代理从目标地址的计算机系统的存储系统请求数据。侦听缓存确定目标地址是否在已知对外部访问安全的地址范围内。如果窥探缓存确定目标地址是安全的，则外部代理继续进行直接内存访问。如果侦听缓存不能确定目标地址是否安全，则侦听缓存将请求转发到处理器。在处理器解决其本身与存储器系统之间的任何一致性问题之后，处理器发信号通知外部代理进行直接存储器访问。监听缓存可以确定这种处理器活动的安全地址范围。监听缓存通过观察处理器和存储系统之间的流量来使其安全地址范围无效。

8. 发明授权

US07636815B1 System and method for handling direct memory accesses 有权
公开(公告)号：US07636815B1
公开(公告)日：2009-12-22
申请号：US10411168
申请日：2003-04-09
申请人： Alexander C. Klaiber , Guillermo J. Rozas , David Dunn
发明人： Alexander C. Klaiber , Guillermo J. Rozas , David Dunn
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop cache determines if the target address is within an address range known to be safe for external access. If the snoop cache determines that the target address is safe, it signals the external agent to proceed with the direct memory access. If the snoop cache does not determine if the target address is safe, then the snoop cache forwards the request on to the processor. After the processor resolves any coherency problems between itself and the memory system, the processor signals the external agent to proceed with the direct memory access. The snoop cache can determine safe address ranges from such processor activity. The snoop cache invalidates its safe address ranges by observing traffic between the processor and the memory system.

9. 发明授权

US07062631B1 Method and system for enforcing consistent per-physical page cacheability attributes 有权
标题翻译：用于实施一致的每个物理页面缓存属性的方法和系统
公开(公告)号：US07062631B1
公开(公告)日：2006-06-13
申请号：US10623021
申请日：2003-07-17
申请人： Alexander C. Klaiber , David Dunn
发明人： Alexander C. Klaiber , David Dunn
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0837
摘要： A method and system for enforcing consistent per-physical page cacheability attributes is disclosed. The method for enforcing consistent per-physical page cacheability attributes maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.
摘要翻译：公开了一种用于实现一致的每个物理页面缓存性能的方法和系统。用于实施一致的每个物理页面高速缓存属性的方法在处理器寻址存储器内维护存储器一致性，例如通过将PTE中的物理页面地址的期望可缓存性属性与指示当前可缓存状态的权威表相比较。可以在将PTE插入TLB时进行此比较。当比较检测到页面的期望的可缓存性属性和页面的当前可缓存状态之间的不匹配时，可以采取校正动作来将页面转换到期望的可缓存状态。

10. 发明授权

US07418584B1 Executing system management mode code as virtual machine guest 有权
标题翻译：执行系统管理模式代码作为虚拟机guest
公开(公告)号：US07418584B1
公开(公告)日：2008-08-26
申请号：US11066752
申请日：2005-02-25
申请人： Alexander C. Klaiber , Geoffrey S. Strongin , Kevin J. McGrath
发明人： Alexander C. Klaiber , Geoffrey S. Strongin , Kevin J. McGrath
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/45533
摘要： In one embodiment, a register in a processor is programmable with an intercept indication indicative of whether or not an event that would cause a transition by the processor to a first mode is to be intercepted during execution of a guest. Responsive to the intercept indication and further responsive to detecting the event, execution circuitry in the processor is configured to exit the guest. In another embodiment, a method comprises: detecting an event that would cause a processor to transition to a first mode, wherein first code is to be executed in the first mode; and causing the first code to be executed in a guest responsive to the detecting. In still another embodiment, a computer accessible medium comprising instructions which when executed in response to detecting the event, cause the first code to be executed in a guest.
摘要翻译：在一个实施例中，处理器中的寄存器是可编程的，其中拦截指示指示在执行客户期间是否将由处理器转换到第一模式的事件被拦截。响应于拦截指示并进一步响应于检测事件，处理器中的执行电路被配置为退出客人。在另一个实施例中，一种方法包括：检测将导致处理器转换到第一模式的事件，其中第一代码将以第一模式执行; 并且响应于检测使得在客人中执行第一代码。在另一个实施例中，一种包括指令的计算机可访问介质，当被响应于检测到事件而被执行时，导致第一代码在客户机中被执行。

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