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1. 发明授权

US08145732B2 Live network configuration within a link based computing system 有权
标题翻译：基于链路的计算系统中的实时网络配置
公开(公告)号：US08145732B2
公开(公告)日：2012-03-27
申请号：US11284537
申请日：2005-11-21
申请人： Mohan J. Kumar , Murugasamy Nachimuthu , Allen Baum
发明人： Mohan J. Kumar , Murugasamy Nachimuthu , Allen Baum
IPC分类号： G06F15/177 , G06F15/173 , G06F15/16 , G06F11/00 , G06F9/44 , G06F9/445 , H04L12/28 , H04B1/38 , G06Q10/00 , G06Q30/00
CPC分类号： H04L41/082
摘要： A method is described in which, in response to notice of a configuration event yet to happen within a network that is part of a link-based computing system, a component within said link based computing system: a) identifies networking configuration information changes to be made by components within the link-based computing system; and, b) sends instances of program code to each one of the components. Each instance of program code is to be executed by a specific component that it was sent to. Each instance of program code is customized to implement the particular one or more networking configuration information changes to be made at the specific component it was sent to.
摘要翻译：描述了一种方法，其中响应于在作为基于链路的计算系统的一部分的网络内尚未发生的配置事件的通知，所述基于链路的计算系统中的组件：a）将网络配置信息变化标识为由基于链路的计算系统中的组件构成; 和b）将程序代码的实例发送到每个组件。程序代码的每个实例都要由发送到的特定组件来执行。程序代码的每个实例被定制以实现要在其发送到的特定组件上进行的特定一个或多个网络配置信息更改。

2. 发明授权

US07273156B2 Adjustable sheet dispenser 失效
标题翻译：可调片材分送机
公开(公告)号：US07273156B2
公开(公告)日：2007-09-25
申请号：US10860357
申请日：2004-06-02
申请人： Hongxia Gao , Gary Douglas Williams , Patricia Ann Samolinski , Scott Allen Baum , Sara Marie Vermillion , Daphne Lynn VanBuren , Tammy Jo Balzar , Cynthia Watts Henderson
发明人： Hongxia Gao , Gary Douglas Williams , Patricia Ann Samolinski , Scott Allen Baum , Sara Marie Vermillion , Daphne Lynn VanBuren , Tammy Jo Balzar , Cynthia Watts Henderson
IPC分类号： B65H1/00
CPC分类号： B65D83/0805
摘要： A dispenser for sheet materials includes a top portion, a bottom portion, and a restraining member preventing the top and bottom portion from separating. The top portion and the bottom portion can telescope to vary the dispenser's overall height. In one embodiment, by designing a dispenser having bottom sidewalls and top sidewalls of approximately the same length, problems with access to the exposed sheet or excessive manipulation to change the dispenser's height can be avoided. In another embodiment, by designing the dispenser such that the height of the dispenser can automatically reduce as the sheet material is depleted or where the height can be adjusted by simply pushing down on the dispenser's top makes the dispenser convenient to use.
摘要翻译：用于片材的分配器包括顶部，底部和防止顶部和底部分离的限制构件。顶部和底部可以伸缩以改变分配器的整体高度。在一个实施例中，通过设计具有大致相同长度的底侧壁和顶侧壁的分配器，可以避免进入暴露片材的问题或过度操作以改变分配器的高度。在另一个实施例中，通过设计分配器，使得分配器的高度可随着片材耗尽而自动降低，或者通过简单地向下按分配器的顶部来调整高度，使得分配器方便使用。

3. 发明申请

US20070118628A1 Live network configuration within a link based computing system 有权
标题翻译：基于链路的计算系统中的实时网络配置
公开(公告)号：US20070118628A1
公开(公告)日：2007-05-24
申请号：US11284537
申请日：2005-11-21
申请人： Mohan Kumar , Murugasamy Nachimuthu , Allen Baum
发明人： Mohan Kumar , Murugasamy Nachimuthu , Allen Baum
IPC分类号： G06F15/177
CPC分类号： H04L41/082
摘要： A method is described in which, in response to notice of a configuration event yet to happen within a network that is part of a link-based computing system, a component within said link based computing system: a) identifies networking configuration information changes to be made by components within the link-based computing system; and, b) sends instances of program code to each one of the components. Each instance of program code is to be executed by a specific component that it was sent to. Each instance of program code is customized to implement the particular one or more networking configuration information changes to be made at the specific component it was sent to.
摘要翻译：描述了一种方法，其中响应于在作为基于链路的计算系统的一部分的网络内尚未发生的配置事件的通知，所述基于链路的计算系统中的组件：a）将网络配置信息变化标识为由基于链路的计算系统中的组件构成; 和b）将程序代码的实例发送到每个组件。程序代码的每个实例都要由发送到的特定组件来执行。程序代码的每个实例被定制以实现要在其发送到的特定组件上进行的特定一个或多个网络配置信息更改。

4. 发明授权

US4809160A Privilege level checking instruction for implementing a secure hierarchical computer system 失效
标题翻译：用于实施安全分级计算机系统的权限级别检查指令
公开(公告)号：US4809160A
公开(公告)日：1989-02-28
申请号：US792702
申请日：1985-10-28
申请人： Michael J. Mahon , Allen Baum , William R. Bryg , Terrence C. Miller
发明人： Michael J. Mahon , Allen Baum , William R. Bryg , Terrence C. Miller
IPC分类号： G06F12/14 , G06F9/455 , G06F9/46 , G06F11/00 , G06F21/24
CPC分类号： G06F9/468 , G06F9/45537
摘要： A low overhead way for insuring that only routines of sufficient privilege can execute on a secured page of memory in an hierarchial computer system, and for raising the privilege level of a low privilege process in an orderly and secure way is presented. This is done through the execution of a single "gateway" branch instruction standing between a procedure call by a lower privileged routine, such as a user program, and an operating system itself.
摘要翻译：提供了一种低开销方式，用于确保仅有足够权限的例程可以在分层计算机系统中的存储器的安全页面上执行，并且以有序和安全的方式提高低特权过程的特权级别。这通过执行站在诸如用户程序的较低特权例程的过程调用与操作系统本身之间的单个“网关”分支指令来完成。

5. 发明授权

US4713755A Cache memory consistency control with explicit software instructions 失效
标题翻译：具有显式软件指令的缓存内存一致性控制
公开(公告)号：US4713755A
公开(公告)日：1987-12-15
申请号：US750381
申请日：1985-06-28
申请人： William S. Worley, Jr. , William R. Bryg , Allen Baum
发明人： William S. Worley, Jr. , William R. Bryg , Allen Baum
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3812 , G06F12/0804 , G06F12/0837 , Y10S707/99934
摘要： Memory integrity is maintained in a system with a hierarchical memory using a set of explicit cache control instructions. The caches in the system have two status flags, a valid bit and a dirty bit, with each block of information stored. The operating system executes selected cache control instructions to ensure memory integrity whenever there is a possibility that integrity could be compromised.
摘要翻译：在使用一组显式高速缓存控制指令的分层存储器的系统中维持存储器完整性。系统中的缓存具有两个状态标志，一个有效位和一个脏位，每个信息块都被存储。操作系统执行选定的缓存控制指令，以确保内存完整性，只要可能会危及完整性。

6. 发明授权

US08301907B2 Supporting advanced RAS features in a secured computing system 有权
标题翻译：支持安全计算系统中的高级RAS功能
公开(公告)号：US08301907B2
公开(公告)日：2012-10-30
申请号：US11863563
申请日：2007-09-28
申请人： Mahesh S. Natu , Sham Datta , Jeff Wiedemeier , James R. Vash , Sailesh Kottapalli , Scott P. Bobholz , Allen Baum
发明人： Mahesh S. Natu , Sham Datta , Jeff Wiedemeier , James R. Vash , Sailesh Kottapalli , Scott P. Bobholz , Allen Baum
IPC分类号： G06F11/30
CPC分类号： G06F15/16
摘要： Systems and methods for enabling Reliability, Availability & Serviceability features after launching a secure environment under the control of LaGrande Technology (LT), or comparable security technology, without compromising security are provided. In one embodiment, the method comprises adding at least one specific capability to a processor to enable at least one of CPU hot-plug, CPU migration, CPU hot removal and capacity on demand.
摘要翻译：提供了在LaGrande Technology（LT）控制下启动可靠性，可用性和可维护性特性后，提供可靠性，可用性和可维护性功能的系统和方法，或者可比较的安全技术，而不会影响安全性。在一个实施例中，该方法包括将至少一个特定能力添加到处理器，以实现CPU热插拔，CPU迁移，CPU热去除和按需容量中的至少一个。

7. 发明申请

US20090089566A1 SUPPORTING ADVANCED RAS FEATURES IN A SECURED COMPUTING SYSTEM 有权
标题翻译：支持安全计算系统中的高级RAS功能
公开(公告)号：US20090089566A1
公开(公告)日：2009-04-02
申请号：US11863563
申请日：2007-09-28
申请人： Mahesh S. Natu , Sham Datta , Jeff Wiedemeier , James R. Vash , Sailesh Kottapalli , Scott P. Bobholz , Allen Baum
发明人： Mahesh S. Natu , Sham Datta , Jeff Wiedemeier , James R. Vash , Sailesh Kottapalli , Scott P. Bobholz , Allen Baum
IPC分类号： G06F15/177
CPC分类号： G06F15/16
摘要： Systems and methods for enabling Reliability, Availability & Serviceability features after launching a secure environment under the control of LaGrande Technology (LT), or comparable security technology, without compromising security are provided. In one embodiment, the method comprises adding at least one specific capability to a processor to enable at least one of CPU hot-plug, CPU migration, CPU hot removal and capacity on demand.
摘要翻译：提供了在LaGrande Technology（LT）控制下启动可靠性，可用性和可维护性特性后，提供可靠性，可用性和可维护性功能的系统和方法，或者可比较的安全技术，而不会影响安全性。在一个实施例中，该方法包括将至少一个特定能力添加到处理器，以实现CPU热插拔，CPU迁移，CPU热去除和按需容量中的至少一个。

8. 发明申请

US20070041405A1 Method and system for response determinism by synchronization 有权
标题翻译：通过同步的响应确定性的方法和系统
公开(公告)号：US20070041405A1
公开(公告)日：2007-02-22
申请号：US11166030
申请日：2005-06-23
申请人： Muraleedhara Navada , Tim Frodsham , Sanjay Dabral , Allen Baum , Chris Matthews , Chris Gianos , Rahul Shah , Theodore Schoenborn
发明人： Muraleedhara Navada , Tim Frodsham , Sanjay Dabral , Allen Baum , Chris Matthews , Chris Gianos , Rahul Shah , Theodore Schoenborn
IPC分类号： H04J3/06
CPC分类号： H04L7/10 , H04L7/0008 , H04L7/0041
摘要： A discussion of improving integrated device deterministic response to test vectors. For example, limiting the transmission delay for an integrated device's response within known bounds by synchronizing an initialization training sequence to a reset deassertion. Specifically, the proposal facilitates response determinism from the DUT by synchronizing training sequences and subsequently synchronizing flit transmission to reset assertion as sampled by reference clock.
摘要翻译：关于改进对测试矢量的集成设备确定性响应的讨论。例如，通过将初始化训练序列同步到复位失效来限制在已知边界内的集成设备的响应的传输延迟。具体地，该提议通过使训练序列同步并随后将颤振传输同步到由参考时钟采样的复位断言来促进来自DUT的响应确定性。

9. 发明申请

US20060225074A1 Method and apparatus for communication between two or more processing elements 失效
标题翻译：用于在两个或多个处理元件之间进行通信的方法和装置
公开(公告)号：US20060225074A1
公开(公告)日：2006-10-05
申请号：US11095341
申请日：2005-03-30
申请人： Kushagra Vaid , John Crawford , Allen Baum
发明人： Kushagra Vaid , John Crawford , Allen Baum
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/522
摘要： A technique for performing barrier synchronization among a plurality of program threads. More particularly, at least one embodiment of the invention keeps track of completed tasks associated with a number of program threads using bits within a barrier register that can be updated and reassigned without incurring the amount of bus traffic as in the prior art.
摘要翻译：一种用于在多个程序线程之间执行屏障同步的技术。更具体地，本发明的至少一个实施例使用可以被更新和重新分配的屏障寄存器内的位来跟踪与多个程序线程相关联的完成的任务，而不会像现有技术那样产生总线流量。

10. 发明授权

US4947364A Method in a computing system for performing a multiplication 失效
标题翻译：用于执行乘法的计算系统中的方法
公开(公告)号：US4947364A
公开(公告)日：1990-08-07
申请号：US392177
申请日：1989-08-09
申请人： Michael J. Mahon , Allen Baum
发明人： Michael J. Mahon , Allen Baum
IPC分类号： G06F7/52
CPC分类号： G06F7/5332
摘要： In a computing system a method for performing a multiplication of a first multiplicand and a second multiplicand is presented. The computing system includes a plurality of registers, an instruction decoder, an arithmetic logic unit, and a preshifter. The first multiplicand is divided into a plurality of equal length sections. Each section includes "n" bits, where "n" is an integer greater than one. The second multiplicand is placed in a first register from the plurality of registers. A second register from the plurality of registers is cleared to zero. For each section from the plurality of sections, starting with a first section containing high order bits of the first multiplication and proceeding to a last section of the first multiplicand containing low order bits of the first multiplicand the following three substeps. First, when the low order bit of a current section is a "1", the contents of the first register are added to the contents of the second register via the arithmetic logic unit. Second, for every other bit in the current section that is a "1", a shift-and-add operation is performed by shifting, via the preshifter, the contents of the first register by an amount equal to the number of bit places the bit is to the left of the low order bit of the current section and by adding, via the arithmetic logic unit, the preshifted contents of the first register to the contents of the second register. Third, for every section from the plurality of sections that does not contain low order bits of the first multiplicand, the contents of the first register "n" bits are shifted to the left.
摘要翻译：在计算系统中，呈现执行第一被乘数和第二被乘数相乘的方法。计算系统包括多个寄存器，指令解码器，算术逻辑单元和预定机。第一被乘数被分成多个等长的部分。每个部分包括“n”位，其中“n”是大于1的整数。第二被乘数被放置在来自多个寄存器的第一寄存器中。来自多个寄存器的第二寄存器被清零。对于来自多个部分的每个部分，从包含第一乘法的高阶位的第一部分开始，并且进行到包含第一被乘数的低阶位的第一被乘数的最后部分以及以下三个子步骤。首先，当当前部分的低位位为“1”时，第一寄存器的内容经由算术逻辑单元被添加到第二寄存器的内容。第二，对于当前部分中的“1”的每个其他位，移位和加法运算是通过预定机器将第一寄存器的内容移位等于位置数位位于当前部分的低位位置的左侧，并且经由算术逻辑单元将第一寄存器的预定内容相加到第二寄存器的内容。第三，对于不包含第一被乘数的低位的多个部分的每个部分，第一个寄存器“n”位的内容向左移位。

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