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1. 发明授权

US07414554B1 Low-cost linearity correction in an ADC without storing lookup tables 有权
标题翻译： ADC中的低成本线性校正，无需存储查找表
公开(公告)号：US07414554B1
公开(公告)日：2008-08-19
申请号：US11512295
申请日：2006-08-29
申请人： Anatoliy V. Tsyrganovich
发明人： Anatoliy V. Tsyrganovich
IPC分类号： H03M1/10
CPC分类号： H03M1/1038 , H03M1/1028 , H03M1/12
摘要： Linearity correction is performed by determining whether a data output value (DOUT) from an analog-to-digital converter (ADC) is in a first subrange or a second subrange. If DOUT is in the first subrange, then DOUT is scaled by a first scaling correction factor (SCF1), and the result is adjusted by a first best fit adjustment value (BFAV1). If DOUT is in the second subrange, then DOUT is scaled by a second scaling correction factor (SCF2), and the result is adjusted by a second best fit adjustment value (BFAV2). The data output range of an ADC can be processed in many ranges of such subranges. Techniques are set forth for determining SCF1, SCF2, BFAV1 and BFAV2. Employing the linearity correction method allows a low-cost microcontroller having an ADC to perform adequate linearity correction on the ADC output data without having to store an INL lookup table.
摘要翻译：通过确定来自模数转换器（ADC）的数据输出值（DOUT）是否处于第一子范围或第二子范围来执行线性校正。如果DOUT处于第一子范围，则DOUT按第一缩放校正因子（SCF 1）缩放，并且结果通过第一最佳拟合调整值（BFAV 1）进行调整。如果DOUT处于第二子范围，则DOUT按第二缩放校正因子（SCF 2）缩放，结果通过第二最佳拟合调整值（BFAV 2）进行调整。 ADC的数据输出范围可以在这种子范围的许多范围内进行处理。阐述了确定SCF 1，SCF 2，BFAV 1和BFAV 2的技术。使用线性校正方法允许具有ADC的低成本微控制器对ADC输出数据执行适当的线性校正，而不必存储INL查找表。

2. 发明授权

US07002415B2 Frequency locked loop 有权
标题翻译：锁频环路
公开(公告)号：US07002415B2
公开(公告)日：2006-02-21
申请号：US10690874
申请日：2003-10-21
申请人： Anatoliy V. Tsyrganovich
发明人： Anatoliy V. Tsyrganovich
IPC分类号： H03L7/00
CPC分类号： H03L7/085 , H03D13/001 , H03L7/091
摘要： A frequency locked loop in a microcontroller integrated circuit has a precision digital feedback control loop. The frequency locked loop performs a clock multiplication function such that an inexpensive and low frequency external crystal is usable to both clock a processor of the microcontroller with a higher frequency and low-jitter clock signal and to clock a real time clock of the microcontroller with a low frequency time base that is a power of two multiple of one hertz. In one embodiment, the digital feedback control loop includes a ramp generator, a digital filter, and a loop divider. The ramp generator is controlled to output steeper and steeper ramps as the frequency locking process proceeds toward frequency lock. A preset value that presets the loop divider is changed to adjust the phase of a feedback signal with respect to a reference input signal.
摘要翻译：微控制器集成电路中的锁相环具有精确的数字反馈控制回路。频率锁定环执行时钟相乘功能，使得便宜且低频的外部晶体可用于以较高频率和低抖动时钟信号来对微控制器的处理器进行时钟控制，并且以一个低频时基是2赫兹的倍数。在一个实施例中，数字反馈控制回路包括斜坡发生器，数字滤波器和环路分频器。当频率锁定过程进行频率锁定时，斜坡发生器被控制以输出更陡峭和更陡峭的斜坡。改变预置环路分频器的预设值，以相对于参考输入信号调整反馈信号的相位。

3. 发明授权

US6163346A Dot crawl reduction in NTSC/PAL graphic encoder 失效
标题翻译： NTSC / PAL图形编码器中的点爬行减少
公开(公告)号：US6163346A
公开(公告)日：2000-12-19
申请号：US940122
申请日：1997-09-29
申请人： Anatoliy V. Tsyrganovich
发明人： Anatoliy V. Tsyrganovich
IPC分类号： H04N9/64 , H04N5/21
CPC分类号： H04N9/646
摘要： By reducing the saturation (amplitude) at changes in the hue (phase) of the chrominance subcarrier of a video signal, the phenomenon of "dot crawl" can be substantially reduced for graphic data. It has been found that large hue (phase) changes associated with graphic data can cause large frequency shifts of the chrominance subcarrier resulting in a substantial portion of the chrominance subcarrier being unsuppressed by the chrominance subcarrier rejection filter of the luminance decoder. By reducing the saturation during the hue transition, the intensity of the spurious luminance information of the non-suppressed chrominance subcarrier is reduced.
摘要翻译：通过在视频信号的色度副载波的色调（相位）的变化中减小饱和度（幅度），对于图形数据，可以显着减少“点爬行”现象。已经发现，与图形数据相关联的大的色相（相位）变化可能导致色度副载波的大的频移，导致色度副载波的大部分被亮度解码器的色度副载波抑制滤波器抑制。通过在色调转换期间减小饱和度，降低了非抑制色度副载波的杂散亮度信息的强度。

4. 发明授权

US07551110B1 Chopping and oversampling ADC having reduced low frequency drift 有权
标题翻译：斩波和过采样ADC具有降低的低频漂移
公开(公告)号：US07551110B1
公开(公告)日：2009-06-23
申请号：US12148715
申请日：2008-04-21
申请人： Anatoliy V. Tsyrganovich
发明人： Anatoliy V. Tsyrganovich
IPC分类号： H03M3/00
CPC分类号： H03M3/34 , H03M3/458
摘要： An integrated circuit includes an analog-to-digital (ADC) portion and a processor portion. The processor portion generates high frequency noise. The ADC portion includes chopper switches, an ADC, a first low-pass filter (LPF), an inverter, and a second LPF. An analog sensor signal is chopped by the chopper switches at a chopping frequency below the processor noise frequency. The ADC performs conversions a rate higher than the chopper frequency such that multiple first conversions are performed when the chopper switches are in a first configuration and multiple second conversions are performed when the chopper switches are in a second configuration. The first LPF attenuates the high frequency noise, converts the first conversions into first information, and converts the second conversions into second information. The inverter inverts the second information. The second LPF attenuates transposed 1/F noise and converts the first information and the inverted second information into ADC output values.
摘要翻译：集成电路包括模数（ADC）部分和处理器部分。处理器部分产生高频噪声。 ADC部分包括斩波开关，ADC，第一低通滤波器（LPF），反相器和第二LPF。斩波开关的模拟传感器信号以低于处理器噪声频率的斩波频率斩波。 ADC以比斩波器频率高的速率进行转换，使得当斩波开关处于第一配置时执行多个第一转换，并且当斩波开关处于第二配置时执行多次第二转换。第一LPF衰减高频噪声，将第一转换转换成第一信息，并将第二转换转换成第二信息。逆变器反转第二个信息。第二LPF衰减转置的1 / F噪声，并将第一信息和反相第二信息转换为ADC输出值。

5. 发明授权

US06839010B1 Sigma-delta analog-to-digital converter with reduced quantization noise 有权
标题翻译： Sigma-delta模数转换器具有降低的量化噪声
公开(公告)号：US06839010B1
公开(公告)日：2005-01-04
申请号：US10331037
申请日：2002-12-27
申请人： Anatoliy V. Tsyrganovich
发明人： Anatoliy V. Tsyrganovich
IPC分类号： H03M3/00
CPC分类号： H03M3/344 , H03M3/458
摘要： An improved sigma-delta converter includes a post converter filter that receives a digital data stream. The data stream has a digital amplitude and contains quantization noise. Quantization noise is larger for digital amplitudes in a second larger-amplitude range than in a first smaller-amplitude range. The post converter filter has a higher cut-off frequency when the digital amplitude is in the first amplitude range and a lower cut-off frequency when the digital amplitude is in the second amplitude range. The post converter filter therefore filters out a portion of the larger quantization noise when the digital amplitude is larger. Quanitization noise is reduced without limiting the input signal voltage range that can be digitized.

6. 发明授权

US6002449A Integrated television processor 失效
标题翻译：综合电视处理器
公开(公告)号：US6002449A
公开(公告)日：1999-12-14
申请号：US950722
申请日：1997-10-15
申请人： Anatoliy V. Tsyrganovich
发明人： Anatoliy V. Tsyrganovich
IPC分类号： H04N5/44 , H04N5/445 , H04N5/775
CPC分类号： H04N5/775 , H04N21/426 , H04N5/44 , H04N5/4401 , H04N5/44504
摘要： By forming a digital video processor and digital television controller on the same integrated circuit, a number of advantages in improved picture quality can be obtained. The length of the communication connections between these two elements can be reduced, thus reducing television picture distortion caused by electromagnetic interference. Additionally, the elements can be controlled by a single dot clock generator with a single phase locked loop circuit. Also, register banks can be used for intercommunication between the television controller and the video processor rather than the communication between two different ICs over a bus.
摘要翻译：通过在同一集成电路上形成数字视频处理器和数字电视控制器，可以获得提高图像质量的许多优点。这两个元件之间的通信连接的长度可以减少，从而减少由电磁干扰引起的电视图像失真。另外，这些元件可以由具有单个锁相环电路的单点时钟发生器控制。此外，寄存器组可以用于电视控制器和视频处理器之间的相互通信，而不是通过总线上的两个不同IC之间的通信。

7. 发明授权

US07688307B1 Determining the distance an object has moved using an accelerometer 有权
标题翻译：使用加速度计确定物体移动的距离
公开(公告)号：US07688307B1
公开(公告)日：2010-03-30
申请号：US11339233
申请日：2006-01-24
申请人： Anatoliy V. Tsyrganovich
发明人： Anatoliy V. Tsyrganovich
IPC分类号： G06F3/033 , G09G5/08
CPC分类号： G06F3/0346 , G06F3/03543 , G06F3/0383
摘要： An accelerometer-based mouse is one example of a device that determines the distance an object moves. The mouse disables a cursor from moving across a computer screen during movements of the mouse that occur while the mouse is lifted from a working surface. A mouse control unit generates a cursor movement disable signal that stops the cursor from moving from the time the mouse is lifted until the mouse is set down. The mouse control unit generates the disable signal by determining the derivative of an acceleration signal for the vertical (z) dimension relative to the working surface. The mouse includes a microcontroller programmed to disengage cursor movement when the cursor movement disable signal is asserted. The mouse does not include a ball and rollers whose performance can degrade as they become dirty. The mouse can detect movement even when the mouse slides over a surface that has no pattern.
摘要翻译：基于加速度计的鼠标是确定对象移动距离的设备的一个示例。当鼠标从工作表面抬起时，鼠标移动过程中鼠标移动时，鼠标将禁用光标移动到计算机屏幕上。鼠标控制单元产生光标移动禁止信号，停止光标从鼠标提升直到鼠标放下的时候移动。鼠标控制单元通过确定垂直（z）尺寸相对于工作表面的加速度信号的导数来产生禁用信号。鼠标包括一个被编程为当光标移动禁止信号被断言时使光标移动脱离的微控制器。鼠标不包括球和辊，其性能可能随着脏污而降解。即使鼠标在没有图案的表面上滑动，鼠标也可以检测动作。

8. 发明授权

US07414553B1 Microcontroller having in-situ autocalibrated integrating analog-to-digital converter (IADC) 有权
标题翻译：具有原位自动校准的集成模数转换器（IADC）的微控制器
公开(公告)号：US07414553B1
公开(公告)日：2008-08-19
申请号：US11601003
申请日：2006-11-17
申请人： Anatoliy V. Tsyrganovich
发明人： Anatoliy V. Tsyrganovich
IPC分类号： H03M1/06
CPC分类号： H03M1/1028 , H03M1/56
摘要： A microcontroller has an integrating analog-to-digital converter (IADC) with an in-situ autocalibrating functionality. On-chip autocalibrating circuitry supplies a first predetermined analog input voltage to the IADC and obtains a first data value from the IADC. The autocalibrating circuitry supplies a second predetermined analog input voltage to the IADC and obtains a second data value. The first and second data values are used to calibrate the IADC such that if the first input voltage is later supplied to the IADC, then the IADC will output a first predetermined desired digital output value and such that if the second input voltage is later supplied to the IADC, then the IADC will output a second predetermined desired digital output value. The first and second analog input voltages are generated on-chip so the calibration is performed automatically without having to supply external calibrating signals to the microcontroller. Other related methods and circuitry is disclosed.
摘要翻译：微控制器具有集成模数转换器（IADC），具有原位自动校准功能。片上自动校准电路向IADC提供第一预定模拟输入电压，并从IADC获得第一数据值。自动校准电路将第二预定模拟输入电压提供给IADC，并获得第二数据值。第一和第二数据值用于校准IADC，使得如果第一输入电压稍后被提供给IADC，则IADC将输出第一预定期望的数字输出值，并且使得如果第二输入电压稍后被提供给 IADC，则IADC将输出第二预定的期望的数字输出值。第一和第二模拟输入电压是片上产生的，因此校准自动执行，而不必向微控制器提供外部校准信号。公开了其它相关方法和电路。

9. 发明授权

US07362255B1 Chopping and oversampling ADC having reduced low frequency drift 有权
标题翻译：斩波和过采样ADC具有降低的低频漂移
公开(公告)号：US07362255B1
公开(公告)日：2008-04-22
申请号：US11378785
申请日：2006-03-18
申请人： Anatoliy V. Tsyrganovich
发明人： Anatoliy V. Tsyrganovich
IPC分类号： H03M1/12
CPC分类号： H03M3/34 , H03M3/458
摘要： An integrated circuit includes an analog-to-digital (ADC) portion and a processor portion. The processor portion generates high frequency noise. The ADC portion includes chopper switches, an ADC, a first low-pass filter (LPF), an inverter, and a second LPF. An analog sensor signal is chopped by the chopper switches at a chopping frequency below the processor noise frequency. The ADC performs conversions a rate higher than the chopper frequency such that multiple first conversions are performed when the chopper switches are in a first configuration and multiple second conversions are performed when the chopper switches are in a second configuration. The first LPF attenuates the high frequency noise, converts the first conversions into first information, and converts the second conversions into second information. The inverter inverts the second information. The second LPF attenuates transposed 1/F noise and converts the first information and the inverted second information into ADC output values.
摘要翻译：集成电路包括模数（ADC）部分和处理器部分。处理器部分产生高频噪声。 ADC部分包括斩波开关，ADC，第一低通滤波器（LPF），反相器和第二LPF。斩波开关的模拟传感器信号以低于处理器噪声频率的斩波频率斩波。 ADC以比斩波器频率高的速率进行转换，使得当斩波开关处于第一配置时执行多个第一转换，并且当斩波开关处于第二配置时执行多次第二转换。第一LPF衰减高频噪声，将第一转换转换成第一信息，并将第二转换转换成第二信息。逆变器反转第二个信息。第二LPF衰减转置的1 / F噪声，并将第一信息和反相第二信息转换为ADC输出值。

10. 发明授权

US07170239B2 Circuit and method for reducing east-west geometry mismatch between the top and bottom of a raster display 有权
标题翻译：用于减少光栅显示器顶部和底部之间的东西几何失配的电路和方法
公开(公告)号：US07170239B2
公开(公告)日：2007-01-30
申请号：US10876358
申请日：2004-06-23
申请人： Anatoliy V. Tsyrganovich
发明人： Anatoliy V. Tsyrganovich
IPC分类号： G09G1/28
CPC分类号： H04N3/2335
摘要： The present disclosure describes a technique for reducing east-west geometry mismatch between the top and bottom of a raster display. This is accomplished by generating a horizontal correction signal that does not have any discontinuities. Since there are no discontinuities in the horizontal correction signal, the horizontal deflection current signal will not be distorted. As a result, there will be no east-west geometry mismatch between the top and bottom of the raster display.
摘要翻译：本公开描述了一种用于减少光栅显示器的顶部和底部之间的东西几何失配的技术。这是通过产生不具有任何不连续性的水平校正信号来实现的。由于在水平校正信号中没有不连续性，水平偏转电流信号不会失真。因此，栅格显示的顶部和底部之间将不会出现东西几何不匹配。

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