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1. 发明申请

US20180191362A1 PATTERN BASED ESTIMATION OF ERRORS IN ADC 审中-公开
公开(公告)号：US20180191362A1
公开(公告)日：2018-07-05
申请号：US15909378
申请日：2018-03-01
申请人： Texas Instruments Incorporated
发明人： Srinivas Kumar Reddy Naru , Visvesvaraya Pentakota Appala , Shagun Dusad , Neeraj Shrivastava , Viswanathan Nagarajan , Ani Xavier , Rishi Soundararajan , Sai Aditya Nurani , Roswald Francis
IPC分类号： H03M1/06 , H03M1/12 , H03M1/10 , H03M1/16 , H03M1/36
CPC分类号： H03M1/06 , H03M1/1038 , H03M1/109 , H03M1/1205 , H03M1/164 , H03M1/361
摘要： The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

2. 发明授权

US09941893B2 Pattern based estimation of errors in ADC 有权
公开(公告)号：US09941893B2
公开(公告)日：2018-04-10
申请号：US15485552
申请日：2017-04-12
申请人： Texas Instruments Incorporated
发明人： Srinivas Kumar Reddy Naru , Visvesvaraya Pentakota Appala , Shagun Dusad , Neeraj Shrivastava , Viswanathan Nagarajan , Ani Xavier , Rishi Soundararajan , Sai Aditya Nurani , Roswald Francis
IPC分类号： H03M1/00 , H03M1/06 , H03M1/12
CPC分类号： H03M1/06 , H03M1/1038 , H03M1/109 , H03M1/1205 , H03M1/164 , H03M1/361
摘要： An ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

3. 发明授权

US09735797B2 Digital measurement of DAC timing mismatch error 有权
公开(公告)号：US09735797B2
公开(公告)日：2017-08-15
申请号：US15360349
申请日：2016-11-23
申请人： ANALOG DEVICES, INC.
发明人： Jialin Zhao , Qingdong Meng , Yunzhi Dong , Jose Barreiro Silva
IPC分类号： H03M1/00 , H03M1/10 , H03M1/46 , H03M3/00
CPC分类号： H03M1/1071 , H03M1/1038 , H03M1/16 , H03M1/38 , H03M1/46 , H03M3/412 , H03M3/464
摘要： For analog-to-digital converters (ADCs) which utilize a feedback digital-to-analog converter (DAC) for conversion, the final analog output can be affected or distorted by errors of the feedback DAC. A digital measurement technique can be implemented to determine timing mismatch error for the feedback DAC in a continuous-time delta-sigma modulator (CTDSM) or in a continuous-time pipeline modulator. The methodology utilizes cross-correlation of each DAC unit elements (UEs) output to the entire modulator output to measure its timing mismatch error respectively. Specifically, the timing mismatch error is estimated using a ratio based on a peak value and a value for the next tap in the cross-correlation function. The obtained errors can be stored in a look-up table and fully corrected in digital domain or analog domain.

4. 发明申请

US20170170840A1 DIGITAL MEASUREMENT OF DAC SWITCHING MISMATCH ERROR 有权
公开(公告)号：US20170170840A1
公开(公告)日：2017-06-15
申请号：US15360617
申请日：2016-11-23
申请人： Analog Devices, Inc.
发明人： Jialin ZHAO
IPC分类号： H03M1/10 , H03M1/12 , H03M3/00
CPC分类号： H03M1/1071 , H03M1/1038 , H03M1/1057 , H03M1/1245 , H03M1/167 , H03M1/46 , H03M1/74 , H03M3/378 , H03M3/422 , H03M3/464
摘要： For analog-to-digital converters (ADCs) which utilize a feedback digital-to-analog converter (DAC) for conversion, the final analog output can be affected or distorted by errors of the feedback DAC. A digital measurement technique can be implemented to determine switching mismatch error for the feedback DAC in a continuous-time delta-sigma modulator (CTDSM) or in a continuous-time pipeline modulator. The methodology forces each DAC unit elements (UEs) to switch a certain amount times and then use the modulator itself to measure the errors caused by those switching activities respectively. The obtained errors can be stored in a look-up table and fully corrected in digital domain or analog domain.

5. 发明授权

US09680497B2 Conversion of a discrete-time quantized signal into a continuous-time, continuously variable signal 有权
公开(公告)号：US09680497B2
公开(公告)日：2017-06-13
申请号：US15361385
申请日：2016-11-26
申请人： Syntropy Systems, LLC
发明人： Christopher Pagnanelli
IPC分类号： H03M1/06 , H03M3/00
CPC分类号： H03M3/36 , H03F1/08 , H03F1/30 , H03F1/3247 , H03F1/3258 , H03F3/2175 , H03F3/45475 , H03F2200/447 , H03F2203/45528 , H03M1/1038 , H03M1/785 , H03M3/358 , H03M3/40 , H03M3/402 , H03M3/50 , H03M3/502 , H03M7/3026 , H03M7/3033 , H04L27/362
摘要： Provided are, among other things, systems, apparatuses, methods and techniques for converting a discrete-time quantized signal into a continuous-time, continuously variable signal. An exemplary converter preferably includes: (1) multiple oversampling converters, each processing a different frequency band, operated in parallel; (2) multirate (i.e., polyphase) delta-sigma modulators (preferably second-order or higher); (3) multi-bit quantizers; (4) multi-bit-to-variable-level signal converters, such as resistor ladder networks or current source networks; (5) adaptive nonlinear, bit-mapping to compensate for mismatches in the multi-bit-to-variable-level signal converters (e.g., by mimicking such mismatches and then shifting the resulting noise to a frequently range where it will be filtered out by a corresponding bandpass (reconstruction) filter); (6) multi-band (e.g., programmable noise-transfer-function response) bandpass delta-sigma modulators; and/or (7) a digital pre-distortion linearizer (DPL) for canceling noise and distortion introduced by an analog signal bandpass (reconstruction) filter bank.

6. 发明授权

US09584146B2 System and method for measuring the DC-transfer characteristic of an analog-to-digital converter 有权
标题翻译：用于测量模数转换器的直流传递特性的系统和方法
公开(公告)号：US09584146B2
公开(公告)日：2017-02-28
申请号：US14886545
申请日：2015-10-19
申请人： MediaTek Inc.
发明人： Frank Op 't Eynde , Nathan Egan , Khurram Muhammad , Tien-Yu Lo , Chi-Lun Lo , Michael A. Ashburn
IPC分类号： H03M1/10 , H03M1/12 , H03M3/00
CPC分类号： H03M1/109 , H03M1/1038 , H03M1/12 , H03M3/50
摘要： Systems and methods for measuring and compensating a DC-transfer characteristic of analog-to-digital converters are described. A test-signal generator comprising a sigma-delta modulator may provide calibration signals to an ADC. An output from the ADC may be filtered with a notch filter to suppress quantization noise at discrete frequencies introduced by the sigma-delta modulator. The resulting filtered signal may be compared against an input digital signal to the test-signal generator to determine a transfer characteristic of the ADC.
摘要翻译：描述了用于测量和补偿模数转换器的直流传递特性的系统和方法。包括Σ-Δ调制器的测试信号发生器可以向ADC提供校准信号。来自ADC的输出可以用陷波滤波器滤波，以抑制由Σ-Δ调制器引入的离散频率的量化噪声。所得到的滤波信号可以与输入的数字信号与测试信号发生器进行比较，以确定ADC的传输特性。

7. 发明申请

US20160308545A1 DIGITAL-TO-ANALOG CONVERTER (DAC) WITH ENHANCED DYNAMIC ELEMENT MATCHING (DEM) AND CALIBRATION 有权
标题翻译：具有增强动态元件匹配（DEM）和校准的数字到模拟转换器（DAC）
公开(公告)号：US20160308545A1
公开(公告)日：2016-10-20
申请号：US15130617
申请日：2016-04-15
申请人： MaxLinear, Inc.
发明人： Gaurav Chandra , Tao Zeng , Shantha Murthy Prem Swaroop
IPC分类号： H03M1/06 , H03M1/68 , H03M1/10
CPC分类号： H03M1/066 , H03M1/1038 , H03M1/66
摘要： Systems and methods are provided for digital-to-analog converters (DACs) with enhanced dynamic element matching (DEM) and calibration. DEM may be adapted based on assessment of one or more conditions that may affect the DACs or DEM functions thereof. The one or more condition may comprise amount of signal backoff. The adaption may comprise switching the DEM function (as a whole, or partially—e.g., individual DEM elements) on or off based on the assess conditions. The DACs may incorporate use of calibration. The DEM and/or the calibration may be applied to only a portion of the DAC, such as a particular segment (e.g., a middle segment comprising bits between the MSBs and the LSBs).
摘要翻译：为具有增强的动态元素匹配（DEM）和校准的数模转换器（DAC）提供了系统和方法。可以基于可能影响DAC或其DEM功能的一个或多个条件的评估来调整DEM。一个或多个条件可以包括信号回退量。适应可以包括基于评估条件来打开或关闭DEM功能（整体上，或部分地，例如，单独的DEM元件）。 DAC可以使用校准。 DEM和/或校准可以仅应用于DAC的一部分，例如特定段（例如，包括MSB和LSB之间的位的中间段）。

8. 发明授权

US09407279B2 Systems and methods of element scrambling for compensation and calibration of analog-to-digital converter feedback 有权
标题翻译：元件加扰的系统和方法用于模数转换器反馈的补偿和校准
公开(公告)号：US09407279B2
公开(公告)日：2016-08-02
申请号：US14617376
申请日：2015-02-09
申请人： Cirrus Logic, Inc.
发明人： John L. Melanson , Jaimin Mehta , Stephen T. Hodapp
IPC分类号： H03M1/10 , H03M1/06 , H03M1/08 , H03M1/66 , H03M3/00
CPC分类号： H03M1/1038 , H03M1/06 , H03M1/0665 , H03M1/0863 , H03M1/10 , H03M1/1009 , H03M1/66 , H03M3/458
摘要： An apparatus may include a scrambler element configured to receive an input signal and generate a scrambled thermometer code-like signal having a plurality of bits based on the input signal and having a plurality of possible quantization values. The scrambler element may generate at least one equivalent code of the scrambled thermometer code-like signal for each possible quantization value. For each of one or more of the possible quantization values, the scrambler element may be configured to generate a plurality of possible equivalent codes of the scrambled thermometer code-like signal. Responsive to the input signal indicating a change in quantization value of the scrambled thermometer code-like signal, the scrambler element may change the scrambled thermometer code-like signal by transitioning the smallest possible number of the plurality of bits of the scrambled thermometer code-like signal to change quantization value of the scrambled thermometer code-like signal in accordance with the input signal.
摘要翻译：装置可以包括扰频器元件，其被配置为接收输入信号并且基于输入信号生成具有多个比特的加扰温度计类似码字的信号，并且具有多个可能的量化值。加扰器元件可以为每个可能的量化值生成加扰的温度计代码样信号的至少一个等效代码。对于一个或多个可能的量化值中的每个，加扰器元件可以被配置为生成加扰的温度计代码样信号的多个可能的等效代码。响应于指示加扰的温度计编码类信号的量化值的改变的输入信号，加扰器元件可以通过转换加扰的温度计代码样信号的多个比特的最小可能数来改变加扰的温度计代码样信号信号以根据输入信号改变加扰的温度计代码样信号的量化值。

9. 发明授权

US09362931B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09362931B2
公开(公告)日：2016-06-07
申请号：US14750242
申请日：2015-06-25
申请人： Renesas Electronics Corporation
发明人： Takaya Yamamoto , Hideo Nakane , Keisuke Kimura , Yuichi Okuda , Takashi Oshima
IPC分类号： H03M1/12 , H03M1/00 , H03M1/06 , H03M1/46 , H03M1/10
CPC分类号： H03M1/002 , H03M1/0609 , H03M1/0639 , H03M1/1009 , H03M1/1038 , H03M1/124 , H03M1/145 , H03M1/38 , H03M1/462 , H03M1/468
摘要： There is provided a semiconductor device using low electric power and a small area which can realize highly accurate calibration. The semiconductor device according to the embodiment includes an A/D conversion unit, and a hold signal generating circuit which is coupled to an input side of the A/D conversion unit, and has a hold period not less than two cycles of the A/D conversion unit. The hold signal generating circuit includes: an SC integrator including an input buffer coupled to the input side of the A/D conversion unit, and feedback capacitor coupled to an input and an output of the input buffer; and a logic circuit which compares an output signal of plural bits outputted from the A/D conversion unit with a first and a second threshold values, and outputs a control signal which controls polarity of the SC integrator according to a comparison result.
摘要翻译：提供了一种使用低功率和小面积的半导体器件，可以实现高精度的校准。根据实施例的半导体器件包括A / D转换单元和耦合到A / D转换单元的输入侧的保持信号产生电路，并且具有不少于A / D转换单元的两个周期的保持周期， D转换单元。保持信号生成电路包括：SC积分器，包括耦合到A / D转换单元的输入侧的输入缓冲器，以及耦合到输入缓冲器的输入和输出的反馈电容器; 以及将从A / D转换单元输出的多个比特的输出信号与第一和第二阈值进行比较的逻辑电路，并根据比较结果输出控制SC积分器的极性的控制信号。

10. 发明申请

US20160142069A1 Multi-path, series-switched, passively-summed digital-to-analog converter 审中-公开
标题翻译：多路径，串行切换，被动求和的数模转换器
公开(公告)号：US20160142069A1
公开(公告)日：2016-05-19
申请号：US15004891
申请日：2016-01-23
申请人： John Howard La Grou
发明人： John Howard La Grou
IPC分类号： H03M1/08 , H03M1/66
CPC分类号： H03M1/1038 , H03M1/68
摘要： A digital-to-analog converter which minimizes noise and optimizes dynamic range by apportioning a least significant bits portion of an incoming digital signal to a low-path circuit and a most significant bits portion of the incoming digital signal to a high-path circuit. The low-path circuit has a low-path digital-to-analog converter, which feeds a low-path amplifier, which feeds a low-path resistive element, which feeds an output node. The high-path circuit has a high-path digital-to-analog converter, which feeds a high-path amplifier, which feeds a high-path resistive element when a high-path switching element is closed, which feeds an output node. The output node is a simple electrical connection of the outputs of the low-path and high-path resistive elements. The high-path switching element is closed when the incoming digital signal has an amplitude above a switching threshold level. Parameters of the circuit, including the sizes of the least significant bits portion and most significant bits portion of the incoming digital signal, are selected such that the switching threshold level is significantly above the noise level produced by the high-path circuit thereby providing psychoacoustic masking of noise produced by the high-path circuit.
摘要翻译：一种数模转换器，其通过将输入数字信号的最低有效位部分分配给输入数字信号的低通路电路和最高有效位部分到高路径电路来最小化噪声并优化动态范围。低通路电路具有低通道数模转换器，其馈送低通路放大器，该低通路放大器馈送输入节点的低通路电阻元件。高路径电路具有高通道数模转换器，其馈送高通路放大器，当高通道开关元件闭合时，高通路放大器馈送高通路电阻元件，馈送输出节点。输出节点是低通路和高通路电阻元件的输出的简单电连接。当输入数字信号具有高于开关阈值电平的幅度时，高通道开关元件闭合。选择电路的参数，包括输入数字信号的最低有效位部分和最高有效位部分的大小，使得开关阈值电平明显高于由高通路电路产生的噪声电平，从而提供心理声学屏蔽的高通路电路产生的噪声。

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