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1. 发明授权

US08930716B2 Address translation unit, device and method for remote direct memory access of a memory 有权
标题翻译：用于存储器的远程直接存储器访问的地址转换单元，设备和方法
公开(公告)号：US08930716B2
公开(公告)日：2015-01-06
申请号：US13617942
申请日：2012-09-14
申请人： Florian A. Auernhammer , Nikolaos Chrysos , Rolf Clauberg , Andreas C. Doering , Ronald P. Luijten , Patricia M. Sagmeister
发明人： Florian A. Auernhammer , Nikolaos Chrysos , Rolf Clauberg , Andreas C. Doering , Ronald P. Luijten , Patricia M. Sagmeister
IPC分类号： G06F11/30 , G06F12/10 , H04L9/00 , H04L9/08 , H04L9/32 , G06F12/14
CPC分类号： G06F12/1081 , G06F12/1408 , H04L9/00 , H04L9/0894 , H04L9/3247 , Y02D10/13
摘要： A method for Remote Direct Memory Access (RDMA) of a memory of a processor. An address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address.
摘要翻译：一种用于处理器存储器的远程直接存储器访问（RDMA）的方法。地址转换单元包括地址转换器和签名者。地址转换器被配置为在存储器的实际地址中转换接收的虚拟地址。签名者被配置为对真实地址进行加密签名。

2. 发明申请

US20120303948A1 ADDRESS TRANSLATION UNIT, DEVICE AND METHOD FOR REMOTE DIRECT MEMORY ACCESS OF A MEMORY 有权
标题翻译：地址转换单元，用于远程存储器的直接存储器访问的设备和方法
公开(公告)号：US20120303948A1
公开(公告)日：2012-11-29
申请号：US13480979
申请日：2012-05-25
申请人： Florian A. Auernhammer , Nikolaos Chrysos , Rolf Clauberg , Andreas C. Doering , Ronald P. Luijten , Patricia M. Sagmeister
发明人： Florian A. Auernhammer , Nikolaos Chrysos , Rolf Clauberg , Andreas C. Doering , Ronald P. Luijten , Patricia M. Sagmeister
IPC分类号： G06F12/14 , G06F12/10 , H04L9/00
CPC分类号： G06F12/1081 , G06F12/1408 , H04L9/00 , H04L9/0894 , H04L9/3247 , Y02D10/13
摘要： An address translation unit for Remote Direct Memory Access (RDMA) of a memory of a processor is provided. The address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address.
摘要翻译：提供了一种用于处理器的存储器的远程直接存储器访问（RDMA）的地址转换单元。地址转换单元包括地址转换器和签名者。地址转换器被配置为在存储器的实际地址中转换接收的虚拟地址。签名者被配置为对真实地址进行加密签名。

3. 发明授权

US07831805B2 Coupling a general purpose processor to an application specific instruction set processor 失效
标题翻译：将通用处理器耦合到特定于应用程序的指令集处理器
公开(公告)号：US07831805B2
公开(公告)日：2010-11-09
申请号：US11926090
申请日：2007-10-28
申请人： Andreas C. Doering , Silvio Dragone
发明人： Andreas C. Doering , Silvio Dragone
IPC分类号： G06F15/76
CPC分类号： G06F9/3877 , G06F9/30079 , G06F9/3017 , G06F9/382 , G06F9/3879
摘要： Provides methods, systems and apparatus for coupling a general purpose processor (GPP) to an application specific instruction set processor (ASIP) in such a manner that the GPP can include execute instructions that do not normally comprise part of its instruction set architecture (ISA). The GPP is coupled to the ASIP via a coprocessor port such that instructions issued by the GPP to the port are conveyed to a novel pre-decoder module of the ASIP. The pre-decoder module translates the GPP instruction into operation codes for ASIP instructions to be executed in the ASIP or to an address in the ASIP instruction memory that identifies a start address for a plurality of ASIP instructions defining a complex application specific function. Once the ASIP has executed the instructions it shares the result of the execution with the GPP. In this way, the GPP takes advantage of the ASIP in its ability to more quickly execute an application specific program/procedure.
摘要翻译：提供用于将通用处理器（GPP）耦合到应用特定指令集处理器（ASIP）的方法，系统和装置，使得GPP可以包括通常不包括其指令集架构（ISA）的一部分的执行指令，。 GPP通过协处理器端口耦合到ASIP，使得GPP向端口发出的指令被传送到ASIP的新型预解码器模块。预解码器模块将GPP指令转换为在ASIP中执行的ASIP指令的操作码或ASIP指令存储器中的一个地址，该地址标识了定义复杂应用专用功能的多个ASIP指令的起始地址。一旦ASIP执行了指令，它将与GPP共享执行结果。以这种方式，GPP利用ASIP更快地执行特定应用程序/程序的能力。

4. 发明申请

US20080270754A1 USING FIELD PROGRAMMABLE GATE ARRAY (FPGA) TECHNOLOGY WITH A MICROPROCESSOR FOR RECONFIGURABLE, INSTRUCTION LEVEL HARDWARE ACCELERATION 有权
标题翻译：使用现场可编程门阵列（FPGA）技术与微处理器进行可重新配置，指示级硬件加速
公开(公告)号：US20080270754A1
公开(公告)日：2008-10-30
申请号：US12167202
申请日：2008-07-02
申请人： Andreas C. DOERING , Silvio Dragone , Andreas Herkersdorf , Richard G. Hofmann , Charles E. Kuhlmann
发明人： Andreas C. DOERING , Silvio Dragone , Andreas Herkersdorf , Richard G. Hofmann , Charles E. Kuhlmann
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/3877 , G06F9/30181 , G06F9/3897 , G06F15/7867
摘要： A method for dynamically programming Field Programmable Gate Arrays (FPGAs) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.
摘要翻译：一种用于在协处理器中动态编程现场可编程门阵列（FPGA）的方法，所述协处理器耦合到处理器，所述协处理器包括：由处理器开始执行应用程序; 从所述处理器接收到所述协处理器的指令以执行所述应用的功能; 确定协处理器中的FPGA不是用该功能的逻辑编程的; 获取功能的配置位流; 并使用配置位流对FPGA进行编程。以这种方式，FPGA可以“即时”编程，即在执行应用期间动态地编程。应用程序可以更频繁地利用FPGA提供的硬件加速和资源共享优势。还提供了包括协处理器和处理器的芯片上的逻辑灵活性和空间节省。

5. 发明授权

US07293159B2 Coupling GP processor with reserved instruction interface via coprocessor port with operation data flow to application specific ISA processor with translation pre-decoder 失效
标题翻译：通过协处理器端口将GP处理器与预留指令接口耦合，并将操作数据流传输到具有翻译预解码器的应用程序特定ISA处理器
公开(公告)号：US07293159B2
公开(公告)日：2007-11-06
申请号：US11035934
申请日：2005-01-14
申请人： Andreas C. Doering , Silvio Dragone
发明人： Andreas C. Doering , Silvio Dragone
IPC分类号： G06F15/16
CPC分类号： G06F9/3877 , G06F9/30079 , G06F9/3017 , G06F9/382 , G06F9/3879
摘要： Provides methods, systems and apparatus for coupling a general purpose processor (GPP) to an application specific instruction set processor (ASIP) in such a manner that the GPP can include execute instructions that do not normally comprise part of its instruction set architecture (ISA). The GPP is coupled to the ASIP via a coprocessor port such that instructions issued by the GPP to the port are conveyed to a novel pre-decoder module of the ASIP. The pre-decoder module translates the GPP instruction into operation codes for ASIP instructions to be executed in the ASIP or to an address in the ASIP instruction memory that identifies a start address for a plurality of ASIP instructions defining a complex application specific function. Once the ASIP has executed the instructions it shares the result of the execution with the GPP. In this way, the GPP takes advantage of the ASIP in its ability to more quickly execute an application specific program/procedure.
摘要翻译：提供用于将通用处理器（GPP）耦合到应用特定指令集处理器（ASIP）的方法，系统和装置，使得GPP可以包括通常不包括其指令集架构（ISA）的一部分的执行指令，。 GPP通过协处理器端口耦合到ASIP，使得GPP向端口发出的指令被传送到ASIP的新型预解码器模块。预解码器模块将GPP指令转换为在ASIP中执行的ASIP指令的操作码或ASIP指令存储器中的一个地址，该地址标识了定义复杂应用专用功能的多个ASIP指令的起始地址。一旦ASIP执行了指令，它将与GPP共享执行结果。以这种方式，GPP利用ASIP更快地执行特定应用程序/程序的能力。

6. 发明申请

US20130019108A1 ADDRESS TRANSLATION UNIT, DEVICE AND METHOD FOR REMOTE DIRECT MEMORY ACCESS OF A MEMORY 有权
标题翻译：地址转换单元，用于远程存储器的直接存储器访问的设备和方法
公开(公告)号：US20130019108A1
公开(公告)日：2013-01-17
申请号：US13617942
申请日：2012-09-14
申请人： Florian A. Auernhammer , Nikolaos Chrysos , Rolf Clauberg , Andreas C. Doering , Ronald P. Luijten , Patricia M. Sagmeister
发明人： Florian A. Auernhammer , Nikolaos Chrysos , Rolf Clauberg , Andreas C. Doering , Ronald P. Luijten , Patricia M. Sagmeister
IPC分类号： G06F12/14 , G06F21/00
CPC分类号： G06F12/1081 , G06F12/1408 , H04L9/00 , H04L9/0894 , H04L9/3247 , Y02D10/13
摘要： A method for Remote Direct Memory Access (RDMA) of a memory of a processor. An address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address.
摘要翻译：一种用于处理器存储器的远程直接存储器访问（RDMA）的方法。地址转换单元包括地址转换器和签名者。地址转换器被配置为在存储器的实际地址中转换接收的虚拟地址。签名者被配置为对真实地址进行加密签名。

7. 发明授权

US08930715B2 Address translation unit, device and method for remote direct memory access of a memory 有权
标题翻译：用于存储器的远程直接存储器访问的地址转换单元，设备和方法
公开(公告)号：US08930715B2
公开(公告)日：2015-01-06
申请号：US13480979
申请日：2012-05-25
申请人： Florian A. Auernhammer , Nikolaos Chrysos , Rolf Clauberg , Andreas C. Doering , Ronald P. Luijten , Patricia M. Sagmeister
发明人： Florian A. Auernhammer , Nikolaos Chrysos , Rolf Clauberg , Andreas C. Doering , Ronald P. Luijten , Patricia M. Sagmeister
IPC分类号： G06F11/30 , G06F12/10 , H04L9/00 , H04L9/08 , H04L9/32 , G06F12/14
CPC分类号： G06F12/1081 , G06F12/1408 , H04L9/00 , H04L9/0894 , H04L9/3247 , Y02D10/13
摘要： An address translation unit for Remote Direct Memory Access (RDMA) of a memory of a processor is provided. The address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address.
摘要翻译：提供了一种用于处理器的存储器的远程直接存储器访问（RDMA）的地址转换单元。地址转换单元包括地址转换器和签名者。地址转换器被配置为在存储器的实际地址中转换接收的虚拟地址。签名者被配置为对真实地址进行加密签名。

8. 发明授权

US07603540B2 Using field programmable gate array (FPGA) technology with a microprocessor for reconfigurable, instruction level hardware acceleration 有权
标题翻译：使用现场可编程门阵列（FPGA）技术与微处理器进行可重配置，指令级硬件加速
公开(公告)号：US07603540B2
公开(公告)日：2009-10-13
申请号：US12167202
申请日：2008-07-02
申请人： Andreas C. Doering , Silvio Dragone , Andreas Herkersdorf , Richard G. Hofmann , Charles E. Kuhlmann
发明人： Andreas C. Doering , Silvio Dragone , Andreas Herkersdorf , Richard G. Hofmann , Charles E. Kuhlmann
IPC分类号： G06F9/00 , G06F15/00
CPC分类号： G06F9/3877 , G06F9/30181 , G06F9/3897 , G06F15/7867
摘要： A method for dynamically programming Field Programmable Gate Arrays (FPGAs) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.
摘要翻译：一种用于在协处理器中动态编程现场可编程门阵列（FPGA）的方法，所述协处理器耦合到处理器，所述协处理器包括：由处理器开始执行应用程序; 从所述处理器接收到所述协处理器的指令以执行所述应用的功能; 确定协处理器中的FPGA不是用该功能的逻辑编程的; 获取功能的配置位流; 并使用配置位流对FPGA进行编程。以这种方式，FPGA可以“即时”编程，即在执行应用期间动态地编程。应用程序可以更频繁地利用FPGA提供的硬件加速和资源共享优势。还提供了包括协处理器和处理器的芯片上的逻辑灵活性和空间节省。

9. 发明授权

US07584345B2 System for using FPGA technology with a microprocessor for reconfigurable, instruction level hardware acceleration 有权
标题翻译：使用FPGA技术与微处理器进行可重配置，指令级硬件加速的系统
公开(公告)号：US07584345B2
公开(公告)日：2009-09-01
申请号：US10696865
申请日：2003-10-30
申请人： Andreas C. Doering , Silvio Dragone , Andreas Herkersdorf , Richard G. Hofmann , Charles E. Kuhlmann
发明人： Andreas C. Doering , Silvio Dragone , Andreas Herkersdorf , Richard G. Hofmann , Charles E. Kuhlmann
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/3877 , G06F9/30181 , G06F9/3897 , G06F15/7867
摘要： A method for dynamically programming Field Programmable Gate Arrays (FPGA in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising thecoprocessor and processor are provided as well.
摘要翻译：一种用于动态编程现场可编程门阵列的方法（协处理器中的FPGA，耦合到处理器的协处理器）包括：由处理器开始执行应用程序;从处理器接收指令到协处理器以执行应用程序的功能 ;确定协处理器中的FPGA没有用该功能的逻辑编程;获取功能的配置位流;以及使用配置位流编程FPGA，以这种方式，FPGA可以“即时”编程，即在应用程序的执行过程中动态执行，由FPGA提供的硬件加速和资源共享优势可以被应用程序更频繁地利用，同时提供了包括微处理器和处理器在内的芯片的逻辑灵活性和空间节省。

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