专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08930715B2 Address translation unit, device and method for remote direct memory access of a memory 有权
标题翻译：用于存储器的远程直接存储器访问的地址转换单元，设备和方法
公开(公告)号：US08930715B2
公开(公告)日：2015-01-06
申请号：US13480979
申请日：2012-05-25
申请人： Florian A. Auernhammer , Nikolaos Chrysos , Rolf Clauberg , Andreas C. Doering , Ronald P. Luijten , Patricia M. Sagmeister
发明人： Florian A. Auernhammer , Nikolaos Chrysos , Rolf Clauberg , Andreas C. Doering , Ronald P. Luijten , Patricia M. Sagmeister
IPC分类号： G06F11/30 , G06F12/10 , H04L9/00 , H04L9/08 , H04L9/32 , G06F12/14
CPC分类号： G06F12/1081 , G06F12/1408 , H04L9/00 , H04L9/0894 , H04L9/3247 , Y02D10/13
摘要： An address translation unit for Remote Direct Memory Access (RDMA) of a memory of a processor is provided. The address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address.
摘要翻译：提供了一种用于处理器的存储器的远程直接存储器访问（RDMA）的地址转换单元。地址转换单元包括地址转换器和签名者。地址转换器被配置为在存储器的实际地址中转换接收的虚拟地址。签名者被配置为对真实地址进行加密签名。

2. 发明申请

US20130019108A1 ADDRESS TRANSLATION UNIT, DEVICE AND METHOD FOR REMOTE DIRECT MEMORY ACCESS OF A MEMORY 有权
标题翻译：地址转换单元，用于远程存储器的直接存储器访问的设备和方法
公开(公告)号：US20130019108A1
公开(公告)日：2013-01-17
申请号：US13617942
申请日：2012-09-14
申请人： Florian A. Auernhammer , Nikolaos Chrysos , Rolf Clauberg , Andreas C. Doering , Ronald P. Luijten , Patricia M. Sagmeister
发明人： Florian A. Auernhammer , Nikolaos Chrysos , Rolf Clauberg , Andreas C. Doering , Ronald P. Luijten , Patricia M. Sagmeister
IPC分类号： G06F12/14 , G06F21/00
CPC分类号： G06F12/1081 , G06F12/1408 , H04L9/00 , H04L9/0894 , H04L9/3247 , Y02D10/13
摘要： A method for Remote Direct Memory Access (RDMA) of a memory of a processor. An address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address.
摘要翻译：一种用于处理器存储器的远程直接存储器访问（RDMA）的方法。地址转换单元包括地址转换器和签名者。地址转换器被配置为在存储器的实际地址中转换接收的虚拟地址。签名者被配置为对真实地址进行加密签名。

3. 发明授权

US08930716B2 Address translation unit, device and method for remote direct memory access of a memory 有权
标题翻译：用于存储器的远程直接存储器访问的地址转换单元，设备和方法
公开(公告)号：US08930716B2
公开(公告)日：2015-01-06
申请号：US13617942
申请日：2012-09-14
申请人： Florian A. Auernhammer , Nikolaos Chrysos , Rolf Clauberg , Andreas C. Doering , Ronald P. Luijten , Patricia M. Sagmeister
发明人： Florian A. Auernhammer , Nikolaos Chrysos , Rolf Clauberg , Andreas C. Doering , Ronald P. Luijten , Patricia M. Sagmeister
IPC分类号： G06F11/30 , G06F12/10 , H04L9/00 , H04L9/08 , H04L9/32 , G06F12/14
CPC分类号： G06F12/1081 , G06F12/1408 , H04L9/00 , H04L9/0894 , H04L9/3247 , Y02D10/13
摘要： A method for Remote Direct Memory Access (RDMA) of a memory of a processor. An address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address.
摘要翻译：一种用于处理器存储器的远程直接存储器访问（RDMA）的方法。地址转换单元包括地址转换器和签名者。地址转换器被配置为在存储器的实际地址中转换接收的虚拟地址。签名者被配置为对真实地址进行加密签名。

4. 发明申请

US20120303948A1 ADDRESS TRANSLATION UNIT, DEVICE AND METHOD FOR REMOTE DIRECT MEMORY ACCESS OF A MEMORY 有权
标题翻译：地址转换单元，用于远程存储器的直接存储器访问的设备和方法
公开(公告)号：US20120303948A1
公开(公告)日：2012-11-29
申请号：US13480979
申请日：2012-05-25
申请人： Florian A. Auernhammer , Nikolaos Chrysos , Rolf Clauberg , Andreas C. Doering , Ronald P. Luijten , Patricia M. Sagmeister
发明人： Florian A. Auernhammer , Nikolaos Chrysos , Rolf Clauberg , Andreas C. Doering , Ronald P. Luijten , Patricia M. Sagmeister
IPC分类号： G06F12/14 , G06F12/10 , H04L9/00
CPC分类号： G06F12/1081 , G06F12/1408 , H04L9/00 , H04L9/0894 , H04L9/3247 , Y02D10/13
摘要： An address translation unit for Remote Direct Memory Access (RDMA) of a memory of a processor is provided. The address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address.
摘要翻译：提供了一种用于处理器的存储器的远程直接存储器访问（RDMA）的地址转换单元。地址转换单元包括地址转换器和签名者。地址转换器被配置为在存储器的实际地址中转换接收的虚拟地址。签名者被配置为对真实地址进行加密签名。

5. 发明授权

US08995265B2 Monitoring endpoint buffer occupancy to determine congestion in an ethernet network 有权
标题翻译：监控端点缓冲区占用率以确定以太网网络中的拥塞
公开(公告)号：US08995265B2
公开(公告)日：2015-03-31
申请号：US13360679
申请日：2012-01-28
申请人： Claude Basso , Rolf Clauberg , Casimer M. DeCusatis , Mircea Gusat , Ronald P. Luijten , Fredy D. Neeser , Kenneth M. Valk
发明人： Claude Basso , Rolf Clauberg , Casimer M. DeCusatis , Mircea Gusat , Ronald P. Luijten , Fredy D. Neeser , Kenneth M. Valk
IPC分类号： H04L12/26 , H04L12/835 , H04L12/875
CPC分类号： H04L43/00 , H04L43/08 , H04L47/30 , H04L47/56
摘要： A system to improve a Converged Enhanced Ethernet network may include a controller having a computer processor connected to a layer 2 endpoint buffer. The system may also include a manager executing on the controller to monitor the layer 2 endpoint buffer by determining buffer data packet occupancy and/or rate of change in the buffer data packet occupancy. The system may further include a reporter to notify a congestion source of the layer 2 endpoint buffer based upon the buffer data packet occupancy and/or rate of change in the buffer data packet occupancy.
摘要翻译：改进融合增强以太网的系统可以包括具有连接到层2端点缓冲器的计算机处理器的控制器。系统还可以包括在控制器上执行的管理器，以通过确定缓冲器数据包占用率和/或缓冲器数据包占用率的变化率来监视第二层端点缓冲器。该系统还可以包括报告员，以基于缓冲器数据包占用率和/或缓冲器数据包占用率的变化率来通知第2层端点缓冲器的拥塞源。

6. 发明申请

US20130194923A1 CONVERGED ENHANCED ETHERNET NETWORK 有权
公开(公告)号：US20130194923A1
公开(公告)日：2013-08-01
申请号：US13360679
申请日：2012-01-28
申请人： Claude Basso , Rolf Clauberg , Casimer M. DeCusatis , Mircea Gusat , Ronald P. Luijten , Fredy D. Neeser , Kenneth M. Valk
发明人： Claude Basso , Rolf Clauberg , Casimer M. DeCusatis , Mircea Gusat , Ronald P. Luijten , Fredy D. Neeser , Kenneth M. Valk
IPC分类号： H04L12/26
CPC分类号： H04L43/00 , H04L43/08 , H04L47/30 , H04L47/56
摘要： A system to improve a Converged Enhanced Ethernet network may include a controller having a computer processor connected to a layer 2 endpoint buffer. The system may also include a manager executing on the controller to monitor the layer 2 endpoint buffer by determining buffer data packet occupancy and/or rate of change in the buffer data packet occupancy. The system may further include a reporter to notify a congestion source of the layer 2 endpoint buffer based upon the buffer data packet occupancy and/or rate of change in the buffer data packet occupancy.

7. 发明授权

US5463705A Optical waveguide isolation 失效
标题翻译：光波导隔离
公开(公告)号：US5463705A
公开(公告)日：1995-10-31
申请号：US288639
申请日：1994-08-10
申请人： Rolf Clauberg , Christoph Harder , Christan Heusch , Heinz Jaeckel
发明人： Rolf Clauberg , Christoph Harder , Christan Heusch , Heinz Jaeckel
IPC分类号： G02B6/122 , G01C19/66 , G02B6/125 , G02B6/24 , H01S3/00 , H01S3/083 , H01S5/00 , H01S5/026 , H01S5/10 , G02B6/12
CPC分类号： H01S5/1071 , G02B6/125 , G02B6/243 , H01S3/0064 , H01S5/0064 , H01S5/026 , H01S5/1032
摘要： Optical waveguide isolator (121) for monolithic integration with semiconductor light emitting diodes such as Fabry-Perot or ring laser diodes. The present optical isolator (121), with optical input port (95) and output pod (96), comprises a branching waveguide coupler (56). This branching waveguide coupler (56) has a waveguide stem (60) splitted at one end into two waveguide branches (57, 58) such that a light wave fed via said input pod (95) into a first of these branches (58), is guided via the waveguide stem (60) and the output pod (96) out of the device. A light wave fed to the isolator's output pod (96) is guided along the stem (60) and coupled into the second waveguide branch (57).
摘要翻译：用于与半导体发光二极管（例如法布里 - 珀罗）或环形激光二极管单片集成的光波导隔离器（121）。具有光输入端口（95）和输出盒（96）的本光隔离器（121）包括分支波导耦合器（56）。该分支波导耦合器（56）具有在一端分成两个波导分支（57,58）的波导管（60），使得经由所述输入容器（95）馈送到这些分支（58）中的第一个的光波，经由波导管杆（60）和输出容器（96）引导出装置。馈送到隔离器输出盒（96）的光波沿着杆（60）被引导并且耦合到第二波导支路（57）中。

8. 发明授权

US4843329A Method for contactless testing for electrical opens and short circuits in conducting paths in a substrate 失效
标题翻译：用于非接触式测试的方法，用于在基板中的导电路径中的电开路和短路
公开(公告)号：US4843329A
公开(公告)日：1989-06-27
申请号：US107433
申请日：1987-10-09
申请人： Johannes G. Beha , Armin U. Blacha , Rolf Clauberg , Hugo K. Seitz
发明人： Johannes G. Beha , Armin U. Blacha , Rolf Clauberg , Hugo K. Seitz
IPC分类号： H01L21/66 , G01N23/22 , G01R31/02 , G01R31/308 , H05K3/00
CPC分类号： G01R31/308
摘要： A method for contactlessly testing for opens and shorts in conducting paths within or on a nonconducting substrate. There are a plurality of conducting pads on the surface of the substrate. Charges are contactlessly generated, e.g., by an optical beam, in at least one selected pad inducing a voltage thereon and on pads electrically connected therewith through one of the conducting paths. A two dimensional electron flux is contactlessly caused to be emitted from the selected pad and at least one other pad of the plurality of pads, e.g., by an optical beam. The flux emitted from the pads depends on the voltage on each pad. The flux is detected to distinguish pads in electrical connection.
摘要翻译：一种用于非接触测试非导电衬底内或之上的导通路径中的开路和短路的方法。在基板的表面上有多个导电焊盘。在至少一个所选择的焊盘中，例如通过光束，通过其中一个导电路径与其电连接的焊盘上无接触地产生电荷。二维电子通量被非接触地引起，例如通过光束从所选择的焊盘和多个焊盘中的至少一个其它焊盘发射。从焊盘发射的焊剂取决于每个焊盘上的电压。检测通量以区分电连接的焊盘。

9. 发明授权

US07630414B2 Multiple low-speed into single high-speed SDH/SONET channel mapper/framer device and method 失效
标题翻译：多个低速转换为单高速SDH / SONET通道映射/成帧器的设备及方法
公开(公告)号：US07630414B2
公开(公告)日：2009-12-08
申请号：US10475367
申请日：2002-03-22
申请人： Rolf Clauberg
发明人： Rolf Clauberg
IPC分类号： H04J3/02
CPC分类号： H04J3/1611 , H04J3/0691 , H04J2203/0089
摘要： A method and a device for combining at least two data signals having a first data rate into a single data stream having a second data rate higher than the first data rate for transmission on a shared medium or vice versa. The device has at least one port for receiving at least two data signals and a port addressing unit for extracting data from the data signals received by the ports. The port addressing unit is configured to place the extracted data at predetermined positions in the single data stream to be transmitted on the shared medium and at least one control data insertion unit is provided for placing control data in the single data stream.
摘要翻译：一种用于将具有第一数据速率的至少两个数据信号组合成具有高于第一数据速率的第二数据速率以用于在共享介质上传输的单个数据流的方法和装置，反之亦然。该设备具有用于接收至少两个数据信号的至少一个端口和用于从由端口接收的数据信号中提取数据的端口寻址单元。端口寻址单元被配置为将提取的数据放置在单个数据流中的预定位置以在共享介质上发送，并且提供至少一个控制数据插入单元以将控制数据放置在单个数据流中。

10. 发明授权

US07613850B1 System and method utilizing programmable ordering relation for direct memory access 有权
标题翻译：使用可编程排序关系进行直接存储器访问的系统和方法
公开(公告)号：US07613850B1
公开(公告)日：2009-11-03
申请号：US12343092
申请日：2008-12-23
申请人： Andreas Christian Doering , Patricia Maria Sagmeister , Jonathan Bruno Rohrer , Silvio Dragone , Rolf Clauberg , Florian Alexander Auernhammer , Maria Gabrani
发明人： Andreas Christian Doering , Patricia Maria Sagmeister , Jonathan Bruno Rohrer , Silvio Dragone , Rolf Clauberg , Florian Alexander Auernhammer , Maria Gabrani
IPC分类号： G06F3/00
CPC分类号： G06F13/1621
摘要： A computer system controls ordered memory operations according to a programmatically-configured ordering class protocol to enable parallel memory access while maintaining ordered read responses. The system includes a memory and/or cache memory including a memory/cache controller, an I/O device for communicating memory access requests from system data sources and a memory controller I/O Interface. Memory access requests from the system data sources provide a respective ordering class value. The memory controller I/O Interface processes each memory access request and ordering class value communicated from a data source through the I/O device in coordination with the ordering class protocol. Preferably, the I/O device includes at least one register for storing ordering class values associated with system data sources that implement memory access requests.
摘要翻译：计算机系统根据编程配置的排序类协议来控制有序存储器操作，以在维持有序读取响应的同时启用并行存储器访问。该系统包括存储器和/或高速缓存存储器，其包括存储器/高速缓存控制器，用于从系统数据源传送存储器访问请求的I / O设备和存储器控制器I / O接口。来自系统数据源的存储器访问请求提供了相应的排序类值。存储器控制器I / O接口根据排序类协议处理从数据源通过I / O设备传送的每个存储器访问请求和排序类值。优选地，I / O设备包括至少一个用于存储与实现存储器访问请求的系统数据源相关联的排序类值的寄存器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式