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1. 发明申请

US20110231461A1 Identifier selection 有权
标题翻译：标识符选择
公开(公告)号：US20110231461A1
公开(公告)日：2011-09-22
申请号：US12659669
申请日：2010-03-16
申请人： John Michael Horley , Andrew Brookfield Swaine , Michael John Williams
发明人： John Michael Horley , Andrew Brookfield Swaine , Michael John Williams
IPC分类号： G06F7/00
CPC分类号： G06F7/02 , G06F7/76 , G06F7/764
摘要： A data processing apparatus is provided which is configured to select 2M selected identifiers within a possible range of up to 2N identifiers, where M≦N. The data processing apparatus comprises a selection storage unit configured to store N+1 identifier selection bits, wherein a position of a marker bit in the N+1 identifier selection bits determines M, and an identifier selection unit configured to determine the 2M selected identifiers. The 2M selected identifiers are defined by a base identifier and 2M−1 identifiers incrementally following that base identifier. N−M bits of the N+1 identifier selection bits form N−M most significant bits of the base identifier, and M trailing zeroes form the M least significant bits of the base identifier.
摘要翻译：提供了一种数据处理装置，其被配置为在最多2N个标识符的可能范围内选择2M个选择的标识符，其中M＆N; E; N。所述数据处理装置包括：选择存储单元，被配置为存储N + 1个标识符选择位，其中，所述N + 1个标识符选择位中的标记位的位置确定M;以及标识符选择单元，被配置为确定所述2M个选择的标识符。 2M个选择的标识符由基本标识符和逐渐跟随该基本标识符的2M-1个标识符定义。 N + 1标识符选择位的N-M位形成基本标识符的N-M个最高有效位，并且M个尾随零构成基本标识符的M个最低有效位。

2. 发明授权

US08407529B2 Trace synchronization 有权
标题翻译：跟踪同步
公开(公告)号：US08407529B2
公开(公告)日：2013-03-26
申请号：US13339937
申请日：2011-12-29
申请人： John Michael Horley , Andrew Brookfield Swaine , Thomas Sean Houlihane , Sheldon James Woodhouse , Michael John Williams
发明人： John Michael Horley , Andrew Brookfield Swaine , Thomas Sean Houlihane , Sheldon James Woodhouse , Michael John Williams
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/348 , G06F11/3632 , G06F11/3648
摘要： A data processing apparatus having one or more trace data sources. At least one of said trace data sources includes a trace data generator responsive to activity in monitored circuitry to generate trace data representing said activity. A synchronization marker generator is coupled to the trace data generator and operates to generate a synchronization marker and insert the synchronization marker into the trace data stream. A controller is coupled to the synchronization marker generator to generate and insert a synchronization marker into the trace data stream. The controller controls initiation in dependence on behavior of the data processing apparatus downstream of the trace data generator. In this way, the downstream behavior of the data processing apparatus can be made to influence the rate and timing of insertion of synchronization markers into a trace data stream.
摘要翻译：具有一个或多个跟踪数据源的数据处理装置。所述跟踪数据源中的至少一个包括跟踪数据发生器，其响应于所监视的电路中的活动以产生表示所述活动的跟踪数据。同步标记生成器耦合到跟踪数据生成器，并且操作以产生同步标记并将同步标记插入到跟踪数据流中。控制器耦合到同步标记发生器以产生并将同步标记插入到跟踪数据流中。控制器根据跟踪数据生成器下游的数据处理设备的行为来控制启动。以这种方式，可以使数据处理装置的下行行为影响将同步标记插入到跟踪数据流中的速率和时间。

3. 发明申请

US20120030499A1 Distribution of an incrementing count value 有权
标题翻译：分配增量计数值
公开(公告)号：US20120030499A1
公开(公告)日：2012-02-02
申请号：US13067818
申请日：2011-06-28
申请人： Andrew Brookfield Swaine
发明人： Andrew Brookfield Swaine
IPC分类号： G06F1/04
CPC分类号： G06F1/14
摘要： Circuitry is disclosed that comprises: at least one element located within the circuitry and configured to hold an increasing count value; an encoder for receiving the increasing count value from a source of the increasing count value and configured to encode the increasing count value into encoded values, the encoded values each indicating an exponential amount to be applied to the count value held in the at least one element; interconnect circuitry for receiving the encoded value and transmitting the encoded value to the at least one element; wherein the at least one element comprises a decoder for decoding the encoded values and for increasing the count value in dependence upon the exponential amount.
摘要翻译：公开了一种电路，包括：位于电路内的至少一个元件，并配置成保持增加的计数值; 编码器，用于从增加的计数值的源接收增加的计数值，并且被配置为将增加的计数值编码为编码值，每个编码值指示要应用于保持在至少一个元件中的计数值的指数量 ; 互连电路，用于接收编码值并将编码值发送到至少一个元件; 其中所述至少一个元件包括用于对编码值进行解码并根据指数量来增加计数值的解码器。

4. 发明申请

US20090313507A1 Generation of trace data in a multi-processor system 有权
标题翻译：在多处理器系统中生成跟踪数据
公开(公告)号：US20090313507A1
公开(公告)日：2009-12-17
申请号：US12155926
申请日：2008-06-11
申请人： Andrew Brookfield Swaine , Michael John Williams , David Kevin Hart , Andrew Christopher Rose
发明人： Andrew Brookfield Swaine , Michael John Williams , David Kevin Hart , Andrew Christopher Rose
IPC分类号： G06F11/34
CPC分类号： G06F11/348 , G06F11/3636
摘要： A data processing apparatus is provided having a plurality of processing circuits each having access to a memory. Tracing circuitry is provided for generating a stream of trace data for generating a stream of trace data corresponding to at least one of the plurality of processing circuits. Selection circuitry is provided to enable selective switching of the tracing circuitry from generating a first trace data stream corresponding to a first one of the plurality of processing circuits generating a second different trace data stream corresponding to a different one of the plurality of processing circuits. The selective switching is performed in dependence upon processing state information associating with one or more of the plurality of processing circuits. A corresponding method and computer program product are also provided.
摘要翻译：提供了一种数据处理装置，其具有各自具有访问存储器的多个处理电路。跟踪电路被提供用于产生跟踪数据流，用于产生对应于多个处理电路中的至少一个的跟踪数据流。提供选择电路以使得跟踪电路的选择性切换不产生与多个处理电路中的第一个处理电路相对应的第一跟踪数据流，从而生成对应于多个处理电路中的不同处理电路的第二不同跟踪数据流。根据与多个处理电路中的一个或多个相关联的处理状态信息执行选择性切换。还提供了相应的方法和计算机程序产品。

5. 发明申请

US20090193297A1 Diagnostic context construction and comparison 有权
标题翻译：诊断情境建设与比较
公开(公告)号：US20090193297A1
公开(公告)日：2009-07-30
申请号：US12318442
申请日：2008-12-30
申请人： Michael John Williams , Richard Roy Grisenthwaite , Andrew Brookfield Swaine , John Michael Horley
发明人： Michael John Williams , Richard Roy Grisenthwaite , Andrew Brookfield Swaine , John Michael Horley
IPC分类号： G06F11/28
CPC分类号： G06F11/3636
摘要： A data processing system 1 has a processor core 2 which is programmable to act as one of a plurality of virtual machines each identified by a virtual machine identifier, each virtual machine acting in one of a plurality of contexts each identified by a context identifier, each context executing a sequence of program instructions, each program instruction having one or more associated memory addresses. The data processing system has diagnostic circuitry 10 for performing diagnostic operations on the processor core. Diagnostic control circuitry 12 is provided which is responsive to current values of the virtual machine identifier, the context identifier and at least one of the one or more associated memory addresses to trigger the diagnostic circuitry 10 to perform diagnostic operations.
摘要翻译：数据处理系统1具有处理器核心2，其可编程以充当多个虚拟机中的一个，每个虚拟机由虚拟机标识符标识，每个虚拟机以每个由上下文标识符标识的多个上下文之一起作用，上下文执行程序指令序列，每个程序指令具有一个或多个关联的存储器地址。数据处理系统具有用于在处理器核上进行诊断操作的诊断电路10。提供了诊断控制电路12，其响应虚拟机标识符，上下文标识符的当前值和一个或多个相关联的存储器地址中的至少一个来触发诊断电路10执行诊断操作。

6. 发明授权

US07228457B2 Performing diagnostic operations upon a data processing apparatus with power down support 有权
标题翻译：对具有断电支持的数据处理设备执行诊断操作
公开(公告)号：US07228457B2
公开(公告)日：2007-06-05
申请号：US10801131
申请日：2004-03-16
申请人： Conrado Blasco Allue , Paul Kimelman , Andrew Brookfield Swaine , Richard Roy Grisenthwaite
发明人： Conrado Blasco Allue , Paul Kimelman , Andrew Brookfield Swaine , Richard Roy Grisenthwaite
IPC分类号： G06F11/00
CPC分类号： G06F11/2236
摘要： A system-on-chip integrated circuit 2 is provided with multiple data processing circuits 4, 6, 8 each with an associated diagnostic interface circuit 16, 18, 20 connected via a diagnostic transaction bus 14 to a diagnostic transaction master circuit 12. The diagnostic master transaction circuit 12 issues diagnostic transaction requests to the diagnostic interface circuits 16, 18, 20. If the associated data processing circuits 4, 6, 8 are powered-down, or otherwise non responsive, then the diagnostic interface circuit 16, 18, 20 returns a diagnostic bus transaction error signal to the diagnostic transaction master circuit 12. A sticky-bit latch 30 within each diagnostic interface circuit 16, 18, 20 serves to record a power-down event and force generation of the diagnostic bus transaction error signal until that sticky bit is cleared by the diagnostic mechanisms. This ensure the diagnostic mechanisms are made aware of the power-down event so they may take any appropriate remedial action that might be necessary as a result of that power-down event.
摘要翻译：系统级芯片集成电路2具有多个数据处理电路4,6,8，每个数据处理电路具有通过诊断事务总线14连接到诊断事务主电路12的相关联的诊断接口电路16,18,20。诊断主交易电路12向诊断接口电路16,18,20发出诊断事务请求。如果相关联的数据处理电路4,6,8被断电或以其他方式不响应，则诊断接口电路16,18,20将诊断总线事务错误信号返回给诊断事务主电路12。每个诊断接口电路16,18,20内的粘滞锁存器30用于记录诊断总线事务错误信号的掉电事件和强制产生，直到诊断机构清除该粘滞位。这样可以确保诊断机制能够意识到掉电事件，因此可能会由于断电事件而采取任何必要的补救措施。

7. 发明授权

US07191293B2 Recovering pending trace data within a data processing system 有权
标题翻译：恢复数据处理系统中的待处理跟踪数据
公开(公告)号：US07191293B2
公开(公告)日：2007-03-13
申请号：US10801137
申请日：2004-03-16
申请人： Daryl Wayne Bradley , Andrew Brookfield Swaine , Sheldon James Woodhouse , John Michael Horley
发明人： Daryl Wayne Bradley , Andrew Brookfield Swaine , Sheldon James Woodhouse , John Michael Horley
IPC分类号： G06F12/06 , G06F9/44
CPC分类号： G06F11/3476
摘要： A trace data system is provided in which flush request signals are generated and passed to trace data sources to trigger them to output any buffered trace data they are storing which was generated prior to the flush request being signalled. When the trace data has been flushed from these trace data sources, they signal this by generating a flush complete signal. The flushing of trace data may advantageously be performed prior to a power-down operation and using a trace bus bridge.
摘要翻译：提供跟踪数据系统，其中生成刷新请求信号并将其传递到跟踪数据源，以触发它们输出它们正在存储的任何缓冲的跟踪数据，该数据是在发送刷新请求之前生成的。当跟踪数据从这些跟踪数据源中刷新时，它们会通过生成一个完整的完成信号来发出信号。跟踪数据的刷新可以有利地在掉电操作之前和使用跟踪总线桥处执行。

8. 发明授权

US07134117B2 Instruction tracing in data processing systems 有权
标题翻译：数据处理系统中的指令跟踪
公开(公告)号：US07134117B2
公开(公告)日：2006-11-07
申请号：US10352030
申请日：2003-01-28
申请人： Andrew Brookfield Swaine
发明人： Andrew Brookfield Swaine
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F11/348 , G06F11/25 , G06F11/28 , G06F11/3476 , G06F11/3636
摘要： A tracing circuit 8 within an apparatus for data processing 2 generates trace data including instruction trace words encoding trace events W, E, N representing program instruction execution. The instruction trace words have a predetermined length and each represent a sequence of trace events corresponding to a combination of execution of one or more program instructions combined with one or more trace events that are other than execution of a program instruction word. Particular examples are a sequence of executed program instructions terminated by a program instruction that fails its condition codes or a sequence of wait processing cycles terminated by a program instruction that executes.
摘要翻译：用于数据处理的装置2内的跟踪电路8生成跟踪数据，其中包括编码表示程序指令执行的跟踪事件W，E，N的指令跟踪字。指令跟踪字具有预定的长度，并且每个代表对应于与除了执行程序指令字之外的一个或多个跟踪事件组合的一个或多个程序指令的执行的组合的跟踪事件序列。特定示例是由程序指令终止的执行程序指令的序列，其失败其条件代码或由执行的程序指令终止的等待处理循环的序列。

9. 发明授权

US07020768B2 Apparatus and method for facilitating debugging of sequences of processing instructions using context identifier comparison 有权
标题翻译：使用上下文标识符比较便利调试处理指令序列的装置和方法
公开(公告)号：US07020768B2
公开(公告)日：2006-03-28
申请号：US09792643
申请日：2001-02-26
申请人： Andrew Brookfield Swaine , Conrado Blasco Allué , Ian Victor Devereux , David James Williamson , Anthony Neil Berent
发明人： Andrew Brookfield Swaine , Conrado Blasco Allué , Ian Victor Devereux , David James Williamson , Anthony Neil Berent
IPC分类号： G06F9/44 , G06F11/36
CPC分类号： G06F9/3824 , G06F9/3802 , G06F11/3466 , G06F11/3636
摘要： The present invention provides an apparatus and method for facilitating debugging of sequences of processing instructions. The apparatus comprises a processing circuit for executing processing instructions, the processing circuit having multiple states of operation, with each state of operation being assigned a context identifier to identify the state of operation. Further, logic is provided for facilitating debugging of sequences of processing instructions executed by the processing circuit. The logic comprises control logic, responsive to control parameters, to perform predetermined actions to facilitate debugging, and triggering logic for generating the control parameters dependent on data received from the processing circuit indicative of the processing being performed by the processing circuit. The triggering logic comprises at least one context identifier comparator for comparing a context identifier provided within the data received from the processing circuit with a predetermined context identifier, and to generate a signal indicating whether that context identifier matches the predetermined context identifier. By this approach, the present invention enables a data processing apparatus to be provided with tracing mechanisms and/or debugging mechanisms which can reliably operate even in situations where the sequences of processing instructions from different states of operation occupy overlapping regions in the memory's address space.
摘要翻译：本发明提供了一种便于调试处理指令序列的装置和方法。该装置包括用于执行处理指令的处理电路，该处理电路具有多个操作状态，每个操作状态被分配上下文标识符以识别操作状态。此外，提供逻辑以便于调试由处理电路执行的处理指令的序列。逻辑包括响应于控制参数的控制逻辑，以执行预定的动作以便于调试，以及触发用于根据从处理电路接收的指示由处理电路执行的处理的数据产生控制参数的逻辑。触发逻辑包括至少一个上下文标识符比较器，用于将从处理电路接收的数据中提供的上下文标识符与预定上下文标识符进行比较，并产生指示该上下文标识符是否匹配预定上下文标识符的信号。通过这种方法，本发明使数据处理装置能够提供跟踪机制和/或调试机制，即使在来自不同操作状态的处理指令的序列占据存储器地址空间中的重叠区域的情况下也可以可靠地运行。

10. 发明授权

US08966309B2 Distribution of an incrementing count value 有权
标题翻译：分配增量计数值
公开(公告)号：US08966309B2
公开(公告)日：2015-02-24
申请号：US13067818
申请日：2011-06-28
申请人： Andrew Brookfield Swaine
发明人： Andrew Brookfield Swaine
IPC分类号： H04L12/56 , G06F1/14
CPC分类号： G06F1/14
摘要： Circuitry is disclosed that comprises: at least one element located within the circuitry and configured to hold an increasing count value; an encoder for receiving the increasing count value from a source of the increasing count value and configured to encode the increasing count value into encoded values, the encoded values each indicating an exponential amount to be applied to the count value held in the at least one element; interconnect circuitry for receiving the encoded value and transmitting the encoded value to the at least one element; wherein the at least one element comprises a decoder for decoding the encoded values and for increasing the count value in dependence upon the exponential amount.
摘要翻译：公开了一种电路，包括：位于电路内的至少一个元件，并配置成保持增加的计数值; 编码器，用于从增加的计数值的源接收增加的计数值，并且被配置为将增加的计数值编码为编码值，每个编码值指示要应用于保持在至少一个元件中的计数值的指数量 ; 互连电路，用于接收编码值并将编码值发送到至少一个元件; 其中所述至少一个元件包括用于对编码值进行解码并根据指数量来增加计数值的解码器。

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