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1. 发明授权

US08386754B2 Renaming wide register source operand with plural short register source operands for select instructions to detect dependency fast with existing mechanism 有权
标题翻译：重新命名宽的寄存器源操作数，具有多个短寄存器源操作数，用于使用现有机制快速检测依赖关系的选择指令
公开(公告)号：US08386754B2
公开(公告)日：2013-02-26
申请号：US12457905
申请日：2009-06-24
申请人： Conrado Blasco Allue , David James Williamson , James Nolan Hardage , Glen Andrew Harris , Robert Gregory McDonald
发明人： Conrado Blasco Allue , David James Williamson , James Nolan Hardage , Glen Andrew Harris , Robert Gregory McDonald
IPC分类号： G06F9/38
CPC分类号： G06F9/30112 , G06F9/3017 , G06F9/3836 , G06F9/384
摘要： An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register of a double precision size may alias with two single precision registers being used as destinations of one or more preceding program instructions. In order to track this data dependency the double precision register may be remapped into a micro-operation specifying two single precision registers as its source register. In this way, scheduling circuitry may use its existing hazard detection and management mechanisms to handle potential data hazards and dependencies. Not all program instructions having such data hazards between registers of different sizes are handled by this source register remapping. For these other program instructions a slower mechanism for dealing with the data dependency hazard is provided. This slower mechanism may, for example, be to drain all the preceding micro-operations from the execution pipelines before issuing the micro-operation having the data hazard.
摘要翻译：无序重命名处理器具有寄存器文件，在该寄存器文件中可能发生不同大小的寄存器之间的混叠。以这种方式，具有双精度尺寸的源寄存器的程序指令可以使用两个单精度寄存器作为一个或多个先前程序指令的目的地。为了跟踪这种数据依赖关系，双精度寄存器可以重新映射成指定两个单精度寄存器作为其源寄存器的微操作。以这种方式，调度电路可以使用其现有的危险检测和管理机制来处理潜在的数据危害和依赖性。并不是所有具有不同大小的寄存器之间的数据危害的程序指令都由该源寄存器重新映射来处理。对于这些其他程序指令，提供了一种用于处理数据依赖性危害的较慢机制。例如，这种较慢的机制可以在发出具有数据危险的微操作之前从执行管线中排出所有先前的微操作。

2. 发明申请

US20120124346A1 Decoding conditional program instructions 审中-公开
标题翻译：解码条件程序指令
公开(公告)号：US20120124346A1
公开(公告)日：2012-05-17
申请号：US12926395
申请日：2010-11-15
申请人： James Nolan Hardage , Conrado Blasco Allue , Glen Andrew Harris , David James Williamson
发明人： James Nolan Hardage , Conrado Blasco Allue , Glen Andrew Harris , David James Williamson
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/30072 , G06F9/30145 , G06F9/3017 , G06F9/3842 , G06F9/3887
摘要： A processor 2 includes instruction decoding circuitry 8 and processing circuitry 16, 18, 20, 22, 24. The instruction decoding circuitry decodes at least one conditional program instruction in accordance with a conditional prediction as one of, in accordance with the condition prediction being a condition pass, one or more micro-operation instructions that control the processing circuitry to perform the processing action together with a condition resolution micro-operation instruction, or in accordance with the condition prediction being a condition fail, at least a condition resolution micro-operation instruction. Condition resolution circuitry 24 responds to the condition resolution micro-operation instruction to determine if the condition prediction is incorrect. If the condition prediction is incorrect, then the condition resolution circuitry flushes any micro-operation instructions associated with the conditional program instruction from the processing circuitry, changes the condition prediction to a new prediction and triggers the redecoding of the conditional program instruction in accordance with the new condition prediction.
摘要翻译：处理器2包括指令解码电路8和处理电路16,18,20,22,24 24.指令解码电路根据条件预测将至少一个条件程序指令解码为根据条件预测为条件通过，一个或多个微操作指令，其控制处理电路与条件分辨率微操作指令一起执行处理动作，或者根据状态预测是条件失败，至少条件分辨率微操作指令。条件解析电路24响应条件分辨率微操作指令以确定条件预测是否不正确。如果条件预测不正确，则条件分辨率电路从处理电路刷新与条件程序指令相关联的任何微操作指令，将条件预测改变为新的预测，并根据该条件程序指令触发重新编码条件程序指令新条件预测。

3. 发明授权

US07496899B2 Preventing loss of traced information in a data processing apparatus 有权
标题翻译：防止在数据处理设备中丢失跟踪信息
公开(公告)号：US07496899B2
公开(公告)日：2009-02-24
申请号：US11205310
申请日：2005-08-17
申请人： Stephen John Hill , Glen Andrew Harris , David James Williamson
发明人： Stephen John Hill , Glen Andrew Harris , David James Williamson
IPC分类号： G06F9/44 , G06F9/00
CPC分类号： G06F9/3836 , G06F9/30145 , G06F9/3838 , G06F9/3857 , G06F11/3636 , G06F11/3656
摘要： Techniques for preventing the loss of trace information being transmitted via trace infrastructure are disclosed. A data processing apparatus for processing instructions is provided. The data processing apparatus comprises: decode/issue logic operable to receive and decode an instruction to be processed by the data processing apparatus and to determine when to issue a decoded instructions for execution by execution logic; execution logic operable to execute the decoded instructions; interface logic selectively operable to receive trace information relating to the state of the data processing apparatus generated in response to execution of the decoded instructions for transmission to trace monitoring infrastructure; and throttle logic operable to predict whether issuing the decoded instruction to the execution logic for execution would be likely to cause the trace information to be transmitted to said trace monitoring infrastructure to exceed a capacity of said trace monitoring infrastructure and, if so, to prevent the decode/issue logic from issuing the decoded instruction to the execution logic. Accordingly, the throttle logic reviews each instruction to be executed and predicts whether issuing that instruction at that time will or is likely to cause the capacity to be exceeded. In the event that the throttle logic determines that the capacity is likely to be exceeded, the instruction is prevented from being issued to the execution logic which reduces the likelihood that any state information is lost.
摘要翻译：公开了用于防止通过迹线基础设施传输的跟踪信息丢失的技术。提供了一种处理指令的数据处理装置。数据处理装置包括：解码/发布逻辑，可操作以接收和解码由数据处理装置处理的指令，并确定何时发出经执行逻辑执行的解码指令; 执行逻辑，用于执行解码指令; 接口逻辑选择性地可操作以接收与响应于解码指令的执行而生成的数据处理设备的状态相关的跟踪信息，以便传输到跟踪监视基础设施; 并且可操作以用于预测是否向执行逻辑发出解码指令以进行执行的油门逻辑可能导致跟踪信息被发送到所述跟踪监视基础设施以超过所述跟踪监视基础设施的容量，如果是，则阻止解码/发布逻辑从解码指令发出到执行逻辑。因此，节气门逻辑检查要执行的每个指令，并且预测当时是否发出该指令将或可能导致超过容量。在节气门逻辑确定容量可能被超过的情况下，防止指令被发送到执行逻辑，这减少了任何状态信息丢失的可能性。

4. 发明授权

US07389459B2 Provision of debug via a separate ring bus in a data processing apparatus 有权
标题翻译：通过数据处理设备中的单独的环形总线提供调试
公开(公告)号：US07389459B2
公开(公告)日：2008-06-17
申请号：US11085598
申请日：2005-03-22
申请人： Conrado Blasco Allue , Stephen John Hill , David James Williamson
发明人： Conrado Blasco Allue , Stephen John Hill , David James Williamson
IPC分类号： G01R31/28 , G11C29/00 , G11C7/00
CPC分类号： G06F11/2242 , G01R31/31705 , G01R31/31722 , G01R31/31723 , G11C29/08 , G11C29/16 , G11C2029/0401
摘要： A data processing apparatus is provided having a plurality of functional units. At least one of the functional units is operable to perform data processing operations and at least a subset of the plurality of functional units have at least one of a respective co-processor register for storing configuration data and a respective debug register for storing debug data. A debug controller outputs debug data and co-ordinates debug operations. A configuration ring-bus provides a ring path for communication of configuration instructions between a first ring sequence of the plurality of functional units and a debug ring-bus provides a ring path for communication of the debug data between a second ring sequence of the plurality of functional units. Separate provision of the debug ring-bus and the configuration ring-bus provides independent access to the co-processor register and to the debug register.
摘要翻译：提供具有多个功能单元的数据处理装置。功能单元中的至少一个可操作以执行数据处理操作，并且多个功能单元的至少一个子集具有用于存储配置数据的相应协处理器寄存器和用于存储调试数据的相应调试寄存器中的至少一个。调试控制器输出调试数据并协调调试操作。配置环总线提供用于在多个功能单元的第一环序列之间进行配置指令的通信的环路径，并且调试环总线提供用于在多个功能单元的第二环序列之间的调试数据的通信的环路功能单位。调试环总线和配置环总线的单独提供可以独立访问协处理器寄存器和调试寄存器。

5. 发明申请

US20100332805A1 Remapping source Registers to aid instruction scheduling within a processor 有权
标题翻译：重映射源寄存器以帮助处理器内的指令调度
公开(公告)号：US20100332805A1
公开(公告)日：2010-12-30
申请号：US12457905
申请日：2009-06-24
申请人： Conrado Blasco Allue , David James Williamson , James Nolan Hardage , Glen Andrew Harris , Robert Gregory McDonald
发明人： Conrado Blasco Allue , David James Williamson , James Nolan Hardage , Glen Andrew Harris , Robert Gregory McDonald
IPC分类号： G06F9/30
CPC分类号： G06F9/30112 , G06F9/3017 , G06F9/3836 , G06F9/384
摘要： An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register of a double precision size may alias with two single precision registers being used as destinations of one or more preceding program instructions. In order to track this data dependency the double precision register may be remapped into a micro-operation specifying two single precision registers as its source register. In this way, scheduling circuitry may use its existing hazard detection and management mechanisms to handle potential data hazards and dependencies. Not all program instructions having such data hazards between registers of different sizes are handled by this source register remapping. For these other program instructions a slower mechanism for dealing with the data dependency hazard is provided. This slower mechanism may, for example, be to drain all the preceding micro-operations from the execution pipelines before issuing the micro-operation having the data hazard.
摘要翻译：无序重命名处理器具有寄存器文件，在该寄存器文件中可能发生不同大小的寄存器之间的混叠。以这种方式，具有双精度尺寸的源寄存器的程序指令可以使用两个单精度寄存器作为一个或多个先前程序指令的目的地。为了跟踪这种数据依赖关系，双精度寄存器可以重新映射成指定两个单精度寄存器作为其源寄存器的微操作。以这种方式，调度电路可以使用其现有的危险检测和管理机制来处理潜在的数据危害和依赖性。并不是所有具有不同大小的寄存器之间的数据危害的程序指令都由该源寄存器重新映射来处理。对于这些其他程序指令，提供了一种用于处理数据依赖性危害的较慢机制。例如，这种较慢的机制可能在发出具有数据危险的微操作之前从执行管线中排出所有先前的微操作。

6. 发明授权

US07343481B2 Branch prediction in a data processing system utilizing a cache of previous static predictions 有权
标题翻译：利用先前静态预测的缓存的数据处理系统中的分支预测
公开(公告)号：US07343481B2
公开(公告)日：2008-03-11
申请号：US10391186
申请日：2003-03-19
申请人： David James Williamson
发明人： David James Williamson
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/3846
摘要： A data processing system incorporates an instruction prefetch unit 8 including a static branch predictor 12. A static branch prediction cache 30, 32, 34 is provided for storing a most recently encountered static branch prediction such that a subsequent request to fetch the already encountered branch instruction can be identified before the opcode for that branch instruction is returned. The cached static branch prediction can thus redirect the prefetching to the branch target address sooner than the static predictor 12.
摘要翻译：数据处理系统包括包括静态分支预测器12的指令预取单元8。提供静态分支预测高速缓存30,32,34，用于存储最近遇到的静态分支预测，使得可以在返回所述分支指令的操作码之前识别提取已经遇到的分支指令的后续请求。因此，缓存的静态分支预测可以比静态预测器12更早地将预取重定向到分支目标地址。

7. 发明授权

US07093236B2 Tracing out-of-order data 有权
标题翻译：跟踪乱序数据
公开(公告)号：US07093236B2
公开(公告)日：2006-08-15
申请号：US09773387
申请日：2001-02-01
申请人： Andrew Brookfield Swaine , David James Williamson , Paul Robert Gotch
发明人： Andrew Brookfield Swaine , David James Williamson , Paul Robert Gotch
IPC分类号： G06F9/44 , G06F11/00
CPC分类号： G06F9/3824 , G06F9/3802 , G06F11/3466 , G06F11/3636
摘要： An integrated circuit is provided with a tracing mechanism that is responsive to data access misses to insert a data place holder within a stream of trace data. When the missed data is later returned, this is inserted into the stream of traced data as a later data value. Analysis of the stream trace data may subsequently correlate between instructions that gave rise to data misses and the late data that was subsequently returned.
摘要翻译：集成电路设置有跟踪机制，其响应于数据访问未命中以将数据占位符插入到跟踪数据流内。当稍后返回丢失数据时，将其作为稍后的数据值插入跟踪数据流中。流跟踪数据的分析随后可能导致引起数据丢失的指令和随后返回的后期数据之间相关。

8. 发明申请

US20110016338A1 Storage of system configuration data on a processor 有权
标题翻译：将系统配置数据存储在处理器上
公开(公告)号：US20110016338A1
公开(公告)日：2011-01-20
申请号：US12458560
申请日：2009-07-15
申请人： David James Williamson , James Nolan Hardage
发明人： David James Williamson , James Nolan Hardage
IPC分类号： G06F9/30 , G06F1/32
CPC分类号： G06F9/30116 , G06F9/30087 , G06F9/3013 , G06F9/3861 , G06F9/3891
摘要： A processor is disclosed having a plurality of general purpose registers for storing data for processing by the processor; a set of system configuration registers for storing data indicative of a current configuration of the processor; the system configuration registers being located together in a register file; and at least some of the set of system configuration registers having a shadow register for storing a duplicate value remote from the register file, the shadow register being located close to a component that the shadow register stores a configuration value for.
摘要翻译：公开了一种具有多个通用寄存器的处理器，用于存储由处理器处理的数据; 一组系统配置寄存器，用于存储指示处理器的当前配置的数据; 系统配置寄存器一起位于寄存器文件中; 并且所述一组系统配置寄存器中的至少一些具有用于存储远离寄存器文件的重复值的影子寄存器，所述影子寄存器位于靠近所述影子寄存器存储配置值的组件。

9. 发明申请

US20100325358A1 Data storage protocols to determine items stored and items overwritten in linked data stores 有权
标题翻译：用于确定存储的项目的数据存储协议和链接数据存储中覆盖的项目
公开(公告)号：US20100325358A1
公开(公告)日：2010-12-23
申请号：US12457812
申请日：2009-06-22
申请人： Paul Gilbert Meyer , David James Williamson , Simon John Craske
发明人： Paul Gilbert Meyer , David James Williamson , Simon John Craske
IPC分类号： G06F12/08 , G06F12/00 , G06F12/10
CPC分类号： G06F12/1027 , G06F12/1054 , G06F2212/682
摘要： A storage apparatus and method for storing a plurality of items is disclosed. The storage apparatus is configured to receive a first access request and a second access request for accessing respective items in a same clock cycle. The storage apparatus comprises: two stores each for storing a subset of the plurality of items, the first access request being routed to a first store and said second access request to a second store; miss detecting circuitry for detecting a miss where a requested item is not stored in the accessed store; item retrieving circuitry for retrieving an item whose access generated a miss from a further store; updating circuitry for selecting an item to overwrite in a respective one of the two stores in dependence upon an access history of the respective store, the updating circuitry being responsive to the miss detecting circuitry detecting the miss in an access to the first store and to at least one further condition to update both of the two stores with the item retrieved from the further store by overwriting the selected items.
摘要翻译：公开了一种用于存储多个物品的存储装置和方法。存储装置被配置为接收在相同时钟周期中访问各个项目的第一访问请求和第二访问请求。存储装置包括：两个存储器，每个存储器用于存储多个项目的子集，第一访问请求被路由到第一存储器，并且所述第二访问请求传送到第二存储器; 用于检测未请求的未检测电路，其中所请求的项目不存储在所访问的存储器中; 项目检索电路，用于检索其访问从另一商店中产生未命中的项目; 更新电路，用于根据相应存储器的访问历史来选择要在两个存储器中的相应一个存储器中重写的项目，所述更新电路响应于所述未检测电路检测到对所述第一存储器的访问中的遗漏并且处于至少一个进一步的条件是通过覆盖所选择的项目来更新从另外的商店检索的商品的两个商店。

10. 发明授权

US07020768B2 Apparatus and method for facilitating debugging of sequences of processing instructions using context identifier comparison 有权
标题翻译：使用上下文标识符比较便利调试处理指令序列的装置和方法
公开(公告)号：US07020768B2
公开(公告)日：2006-03-28
申请号：US09792643
申请日：2001-02-26
申请人： Andrew Brookfield Swaine , Conrado Blasco Allué , Ian Victor Devereux , David James Williamson , Anthony Neil Berent
发明人： Andrew Brookfield Swaine , Conrado Blasco Allué , Ian Victor Devereux , David James Williamson , Anthony Neil Berent
IPC分类号： G06F9/44 , G06F11/36
CPC分类号： G06F9/3824 , G06F9/3802 , G06F11/3466 , G06F11/3636
摘要： The present invention provides an apparatus and method for facilitating debugging of sequences of processing instructions. The apparatus comprises a processing circuit for executing processing instructions, the processing circuit having multiple states of operation, with each state of operation being assigned a context identifier to identify the state of operation. Further, logic is provided for facilitating debugging of sequences of processing instructions executed by the processing circuit. The logic comprises control logic, responsive to control parameters, to perform predetermined actions to facilitate debugging, and triggering logic for generating the control parameters dependent on data received from the processing circuit indicative of the processing being performed by the processing circuit. The triggering logic comprises at least one context identifier comparator for comparing a context identifier provided within the data received from the processing circuit with a predetermined context identifier, and to generate a signal indicating whether that context identifier matches the predetermined context identifier. By this approach, the present invention enables a data processing apparatus to be provided with tracing mechanisms and/or debugging mechanisms which can reliably operate even in situations where the sequences of processing instructions from different states of operation occupy overlapping regions in the memory's address space.
摘要翻译：本发明提供了一种便于调试处理指令序列的装置和方法。该装置包括用于执行处理指令的处理电路，该处理电路具有多个操作状态，每个操作状态被分配上下文标识符以识别操作状态。此外，提供逻辑以便于调试由处理电路执行的处理指令的序列。逻辑包括响应于控制参数的控制逻辑，以执行预定的动作以便于调试，以及触发用于根据从处理电路接收的指示由处理电路执行的处理的数据产生控制参数的逻辑。触发逻辑包括至少一个上下文标识符比较器，用于将从处理电路接收的数据中提供的上下文标识符与预定上下文标识符进行比较，并产生指示该上下文标识符是否匹配预定上下文标识符的信号。通过这种方法，本发明使数据处理装置能够提供跟踪机制和/或调试机制，即使在来自不同操作状态的处理指令的序列占据存储器地址空间中的重叠区域的情况下也可以可靠地运行。

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