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1. 发明授权

US08166217B2 System and method for reading and writing data using storage controllers 有权
标题翻译：使用存储控制器读取和写入数据的系统和方法
公开(公告)号：US08166217B2
公开(公告)日：2012-04-24
申请号：US10878803
申请日：2004-06-28
申请人： Theodore C. White , William W. Dennin , Angel G. Perozo
发明人： Theodore C. White , William W. Dennin , Angel G. Perozo
IPC分类号： G06F3/00 , G06F13/12 , G06F13/14 , H03M1/22 , H03M7/00 , H03M9/00 , H04L12/50
CPC分类号： G06F3/0661 , G06F3/0607 , G06F3/0685
摘要： A controller for interfacing a host and storage device is provided. The controller includes a channel that can receive data from the storage device in a first format and store the data in an intermediate buffer memory in a second format. The channel includes conversion logic that converts data from the first format to the second format and from the second format to the first format depending upon whether data is being read or written from the buffer memory. The conversion logic uses a shuttle register and shuttle counter for aligning data that is being transferred between the storage device and the buffer memory by appropriately concatenating data to meet the first and second format requirements. The first format is based on 10-bit symbols and the second format is based on 8-bits.
摘要翻译：提供了用于连接主机和存储设备的控制器。控制器包括可以以第一格式从存储设备接收数据并以第二格式将数据存储在中间缓冲存储器中的通道。该通道包括转换逻辑，其根据数据是从缓冲存储器读取还是从缓冲存储器写入，将数据从第一格式转换为第二格式，从第二格式转换为第一格式。转换逻辑使用梭式寄存器和穿梭计数器，通过适当连接数据来对准在存储设备和缓冲存储器之间传输的数据，以满足第一和第二格式要求。第一种格式基于10位符号，第二种格式基于8位。

2. 发明授权

US07007114B1 System and method for padding data blocks and/or removing padding from data blocks in storage controllers 失效
标题翻译：用于填充数据块和/或从存储控制器中的数据块中删除填充的系统和方法
公开(公告)号：US07007114B1
公开(公告)日：2006-02-28
申请号：US10619954
申请日：2003-07-15
申请人： Theodore C. White , William W. Dennin , Angel G. Perozo
发明人： Theodore C. White , William W. Dennin , Angel G. Perozo
IPC分类号： G06F3/00 , G06F15/16
CPC分类号： G06F13/28 , G06F13/1673 , G06F13/1678
摘要： A method and system for processing data by a storage controller with a buffer controller coupled to a buffer memory is provided. The method includes, evaluating incoming data block size; determining if the incoming data requires padding; and padding incoming data such that the incoming data can be processed by the buffer controller. The method also includes determining if any pads need to be removed from data that is read from the buffer memory; and removing pads from the data read from the buffer memory. The buffer controller can be set in a mode to receive any MOD size data and includes a first channel with a FIFO for receiving incoming data via a first interface. The buffer controller mode for receiving incoming data can be set by firmware.
摘要翻译：提供了一种由具有耦合到缓冲存储器的缓冲器控制器的存储控制器处理数据的方法和系统。该方法包括：评估输入数据块大小; 确定输入数据是否需要填充; 并填充传入数据，使得输入数据可以由缓冲器控制器处理。该方法还包括确定是否需要从从缓冲存储器读取的数据中去除任何焊盘; 以及从缓冲存储器读取的数据中移除焊盘。可以将缓冲器控制器设置为接收任何MOD尺寸数据的模式，并且包括具有FIFO的第一通道，用于经由第一接口接收输入数据。用于接收传入数据的缓冲控制器模式可以通过固件来设置。

3. 发明授权

US08713224B2 System and method for transferring data in storage controllers 有权
标题翻译：用于在存储控制器中传输数据的系统和方法
公开(公告)号：US08713224B2
公开(公告)日：2014-04-29
申请号：US11232437
申请日：2005-09-21
申请人： Theodore C. White , William W. Dennin , Angel G. Perozo
发明人： Theodore C. White , William W. Dennin , Angel G. Perozo
IPC分类号： G06F13/10
CPC分类号： G06F13/28 , G06F13/1673 , G06F13/1678
摘要： A method and system for processing data by a storage controller with a buffer controller coupled to a buffer memory is provided. The method includes, evaluating incoming data block size; determining if the incoming data requires padding; and padding incoming data such that the incoming data can be processed by the buffer controller. The method also includes determining if any pads need to be removed from data that is read from the buffer memory; and removing pads from the data read from the buffer memory. The buffer controller can be set in a mode to receive any MOD size data and includes a first channel with a FIFO for receiving incoming data via a first interface. The buffer controller mode for receiving incoming data can be set by firmware.
摘要翻译：提供了一种由具有耦合到缓冲存储器的缓冲器控制器的存储控制器处理数据的方法和系统。该方法包括：评估输入数据块大小; 确定输入数据是否需要填充; 并填充传入数据，使得输入数据可以由缓冲器控制器处理。该方法还包括确定是否需要从从缓冲存储器读取的数据中去除任何焊盘; 以及从缓冲存储器读取的数据中移除焊盘。可以将缓冲器控制器设置为接收任何MOD尺寸数据的模式，并且包括具有FIFO的第一通道，用于经由第一接口接收输入数据。用于接收传入数据的缓冲控制器模式可以通过固件来设置。

4. 发明授权

US07730344B1 System and method for error correction 失效
标题翻译：用于纠错的系统和方法
公开(公告)号：US07730344B1
公开(公告)日：2010-06-01
申请号：US11511131
申请日：2006-08-28
申请人： Angel G. Perozo
发明人： Angel G. Perozo
IPC分类号： G06F11/00
CPC分类号： G11B20/18 , G11B20/10527 , G11B20/1833 , G11B2020/10675 , G11B2020/10685 , G11B2020/10731 , G11B2020/1843 , G11B2220/2516
摘要： An error correction system for a data storage device comprises a direct access module and a buffer control module. The direct access module receives a data stream that includes a plurality of data words from a host, generates data integrity information based on the plurality of data words, and inserts the data integrity information into the data stream. The buffer control module receives the data stream and stores the data stream to a memory.
摘要翻译：用于数据存储设备的纠错系统包括直接访问模块和缓冲器控制模块。直接访问模块从主机接收包括多个数据字的数据流，基于多个数据字生成数据完整性信息，并将数据完整性信息插入到数据流中。缓冲器控制模块接收数据流并将数据流存储到存储器中。

5. 发明授权

US07287102B1 System and method for concatenating data 有权
标题翻译：用于连接数据的系统和方法
公开(公告)号：US07287102B1
公开(公告)日：2007-10-23
申请号：US10761786
申请日：2004-01-21
申请人： Theodore C. White , William W. Dennin , Angel G. Perozo
发明人： Theodore C. White , William W. Dennin , Angel G. Perozo
IPC分类号： G06F13/00 , G06F3/00 , G06F12/00
CPC分类号： G06F3/0656 , G06F3/0608 , G06F3/0638 , G06F3/0682
摘要： A storage controller includes a first memory that stores a plurality of data blocks that include first and second noncontiguous data segments. A queue module stores data lengths and data start addresses of the first and second data segments. A read assembly module communicates with the first memory and the queue module, receives a request to read the first and second data segments from a host, reads the plurality of data blocks from the first memory, extracts the first and second data segments from the read plurality of data blocks based on the data lengths and data start addresses after the plurality of data blocks is read from the first memory, and transfers the first and second data segments contiguously to the host.
摘要翻译：存储控制器包括存储包括第一和第二非连续数据段的多个数据块的第一存储器。队列模块存储第一和第二数据段的数据长度和数据开始地址。读取组件模块与第一存储器和队列模块通信，接收从主机读取第一和第二数据段的请求，从第一存储器读取多个数据块，从读取中提取第一和第二数据段基于从第一存储器读取多个数据块之后的数据长度和数据开始地址的多个数据块，并将第一和第二数据段连续地传送到主机。

6. 发明授权

US08417900B1 Power save module for storage controllers 有权
标题翻译：存储控制器的省电模块
公开(公告)号：US08417900B1
公开(公告)日：2013-04-09
申请号：US12157212
申请日：2008-06-09
申请人： Angel G. Perozo , Theodore C. White , William W. Dennin , Aurelio J. Cruz
发明人： Angel G. Perozo , Theodore C. White , William W. Dennin , Aurelio J. Cruz
IPC分类号： G06F12/00
CPC分类号： G06F1/3203 , G06F1/3228 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： A storage controller includes a memory controller that interfaces with memory that stores data. A first receive logic interface provides an interface to a host. A second receive logic interface provides an interface to a storage device. A power save module has a power save mode in which at least a clock of the memory controller is turned off while a clock for operating the first receive logic interface and the second receive logic interface is kept on.
摘要翻译：存储控制器包括与存储数据的存储器接口的存储器控制器。第一个接收逻辑接口为主机提供接口。第二接收逻辑接口为存储设备提供接口。省电模块具有省电模式，其中在操作第一接收逻辑接口和第二接收逻辑接口的时钟保持接通时，存储器控制器的至少一个时钟被关闭。

7. 发明授权

US08370541B2 Method and system for processing frames in storage controllers 有权
标题翻译：在存储控制器中处理帧的方法和系统
公开(公告)号：US08370541B2
公开(公告)日：2013-02-05
申请号：US12886806
申请日：2010-09-21
申请人： Angel G. Perozo , William W. Dennin
发明人： Angel G. Perozo , William W. Dennin
IPC分类号： G06F3/00
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/0674
摘要： A storage drive system including an interface and a channel. The interface is configured to i) receive frames from a host and ii) process the frames. The channel is configured to i) receive the frames from the interface and ii) transfer the frames from the interface to a buffer memory. The channel includes a first register configured to store bit values corresponding to frame processing, and includes a first module configured to i) detect frame types of the frames and ii) in response to detecting a first frame type, stop receiving a second frame type while selectively continuing to receive a third frame type based on the bit values.
摘要翻译：一种包括接口和通道的存储驱动系统。该接口被配置为i）从主机接收帧，以及ii）处理帧。通道被配置为i）从接口接收帧，以及ii）将帧从接口传送到缓冲存储器。信道包括配置为存储对应于帧处理的比特值的第一寄存器，并且包括第一模块，其被配置为i）检测帧的帧类型，以及ii）响应于检测到第一帧类型，停止接收第二帧类型，同时选择性地继续基于比特值接收第三帧类型。

8. 发明授权

US07945812B1 System and method for error correction 有权
标题翻译：用于纠错的系统和方法
公开(公告)号：US07945812B1
公开(公告)日：2011-05-17
申请号：US12787484
申请日：2010-05-26
申请人： Angel G. Perozo
发明人： Angel G. Perozo
IPC分类号： G06F11/00
CPC分类号： G11B20/18 , G11B20/10527 , G11B20/1833 , G11B2020/10675 , G11B2020/10685 , G11B2020/10731 , G11B2020/1843 , G11B2220/2516
摘要： A hard disk controller includes a direct access module. The direct access module is configured to receive a data stream from a host, the data stream including a plurality of data words to be transferred to a storage device, generate data integrity information based on the plurality of data words, insert the data integrity information into the data stream prior to transmitting the data stream to a buffer memory, and transmit the data stream. A buffer control module is configured to receive the data stream including the data integrity information from the direct access module, and store the data stream in the buffer memory.
摘要翻译：硬盘控制器包括直接访问模块。直接访问模块被配置为从主机接收数据流，数据流包括要传送到存储设备的多个数据字，基于多个数据字生成数据完整性信息，将数据完整性信息插入在将数据流发送到缓冲存储器之前的数据流，并发送数据流。缓冲器控制模块被配置为从直接访问模块接收包括数据完整性信息的数据流，并将数据流存储在缓冲存储器中。

9. 发明申请

US20110022758A1 METHOD AND SYSTEM FOR PROCESSING FRAMES IN STORAGE CONTROLLERS 有权
标题翻译：存储控制器中处理框架的方法和系统
公开(公告)号：US20110022758A1
公开(公告)日：2011-01-27
申请号：US12886806
申请日：2010-09-21
申请人： Angel G. Perozo , William W. Dennin
发明人： Angel G. Perozo , William W. Dennin
IPC分类号： G06F13/24
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/0674
摘要： Method and system for transferring data between a computing system and a storage device is provided. The system includes a storage controller including a frame snooper module that detects a TMR and generates a pause signal to a channel that stops the channel from sending any non-data frames to a buffer memory, wherein the channel continues to receive and process data frames while the channel is stopped from sending the command frames to the buffer memory; a counter for counting TMRs; and logic for generating an interrupt if a number of TMRs received exceeds a certain threshold value. The method includes detecting a TMR generating a command to stop a channel from receiving non-data frames while continuing to receive data frames from a Fibre Channel interface; and generating an interrupt to a processor after a certain number of TMRs are received.
摘要翻译：提供了用于在计算系统和存储设备之间传送数据的方法和系统。该系统包括存储控制器，该存储控制器包括一个检测TMR的帧窥探模块，并产生一个暂停信号给停止信道的信道，以发送任何非数据帧到缓冲存储器，其中信道继续接收和处理数据帧，同时停止通道发送命令帧到缓冲存储器; 计数TMR的计数器; 以及用于在接收到的多个TMR超过特定阈值时产生中断的逻辑。该方法包括：在继续从光纤通道接口接收数据帧的同时，检测产生停止信道的命令以接收非数据帧的TMR; 并且在接收到一定数量的TMR之后，向处理器产生中断。

10. 发明授权

US07802026B2 Method and system for processing frames in storage controllers 有权
标题翻译：在存储控制器中处理帧的方法和系统
公开(公告)号：US07802026B2
公开(公告)日：2010-09-21
申请号：US10989060
申请日：2004-11-15
申请人： Angel G. Perozo , William W. Dennin
发明人： Angel G. Perozo , William W. Dennin
IPC分类号： G06F3/00
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/0674
摘要： Method and system for transferring data between a computing system and a storage device is provided. The system includes a storage controller including a frame snooper module that detects a TMR and generates a pause signal to a channel that stops the channel from sending any non-data frames to a buffer memory, wherein the channel continues to receive and process data frames while the channel is stopped from sending the command frames to the buffer memory; a counter for counting TMRs; and logic for generating an interrupt if a number of TMRs received exceeds a certain threshold value. The method includes detecting a TMR generating a command to stop a channel from receiving non-data frames while continuing to receive data frames from a Fiber Channel interface; and generating an interrupt to a processor after a certain number of TMRs are received.
摘要翻译：提供了用于在计算系统和存储设备之间传送数据的方法和系统。该系统包括存储控制器，该存储控制器包括一个检测TMR的帧窥探模块，并产生一个暂停信号给停止信道的信道，以发送任何非数据帧到缓冲存储器，其中信道继续接收和处理数据帧，同时停止通道发送命令帧到缓冲存储器; 计数TMR的计数器; 以及用于在接收到的多个TMR超过特定阈值时产生中断的逻辑。该方法包括：在继续从光纤通道接口接收数据帧的同时，检测产生停止信道的命令以接收非数据帧的TMR; 并且在接收到一定数量的TMR之后，向处理器产生中断。

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