专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08869121B2 Method for the translation of programs for reconfigurable architectures 有权
标题翻译：翻译可重构架构程序的方法
公开(公告)号：US08869121B2
公开(公告)日：2014-10-21
申请号：US13177820
申请日：2011-07-07
申请人： Martin Vorbach , Frank May , Armin Nückel
发明人： Martin Vorbach , Frank May , Armin Nückel
IPC分类号： G06F9/45
CPC分类号： G06F8/447
摘要： Data processing using multidimensional fields is described along with methods for advantageously using high-level language codes.
摘要翻译：描述使用多维字段的数据处理以及有利地使用高级语言代码的方法。

2. 发明授权

US08058899B2 Logic cell array and bus system 有权
标题翻译：逻辑单元阵列和总线系统
公开(公告)号：US08058899B2
公开(公告)日：2011-11-15
申请号：US12371040
申请日：2009-02-13
申请人： Martin Vorbach , Frank May , Dirk Reichardt , Frank Lier , Gerd Ehlers , Armin Nückel , Volker Baumgarte , Prashant Rao , Jens Oertel
发明人： Martin Vorbach , Frank May , Dirk Reichardt , Frank Lier , Gerd Ehlers , Armin Nückel , Volker Baumgarte , Prashant Rao , Jens Oertel
IPC分类号： H03K19/199 , G06F7/52
CPC分类号： G06F13/4027 , G06F9/3001 , G06F13/4022 , G06F15/7825 , G06F15/7867 , G06F15/80 , G06F15/8023 , G06F15/8092 , G06F15/82 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.
摘要翻译：具有多个逻辑单元的逻辑单元阵列和用于逻辑单元通信的分段总线系统，所述总线系统包括具有较短和较长段的不同段线，用于连接两个点，以便能够最小化在单独的通信开始和结束点。

3. 发明申请

US20120311301A1 PIPELINE CONFIGURATION PROTOCOL AND CONFIGURATION UNIT COMMUNICATION 有权
标题翻译：管道配置协议和配置单元通信
公开(公告)号：US20120311301A1
公开(公告)日：2012-12-06
申请号：US13491894
申请日：2012-06-08
申请人： Martin VORBACH , Volker Baumgarte , Gerd Ehlers , Frank May , Armin Nückel
发明人： Martin VORBACH , Volker Baumgarte , Gerd Ehlers , Frank May , Armin Nückel
IPC分类号： G06F15/76
CPC分类号： G06F15/7867 , G06F9/3885 , G06F9/3897
摘要： In a method of synchronizing data processing of processor arrangement, responsive to reaching, during execution of a program, a barrier included in a program sequence, the processor arrangement halts the program execution until it is determined that all instructions preceding the barrier in the program sequence have been successfully scheduled for execution.
摘要翻译：在一种使处理器装置的数据处理同步的方法中，响应于在程序执行期间到达包括在程序序列中的屏障，处理器装置停止程序执行，直到确定程序序列中的屏障之前的所有指令已经成功安排执行。

4. 发明授权

US08312200B2 Processor chip including a plurality of cache elements connected to a plurality of processor cores 有权
标题翻译：处理器芯片包括连接到多个处理器核心的多个高速缓存元件
公开(公告)号：US08312200B2
公开(公告)日：2012-11-13
申请号：US12840477
申请日：2010-07-21
申请人： Martin Vorbach , Armin Nückel
发明人： Martin Vorbach , Armin Nückel
IPC分类号： G06F13/20
CPC分类号： G06F15/80 , G06F8/433 , G06F8/45 , G06F15/7867
摘要： Programming of modules which can be reprogrammed during operation is described. Partitioning of code sequences is also described.
摘要翻译：描述可在操作期间重新编程的模块的编程。还描述了代码序列的分区。

5. 发明授权

US08471593B2 Logic cell array and bus system 有权
公开(公告)号：US08471593B2
公开(公告)日：2013-06-25
申请号：US13289296
申请日：2011-11-04
申请人： Martin Vorbach , Frank May , Dirk Reichardt , Frank Lier , Gerd Ehlers , Armin Nückel , Volker Baumgarte , Prashant Rao , Jens Oertel
发明人： Martin Vorbach , Frank May , Dirk Reichardt , Frank Lier , Gerd Ehlers , Armin Nückel , Volker Baumgarte , Prashant Rao , Jens Oertel
IPC分类号： G06F7/52
CPC分类号： G06F13/4027 , G06F9/3001 , G06F13/4022 , G06F15/7825 , G06F15/7867 , G06F15/80 , G06F15/8023 , G06F15/8092 , G06F15/82 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.

6. 发明授权

US08468329B2 Pipeline configuration protocol and configuration unit communication 有权
标题翻译：管道配置协议和配置单元通信
公开(公告)号：US08468329B2
公开(公告)日：2013-06-18
申请号：US13491894
申请日：2012-06-08
申请人： Martin Vorbach , Volker Baumgarte , Gerd Ehlers , Frank May , Armin Nückel
发明人： Martin Vorbach , Volker Baumgarte , Gerd Ehlers , Frank May , Armin Nückel
IPC分类号： G06F11/07
CPC分类号： G06F15/7867 , G06F9/3885 , G06F9/3897
摘要： In a method of synchronizing data processing of processor arrangement, responsive to reaching, during execution of a program, a barrier included in a program sequence, the processor arrangement halts the program execution until it is determined that all instructions preceding the barrier in the program sequence have been successfully scheduled for execution.
摘要翻译：在一种使处理器装置的数据处理同步的方法中，响应于在程序执行期间到达包括在程序序列中的屏障，处理器装置停止程序执行，直到确定程序序列中的屏障之前的所有指令已经成功安排执行。

7. 发明申请

US20100228918A1 CONFIGURABLE LOGIC INTEGRATED CIRCUIT HAVING A MULTIDIMENSIONAL STRUCTURE OF CONFIGURABLE ELEMENTS 有权
公开(公告)号：US20100228918A1
公开(公告)日：2010-09-09
申请号：US12720898
申请日：2010-03-10
申请人： MARTIN VORBACH , Armin Nückel
发明人： MARTIN VORBACH , Armin Nückel
IPC分类号： G06F15/80 , G06F9/06 , G06F12/00 , G06F12/08
CPC分类号： G06F15/80 , G06F8/433 , G06F8/45 , G06F15/7867
摘要： Programming of modules which can be reprogrammed during operation is described. Partitioning of code sequences is also described.

8. 发明申请

US20090210653A1 METHOD AND DEVICE FOR TREATING AND PROCESSING DATA 审中-公开
标题翻译：用于处理和处理数据的方法和设备
公开(公告)号：US20090210653A1
公开(公告)日：2009-08-20
申请号：US12389116
申请日：2009-02-19
申请人： Martin Vorbach , Volker Baumgarte , Armin Nückel , Frank May
发明人： Martin Vorbach , Volker Baumgarte , Armin Nückel , Frank May
IPC分类号： G06F15/80 , G06F9/06
CPC分类号： G06F15/8046
摘要： Procedures and methods for managing and transmitting data within multidimensional systems of transmitters and receivers are described. Splitting a data stream into a plurality of independent branches and subsequent merging of the individual branches to form a data stream is to be performable in a simple manner, the individual data streams being recombined in the correct sequence. This method may be particularly useful for executing reentrant code. The method is well suited, in particular, for configurable architectures; particular attention is paid to the efficient control of configuration and reconfiguration.
摘要翻译：描述了在发射机和接收机的多维系统内管理和传输数据的过程和方法。将数据流分解成多个独立分支并且随后各个分支的合并以形成数据流可以以简单的方式执行，单个数据流以正确的顺序重新组合。该方法对于执行可重入代码可能特别有用。该方法特别适用于可配置架构; 特别注意配置和重新配置的有效控制。

9. 发明申请

US20120072699A1 LOGIC CELL ARRAY AND BUS SYSTEM 有权
标题翻译：逻辑单元阵列和总线系统
公开(公告)号：US20120072699A1
公开(公告)日：2012-03-22
申请号：US13289296
申请日：2011-11-04
申请人： Martin VORBACH , Frank May , Dirk Reichardt , Frank Lier , Gerd Ehlers , Armin Nückel , Volker Baumgarte , Prashant Rao , Jens Oertel
发明人： Martin VORBACH , Frank May , Dirk Reichardt , Frank Lier , Gerd Ehlers , Armin Nückel , Volker Baumgarte , Prashant Rao , Jens Oertel
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F13/4027 , G06F9/3001 , G06F13/4022 , G06F15/7825 , G06F15/7867 , G06F15/80 , G06F15/8023 , G06F15/8092 , G06F15/82 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.
摘要翻译：具有多个逻辑单元的逻辑单元阵列和用于逻辑单元通信的分段总线系统，所述总线系统包括具有较短和较长段的不同段线，用于连接两个点，以便能够最小化在单独的通信开始和结束点。

10. 发明授权

US07996827B2 Method for the translation of programs for reconfigurable architectures 有权
标题翻译：翻译可重构架构程序的方法
公开(公告)号：US07996827B2
公开(公告)日：2011-08-09
申请号：US10486771
申请日：2002-08-16
申请人： Martin Vorbach , May Frank , Armin Nückel
发明人： Martin Vorbach , May Frank , Armin Nückel
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/447
摘要： A method for advantageously translating high-level language codes for data processing using a reconfigurable architecture, memories addressable internally from within said reconfigurable architecture, and memories external to said reconfigurable architecture, may include constructing a finite automaton for computation in such a way that a complex combinatory network of individual functions is formed, assigning memories to the network for storage of operands and results, and separating external memory accesses for providing a transfer of at least one of operands and results as data from an external memory to a memory addressable internally by the reconfigurable architecture.
摘要翻译：一种用于有利地翻译用于使用可重新配置架构的数据处理的高级语言代码的方法，可从内部从所述可重新配置架构内寻址的存储器和所述可重新配置架构外部的存储器的方法可以包括构建用于计算的有限自动机，形成各个功能的组合网络，将存储器分配给存储操作数和结果的存储器，以及分离外部存储器存取，以提供作为数据的操作数和结果中的至少一个的操作数和结果的传输从外部存储器到内部可寻址的存储器可重构架构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式