专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08936995B2 Methods of fabricating isolation regions of semiconductor devices and structures thereof 有权
标题翻译：制造半导体器件的隔离区域的方法及其结构
公开(公告)号：US08936995B2
公开(公告)日：2015-01-20
申请号：US11365226
申请日：2006-03-01
申请人： Armin Tilke , Marcus Culmsee , Chris Stapelmann , Bee Kim Hong , Roland Hampp
发明人： Armin Tilke , Marcus Culmsee , Chris Stapelmann , Bee Kim Hong , Roland Hampp
IPC分类号： H01L21/762 , H01L21/77
CPC分类号： H01L29/0649 , H01L21/02271 , H01L21/76229 , H01L21/76232
摘要： Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.
摘要翻译：公开了制造半导体器件的隔离区域的方法及其结构。在优选实施例中，半导体器件包括工件和形成在工件中的至少一个沟槽。所述至少一个沟槽包括侧壁，底面，下部和上部。第一衬垫设置在所述至少一个沟槽的侧壁和底表面上。第二衬垫设置在至少一个沟槽的下部中的第一衬垫之上。第一绝缘材料设置在至少一个沟槽的下部中的第二衬垫上。第二绝缘材料设置在至少一个沟槽的上部中的第一绝缘材料之上。第一衬垫，第二衬垫，第一绝缘材料和第二绝缘材料包括半导体器件的隔离区域。

2. 发明授权

US08476686B2 Memory device and method for making same 有权
标题翻译：存储器件及其制作方法
公开(公告)号：US08476686B2
公开(公告)日：2013-07-02
申请号：US12169648
申请日：2008-07-09
申请人： Armin Tilke
发明人： Armin Tilke
IPC分类号： H01L27/24
CPC分类号： H01L29/66242 , H01L27/1026 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： An embodiment relates to a memory cell comprising a programmable resistance memory element electrically coupled to a heterojunction bipolar transistor.
摘要翻译：一个实施例涉及一种包含电耦合到异质结双极晶体管的可编程电阻存储元件的存储单元。

3. 发明授权

US08031532B2 Methods of operating embedded flash memory devices 有权
标题翻译：操作嵌入式闪存设备的方法
公开(公告)号：US08031532B2
公开(公告)日：2011-10-04
申请号：US12709982
申请日：2010-02-22
申请人： Danny Pak-Chum Shum , Armin Tilke , Jiang Yan
发明人： Danny Pak-Chum Shum , Armin Tilke , Jiang Yan
IPC分类号： G11C16/04 , H01L29/788
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer lithography masks and may be implemented in stand-alone flash memory devices, embedded flash memory devices, and system on a chip (SoC) flash memory devices.
摘要翻译：公开了闪存器件结构及其制造方法。闪存器件是在绝缘体上硅（SOI）衬底上制造的。使用浅沟槽隔离（STI）区域和SOI衬底的掩埋氧化物层来隔离相邻器件。制造方法需要更少的光刻掩模，并且可以在独立的闪存器件，嵌入式闪存器件以及片上系统（SoC）闪存器件中实现。

4. 发明申请

US20100207238A1 Semiconductor Devices and Methods of Manufacture Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100207238A1
公开(公告)日：2010-08-19
申请号：US12769271
申请日：2010-04-28
申请人： Armin Tilke , Cajetan Wagner , Lincoln O'Riain
发明人： Armin Tilke , Cajetan Wagner , Lincoln O'Riain
IPC分类号： H01L29/06
CPC分类号： H01L21/76264 , H01L21/743
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，半导体器件包括具有设置在工件的顶部下方的掩埋层的工件。隔离环结构设置在工件的顶部部分内，完全延伸穿过掩埋层的至少一部分，隔离环结构包括具有内部区域的环。扩散限制结构设置在隔离环结构的内部区域内。导电区域设置在隔离环结构的内部的一部分内的工件的顶部内，导电区域包括注入并扩散到工件顶部的至少一个掺杂元素。扩散限制结构限定了导电区域的至少一个边缘，并且导电区域耦合到掩埋层。

5. 发明授权

US07687347B2 Embedded flash memory devices on SOI substrates and methods of manufacture thereof 有权
标题翻译： SOI衬底上的嵌入式闪存器件及其制造方法
公开(公告)号：US07687347B2
公开(公告)日：2010-03-30
申请号：US12360985
申请日：2009-01-28
申请人： Danny Pak-Chum Shum , Armin Tilke , Jiang Yan
发明人： Danny Pak-Chum Shum , Armin Tilke , Jiang Yan
IPC分类号： H01L21/336 , H01L21/82 , H01L21/00 , H01L21/84 , G11C7/00
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer lithography masks and may be implemented in stand-alone flash memory devices, embedded flash memory devices, and system on a chip (SoC) flash memory devices.
摘要翻译：公开了闪存器件结构及其制造方法。闪存器件是在绝缘体上硅（SOI）衬底上制造的。使用浅沟槽隔离（STI）区域和SOI衬底的掩埋氧化物层来隔离相邻器件。制造方法需要更少的光刻掩模，并且可以在独立的闪存器件，嵌入式闪存器件以及片上系统（SoC）闪存器件中实现。

6. 发明授权

US07495279B2 Embedded flash memory devices on SOI substrates and methods of manufacture thereof 有权
标题翻译： SOI衬底上的嵌入式闪存器件及其制造方法
公开(公告)号：US07495279B2
公开(公告)日：2009-02-24
申请号：US11223235
申请日：2005-09-09
申请人： Danny Pak-Chum Shum , Armin Tilke , Jiang Yan
发明人： Danny Pak-Chum Shum , Armin Tilke , Jiang Yan
IPC分类号： H01L29/76
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11526 , H01L27/11546
摘要： Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer lithography masks and may be implemented in stand-alone flash memory devices, embedded flash memory devices, and system on a chip (SoC) flash memory devices.
摘要翻译：公开了闪存器件结构及其制造方法。闪存器件是在绝缘体上硅（SOI）衬底上制造的。使用浅沟槽隔离（STI）区域和SOI衬底的掩埋氧化物层来隔离相邻器件。制造方法需要更少的光刻掩模，并且可以在独立的闪存器件，嵌入式闪存器件以及片上系统（SoC）闪存器件中实现。

7. 发明申请

US20090001502A1 Semiconductor Devices and Methods of Manufacture Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090001502A1
公开(公告)日：2009-01-01
申请号：US11771583
申请日：2007-06-29
申请人： Armin Tilke , Cajetan Wagner , Lincoln O'Riain
发明人： Armin Tilke , Cajetan Wagner , Lincoln O'Riain
IPC分类号： H01L29/00 , H01L21/762
CPC分类号： H01L21/76264 , H01L21/743
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the top portion of the workpiece extending completely through at least a portion of the buried layer, the isolation ring structure comprising a ring having an interior region. A diffusion confining structure is disposed within the interior region of the isolation ring structure. A conductive region is disposed within the top portion of the workpiece within a portion of the interior of the isolation ring structure, the conductive region comprising at least one dopant element implanted and diffused into the top portion of the workpiece. The diffusion confining structure defines at least one edge of the conductive region, and the conductive region is coupled to the buried layer.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，半导体器件包括具有设置在工件的顶部下方的掩埋层的工件。隔离环结构设置在工件的顶部部分内，完全延伸穿过掩埋层的至少一部分，隔离环结构包括具有内部区域的环。扩散限制结构设置在隔离环结构的内部区域内。导电区域设置在隔离环结构的内部的一部分内的工件的顶部内，导电区域包括注入并扩散到工件顶部的至少一个掺杂元素。扩散限制结构限定了导电区域的至少一个边缘，并且导电区域耦合到掩埋层。

8. 发明申请

US20080254204A1 DIELECTRIC APPARATUS AND ASSOCIATED METHODS 有权
标题翻译：电介质和相关方法
公开(公告)号：US20080254204A1
公开(公告)日：2008-10-16
申请号：US11735607
申请日：2007-04-16
申请人： Chris Stapelmann , Gert Jaschke , Armin Tilke
发明人： Chris Stapelmann , Gert Jaschke , Armin Tilke
IPC分类号： B05D5/12
CPC分类号： H01L21/02356 , H01L21/02142 , H01L21/02164 , H01L21/02172 , H01L21/0228 , H01L21/28194 , H01L21/3105 , H01L21/3141 , H01L21/31604 , H01L21/31641 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L29/78
摘要： In an embodiment of the invention, an amorphous phase dielectric material is selectively formed over a substrate. The amorphous phase dielectric material is then converted into a crystalline phase dielectric material.
摘要翻译：在本发明的一个实施例中，在衬底上选择性地形成非晶相介质材料。然后将非晶相介电材料转化为结晶相电介质材料。

9. 发明授权

US07005723B2 Bipolar transistor and method of producing same 失效
标题翻译：双极晶体管及其制造方法
公开(公告)号：US07005723B2
公开(公告)日：2006-02-28
申请号：US10764264
申请日：2004-01-23
申请人： Armin Tilke , Kristin Schupke
发明人： Armin Tilke , Kristin Schupke
IPC分类号： H01L27/082
CPC分类号： H01L29/66242 , H01L29/0817 , H01L29/41708 , H01L29/7378
摘要： In a method of producing a bipolar transistor, a semiconductor substrate having a substrate surface is provided. A base-terminal layer for providing a base terminal is formed on the substrate surface, and an emitter window having a wall area is formed in the base-terminal layer. A first spacing layer is formed on the wall area of the emitter contact window, and a recess is etched into the substrate within a window specified by the first spacing layer. A base layer contacted by outdiffusion from the base-terminal layer is formed in the recess of the emitter window, and a second spacing layer is formed on the first spacing layer and on the base layer. The second spacing layer is structured for the purpose of specifying a planar terminal pad on the base layer, and an emitter layer is formed on the planar terminal pad.
摘要翻译：在制造双极晶体管的方法中，提供具有基板表面的半导体基板。在基板表面上形成用于提供基极端子的基极端子层，并且在基极端子层中形成具有壁区域的发射极窗口。第一间隔层形成在发射体接触窗口的壁区域上，并且在由第一间隔层指定的窗口内将凹槽蚀刻到衬底中。在发射器窗口的凹部中形成从基极端子层向外扩散接触的基底层，并且在第一间隔层和基底层上形成第二间隔层。第二间隔层被构造用于在基底层上指定平面端子焊盘，并且在平面端子焊盘上形成发射极层。

10. 发明授权

US07001806B2 Semiconductor structure with increased breakdown voltage and method for producing the semiconductor structure 失效
标题翻译：具有增加的击穿电压的半导体结构和用于制造半导体结构的方法
公开(公告)号：US07001806B2
公开(公告)日：2006-02-21
申请号：US10780276
申请日：2004-02-17
申请人： Armin Tilke , Wolfgang Klein
发明人： Armin Tilke , Wolfgang Klein
IPC分类号： H01L21/8238
CPC分类号： H01L21/8222 , H01L27/0825 , H01L29/0821 , H01L29/732
摘要： A semiconductor structure comprises a buried first semiconductor layer of a first doping type, a second semiconductor layer of the first doping type on the buried semiconductor layer, which is less doped than the buried first semiconductor layer, a semiconductor area of a second doping type on the second semiconductor layer, so that a pn junction is formed between the semiconductor area and the second semiconductor layer, and a recess present below the semiconductor area in the buried first semiconductor layer, which comprises a semiconductor material of the first doping type, which can be less doped than the buried first semiconductor layer and has a larger distance to the semiconductor area of the second doping type on the second semiconductor layer, such that the breakdown voltage across the pn junction is higher than if the recess were not provided. Thereby, it is achieved that both a semiconductor structure with a desired breakdown voltage as well as a further semiconductor structure without this recess can be generated in the buried first semiconductor layer with optimized HF properties.
摘要翻译：半导体结构包括第一掺杂类型的掩埋的第一半导体层，在掩埋半导体层上的第一掺杂类型的第二半导体层，其比掩埋的第一半导体层掺杂的掺杂少，第二掺杂类型的半导体区域第二半导体层，使得在半导体区域和第二半导体层之间形成pn结，以及存在于掩埋的第一半导体层中的半导体区域下方的凹部，其包括第一掺杂型半导体材料，其可以比埋入的第一半导体层的掺杂少，并且在第二半导体层上具有比第二掺杂类型的半导体区域更大的距离，使得跨越pn结的击穿电压高于未设置凹部的击穿电压。由此，可以在具有优化的HF性质的掩埋的第一半导体层中产生具有期望的击穿电压的半导体结构以及没有该凹槽的另外的半导体结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式